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STP10NM60N, STU10NM60N
N-channel 600 V, 0.53 , 10 A, DPAK, TO-220, TO-220FP, IPAK
MDmesh II Power MOSFET
Features
VDSS RDS(on)
Order codes ID Pw
@TJmax max.
3 3
STD10NM60N 70 W 2 2
1 1
STF10NM60N 25 W TO-220 TO-220FP
650 V < 0.55 10 A
STP10NM60N
70 W
STU10NM60N
3
100% avalanche tested 2 3
1 1
Low input capacitance and gate charge
IPAK DPAK
Low gate input resistance
Application
Switching applications Figure 1. Internal schematic diagram
Description $
These devices are N-channel 600 V Power
MOSFET realized using the second generation of
MDmesh technology. It applies the benefits of
the multiple drain process to STMicroelectronics
well-known PowerMESH horizontal layout '
structure. The resulting product offers improved
on-resistance, low gate charge, high dv/dt
capability and excellent avalanche characteristics.
3
!-V
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ........................... 6
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1 Electrical ratings
2 Electrical characteristics
Drain-source
V(BR)DSS ID = 1 mA, VGS = 0 600 V
breakdown voltage
Zero gate voltage VDS = max rating 1 A
IDSS
drain current (VGS = 0) VDS = max rating, TC=125 C 100 A
Gate-body leakage
IGSS VGS = 25 V; VDS=0 100 nA
current (VDS = 0)
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 A 2 3 4 V
Static drain-source on
RDS(on) VGS = 10 V, ID = 4 A 0.53 0.55
resistance
Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Ciss 540 pF
Output capacitance VDS = 50 V, f = 1 MHz,
Coss - 44 - pF
Reverse transfer VGS = 0
Crss 1.2 pF
capacitance
Equivalent
Coss eq(1) capacitance time VDS = 0 to 480 V, VGS = 0 - 110 - pF
related
Rg Gate input resistance f=1 MHz open drain - 6 -
Qg Total gate charge VDD = 480 V, ID = 8 A, 19 nC
Qgs Gate-source charge VGS = 10 V - 3 - nC
Qgd Gate-drain charge (see Figure 17) 10 nC
1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
when VDS increases from 0 to 80% VDSS
1s
10
10s
is
R rea
)
on
100s
S(
ax a
D
m this
by n
1
d ni
1ms
ite io
m at
Li per
O
10ms
Tj=150C
0.1
Tc=25C
Sinlge
pulse
0.01
0.1 1 10 100 VDS(V)
Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP
AM03945v1
ID
(A)
10
is
R rea
)
on
10s
S(
ax a
D
m his
by t
d in
100s
ite on
m ti
Li era
1
p
1ms
O
10ms
Tj=150C
0.1 Tc=25C
Single
pulse
0.01
0.1 1 10 100 VDS(V)
Figure 6. Safe operating area for DPAK, IPAK Figure 7. Thermal impedance for DPAK, IPAK
AM03944v1
ID
(A)
1s
10
10s
is
R rea
)
on
100s
S(
ax a
D
m this
by n
1
d ni
1ms
ite io
m at
Li per
O
10ms
Tj=150C
0.1
Tc=25C
Sinlge
pulse
0.01
0.1 1 10 100 VDS(V)
10 10
8 8
6 6
5V
4 4
2 2
4V
0 0
0 5 10 15 20 25 30 VDS(V) 0 2 4 6 8 10 VGS(V)
Figure 10. Normalized BVDSS vs temperature Figure 11. Static drain-source on resistance
BVDSS AM03955v1 AM00891v1
RDS(on)
(norm) ()
1.07 ID=1mA
0.56
1.05
1.03 0.52
1.01
0.48
0.99 VGS=10V
0.97
0.44
0.95
0.93 0.40
-50 -25 0 25 50 75 100 TJ(C) 0 2 4 6 8 ID(A)
Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations
AM03951v1 AM03952v1
VGS C
(V) (pF)
VDD=480V VGS
12
ID=4A
VDS 1000
10 Ciss
8
100
6
Coss
4 10
2 Crss
0 1
0 5 10 15 20 Qg(nC) 0.1 1 10 100 VDS(V)
Figure 14. Normalized gate threshold voltage Figure 15. Normalized on resistance vs
vs temperature temperature
VGS(th) AM03953v1
RDS(on) AM03954v1
(norm) ID=250A (norm)
1.10 2.1
ID=4A
1.9 VGS=10V
1.00 1.7
1.5
1.3
0.90
1.1
0.80 0.9
0.7
0.70 0.5
-50 -25 0 25 50 75 100 TJ(C) -50 -25 0 25 50 75 100 TJ(C)
3 Test circuits
Figure 16. Switching times test circuit for Figure 17. Gate charge test circuit
resistive load
VDD
12V 47k
1k
100nF
RL 2200 3.3
F F
VDD IG=CONST
VD Vi=20V=VGMAX 100 D.U.T.
VGS 2200
RG D.U.T. F 2.7k VG
PW
47k
PW 1k
AM01468v1 AM01469v1
Figure 18. Test circuit for inductive load Figure 19. Unclamped inductive load test
switching and diode recovery times circuit
L
A A A
D
FAST L=100H VD
G D.U.T. DIODE 2200 3.3
F F VDD
S B 3.3 1000
B B F F
25 VDD ID
D
RG S
Vi D.U.T.
Pw
AM01470v1 AM01471v1
Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform
V(BR)DSS ton toff
tr tdoff tf
VD tdon
90% 90%
IDM
10%
ID 10% VDS
0
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
F1 1.15 1.70
F2 1.15 1.70
G 4.95 5.2
G1 2.4 2.7
H 10 10.4
L2 16
L3 28.6 30.6
L4 9.8 10.6
L5 2.9 3.6
L6 15.9 16.4
L7 9 9.3
Dia 3 3.2
L7
A
B
D
Dia
L5
L6
F1 F2
H G
G1
L2 L4
L3
7012510_Rev_K
mm.
DIM.
min. ty p ma x .
A 2.20 2.40
A1 0.90 1.10
A2 0.03 0.23
b 0.64 0.90
b4 5.20 5.40
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
D1 5.10
E 6.40 6.60
E1 4. 70
e 2.28
e1 4.40 4.60
H 9.35 10.10
L 1
L1 2.80
L2 0.80
L4 0.60 1
R 0.20
V2 0o 8o
0068772_G
mm
Dim
Min Typ Max
A 4.40 4.60
b 0.61 0.88
b1 1.14 1.70
c 0.48 0.70
D 15.25 15.75
D1 1.27
E 10 10.40
e 2.40 2.70
e1 4.95 5.15
F 1.23 1.32
H1 6.20 6.60
J1 2.40 2.72
L 13 14
L1 3.50 3.93
L20 16.40
L30 28.90
P 3.75 3.85
Q 2.65 2.95
0015988_Rev_S
mm.
DIM.
min. typ max.
A 2.20 2.40
A1 0.90 1.10
b 0.64 0.90
b2 0.95
b4 5.20 5.40
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
E 6.40 6.60
e 2.28
e1 4.40 4.60
H 16.10
L 9.00 9.40
(L1) 0.80 1.20
L2 0.80
V1 10 o
0068771_H
DPAK FOOTPRINT
6 Revision history
12
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