1.4.2 Problem 2: Write a Verilog code to implement Multiplexer.

The following points should be taken care of:

1. Use ternary operator to design 2x1 Mux

PROGRAM :

module mux2x1(out,i0,i1,s);

output out;

input i0,i1;

input s;

assign out=s?i1:i0;

endmodule

TEST BENCH :

module mux2x1_tb_v;

// Inputs

reg i0;

reg i1;

reg s;

// Outputs

wire out;

// Instantiate the Unit Under Test (UUT)

mux2x1 uut (

.out(out),

.i0(i0),

.i1(i1),

.s(s)

);

initial begin

// Initialize Inputs
 #100 s=0; i0=0; i1=1;

#100 s=1; i0=0; i1=1;

#100 s=0; i0=1; i1=0;

#100 s=1; i0=1; i1=0;

// Add stimulus here

end

endmodule

WAVEFORM :
 2. Use initial and always statement to design 4x1 Mux

PROGRAM :

module mux4x1(y,s,i);

output y;

input[3:0]i;

input[1:0]s;

reg y;

always@(s,i)

begin

case(s)

2'b00:y=i[0];

2'b01:y=i[1];

2'b10:y=i[2];

2'b11:y=i[3];

endcase

end

endmodule

TEST BENCH :

module mux4x1_tb_v;

// Inputs

reg [1:0] s;

reg [3:0] i;

// Outputs

wire y;

// Instantiate the Unit Under Test (UUT)

mux4x1 uut (

.y(y),
 .s(s),

.i(i)

);

initial begin

// Initialize Inputs

#100 s = 0; i = 0;

#100 s = 0; i = 1;

#100 s = 1; i = 0;

#100 s = 1; i = 1;

end

endmodule

WAVEFORM :
 3. Use Gate Level Model to design 8x1 Mux using two 4x1 Mux and one 2x1 Mux

PROGRAM :

module mux8x1(out,s,i);

output out;

input[7:0]i;

input[2:0]s;

wire w1,w2;

mux4x1 m1(w1,i[3:0],s[1:0]);

mux4x1 m2(w2,i[7:4],s[1:0]);

mux2x1 m3(out,w1,w2,s[2]);

endmodule

TEST BENCH :

module mux8x1_tb_v;

// Inputs

reg [2:0] s;

reg [7:0] i;

// Outputs

wire out;

// Instantiate the Unit Under Test (UUT)

mux8x1 uut (

.out(out),

.s(s),

.i(i)

);

initial begin

// Initialize Inputs
 #100 s=0;i=0;

#100 s=0;i=1;

#100 s=1;i=0;

#100 s=1;i=1;

#100 s=2;i=0;

#100 s=2;i=1;

// Add stimulus here

end

endmodule

WAVEFORM :