Department of Electronics Engineering,

Zakir Hussain College of Engineering &

Technology, Aligarh Muslim University, Aligarh-
202002

CERTIFICATE
This is to certify that dissertation entitled, Design Of Key Analog
Building Blocks Using FinFETs submitted by Ekta Sharma in partial
fulfillment of the requirements for the award of degree of Master of
Technology in Electronics Engineering (Electronic Circuits and Systems
Design) to the Department of Electronics Engineering , AMU Aligarh is an
authentic record of work carried out by her under our supervision and
guidance.

Prof. Mohd. Hasan Dr. Naushad Alam

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 ACKNOWLEDGEMENT

I would like to express my sincere and heartfelt gratitude to my

supervisors Prof. Mohd. Hasan and Dr. Naushad Alam , for allowing me to
do this work under their valuable guidance.. It would have been impossible on
my part to come out with this dissertation work without their inspiration and
valuable suggestions throughout this whole work.
I would like to thank all the authors, reading whose papers and books, I
gained much enough knowledge to understand and carry out my work.
I am also thankful to my family and friends who encouraged and
supported me in my work.
Last but not the least, I am very much grateful to Almighty for
bestowing upon me patience and faith in myself to complete this work.

Ekta Sharma
Faculty No. 15-LEEM-030
Enrolment No. GI-4777

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 ABSTRACT

A simple alpha power law model for FinFET was proposed in preliminary dissertation
work which is being used for automatic design of CMOS Inverting Amplifier using
FinFETs in this dissertation using MATLAB and HSPICE software.
In addition to this, gm - ID method is also used for design of Single Stage Miller
Operational Amplifier(OP-AMP) using resistive load and Two Stage miller OP-AMP
with active load using Pre-Computed Lookup Tables, utilising the same softwares.
Main focus is on specification of Bandwidth, Gain and Phase Margin. The idea can be
further extended to more specifications in future work.
BSIM-CMG 20nm model is used for FinFET. HSPICE toolbox is used for the
simulation purpose in MATLAB.

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 TABLE OF CONTENTS
List of abbreviations & Symbols
List of Figures
List of Tables
Motivation __________________________________________________________________ 1

CHAPTER 1: FinFET __________________________________________________ 2

1.1 Structure and functioning of FinFET____________________________________ 3
1.2 BSIM-CMG model _________________________________________________ 4
1.3 List of physical effects modelled in BSIM-CMG _________________________ 4-5
1.4 Advantages of FinFET over MOSFET __________________________________ 6
1.5 Literature review ________________________________________________ 10-11

CHAPTER 2: GM-ID Starter kit for FinFET ______________________________ 12

2.1 General information ________________________________________________ 13
2.2 Why design analog circuits using FinFETs? ____________________________ 13
2.3 How the design kit works? __________________________________________ 13
2.4 Files detail in Starter kit for FinFET __________________________________ 14
2.5 Files explanation & how to proceed with starter kit ____________________ 14-19
2.6 gm/ID centric technology characterization____________________________ 19-22
2.7 Summary of whole design kit ________________________________________ 22

CHAPTER 3: Proposed Alpha Power Law model __________________________ 23

3.1 Shockley model (for MOSFET) ______________________________________ 24
3.2 Limitations of Shockley model and solution ___________________________ 24-25
3.3 FinFET model ____________________________________________________ 26
3.3.1 Proposed FinFET model description ______________________________ 26
3.3.2 Parameter extraction & curve fitting ______________________________ 26
3.3.2.1 Extraction of B ______________________________________ 27-28
3.3.2.2 Extraction of _________________________________________ 28
3.3.2.3 Extraction of Vth _______________________________________ 29
3.3 2.4 Extraction of K and m _______________________________ 29-30
3.3.3 Extracted parameter values _________________________________________ 30
3.3.4 Results of alpha power law model _________________________________ 30-32

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CHAPTER 4: Analog design & gm/ID design methodology __________________ 33
4.1 Analog design ____________________________________________________ 34
4.1.1 Performance metrics of analog design _____________________________ 34
4.1.2 Regions of transistor operation _________________________________ 34-35
4.2 gm/ID design methodology __________________________________________ 35
4.2.1 Basic description____________________________________________ 35-36
4.2.2 Key features of gm/ID method _________________________________ 36-37
4.2.3 Steps in gm/ID method ________________________________________ 37
4.2.3.1 For bandwidth specification _______________________________ 37
4.2.3.2 For gain specification ____________________________________ 37

CHAPTER 5: Results for validation of gm/ID starter kit for FinFET _________ 38
5.1 CMOS Inverting Amplifier __________________________________________ 39
5.1.1 Design using FinFET alpha power law model _____________________ 40-41
5.1.1.1 Results _____________________________________________ 41-42
5.1.2 Design using gm/ID technique __________________________________ 42
5.1.2.1 Results _______________________________________________ 43
5.2 Single stage Miller OP-AMP with resistive load _________________________ 44
5.2.1 Design using gm/ID technique __________________________________ 45
5.2.2 Results __________________________________________________ 46-48
5.3 Two stage Miller OP-AMP________________________________________ 48-50
5.3.1 Design using gm/ID technique ________________________________ 50-51
5.3.2 Results __________________________________________________ 52-53
6 Conclusion and future work __________________________________________ 54

REFERENCES _____________________________________________________ 55-57

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 List of abbreviations & Symbols
= Intrinsic gate capacitance

ID = drain current,
= mobility of electrons(or holes in case of PMOS),
= drain-source voltage,
= gate-source voltage,
Cox = oxide capacitance per unit area,
Vdsat = drain saturation voltage,
Vth = threshold voltage of transistor,
W = width of MOSFET,
L = length of MOSFET.
Vov = Overdrive voltage
= channel length modulation parameter

GDS = output conductance

KB = Boltzmann constant

T = Temperature

ro = output resistance

ft = transit frequency

NFIN = Number of fins

VT = Thermal voltage

CMR = Common mode range

= process transconductance parameter

CL = Load capacitance

CC = Compensation capacitance

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 LIST OF FIGURES

Fig. 1.1 Structure of FinFET _____________________________________________ 3

Fig. 1.2(a) Triple gate FinFET on SOI _____________________________________ 3
Fig. 1.2(b) Double gate FinFET on SOI ____________________________________ 3
Fig. 1.2(c) Triple gate FinFET on Bulk Silicon ______________________________ 4
Fig. 1.2(d) Planar double gate FinFET _____________________________________ 4
Fig. 1.2 Different Multi gate FinFET architectures __________________________ 4
Fig. 1.3 Planar FET ____________________________________________________ 6
Fig. 1.4 FinFET ______________________________________________________ 6
Fig. 1.5 Output conductance at VDS = 1.2V & VOV = 0.2V ____________________ 7
Fig. 1.6 Voltage gain at VDS = 1.2V & VOV = 0.2V _________________________ 7
Fig. 1.7 gm vs VGS ___________________________________________________ 8
Fig. 1.8 gm/IDS vs IDS ________________________________________________ 8
Fig. 1.9 Intrinsic gain vs Current density ____________________________________ 9
Fig. 1.10 Cutoff frequency vs Current density _______________________________ 9
Fig. 2.1 Basic analog design description ___________________________________ 13
Fig. 2.2 ID-VGS characteristics plotted in MATLAB ________________________ 18
Fig. 2.3 ID-VDS characteristics plotted in MATLAB ________________________ 19
Fig. 2.4 Transcnductance efficiency vs VGS ________________________________ 19
Fig. 2.5 Transit frequency chart for varying length and NFIN=1 ________________ 20
Fig. 2.6 Intrinsic gain chart for varying length and NFIN=1 ___________________ 20
Fig. 2.7 Current density chart for varying length and NFIN=1 __________________ 21
Fig. 2.8 VDS dependence of ID/NFIN w.r.t gm/ID __________________________ 21
Fig. 2.9 Conductance vs gm/ID for NFIN=1 _______________________________ 22
Fig. 3.1 Measured VDS-ID characteristics & Shockley model __________________ 25
Fig. 3.2 Measured & model calculation of VGS-ID characteristics ______________ 25
Fig. 3.3 ID-VGS characteristics of NFET (W=71nm,L=71nm) _________________ 27
Fig. 3.4 ID-VDS characteristics of NFET(Weff = L) _________________________ 28
Fig. 3.5 ID,gm vs VGS characteristics(NFIN=1, L=71nm) ____________________ 29
Fig. 3.6 ID-VDS characteristics of NFET(NFET = 1)[Model & Simulated] _______ 31
Fig. 3.7 ID-VDS characteristics of NFET(NFET = 100)[Model & Simulated] _____ 31
Fig. 3.8 ID-VDS characteristics of PFET(NFET = 1)[Model & Simulated] _______ 32
Fig. 3.9 ID-VDS characteristics of PFET(NFET = 100)[Model & Simulated] _____ 32

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Fig. 4.1 ID vs VGS for NMOS transistor with aspect ratio W/L = 6/100nm ______ 35
Fig. 5.1 Schemetic of CMOS Inverting amplifier(Inverter) ____________________ 39
Fig. 5.2 DC Characteristics of Inverter[FinFET model]_______________________ 41
Fig. 5.3 AC Characteristics of Inverter[FinFET model]_______________________ 41
Fig. 5.4 Slew rate Characteristics of Inverter[FinFET model] __________________ 42
Fig. 5.5 AC Characteristics of Inverter[gm/ID method]_______________________ 43
Fig. 5.6 Slew rate Characteristics of Inverter[gm/ID method] __________________ 43
Fig. 5.7 Schemetic of Single stage Miller OP-AMP with resistive load __________ 44
Fig. 5.8 AC Characteristics of Single stage Miller OP-AMP ___________________ 46
Fig. 5.9 Transient Characteristics of Single stage Miller OP-AMP ______________ 46
Fig. 5.10 DC Characteristics of Single stage Miller OP-AMP __________________ 47
Fig. 5.11 Schemetic of two stage Miller OP-AMP___________________________ 48
Fig. 5.12 DC Characteristics of Two stage Miller OP-AMP ___________________ 52
Fig. 5.13 Transient Characteristics of Two stage Miller OP-AMP ______________ 52
Fig. 5.14 AC Characteristics of Two Stage Miller OP-AMP __________________ 53
Fig. 5.15 Slew rate of Two Stage Miller OP-AMP __________________________ 53

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 LIST OF TABLES

Table 1 Parameters extracted for Alpha Power Law model of FinFET ___________ 30
Table 2 Comparison of results obtained from FinFET model and gm/ID method ___ 43
Table 3 Results of Single Stage Miller OP-AMP with resistive load _____________ 47
Table 4 Results of Two Stage Miller OP-AMP ______________________________ 51

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