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by
Seung Wook Yoon, Patrick Tang, Yaojian Lin, Pandi C. Marimuthu and Raj Pendse
STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442
STATS ChipPAC Inc.47400 Kato Road Fremont, CA 94538 USA
Copyright 2013. Reprinted from 2013 Electronic System Technologies Conference and
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Flipchip eWLB (embedded Wafer Level Ball Grid Array) Technology
as Innovative 2.5D Packaging Solutions
Seung Wook Yoon, ,Patrick Tang, Yaojian Lin, Pandi C. Marimuthu and Raj Pendse
STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442
STATS ChipPAC Inc.47400 Kato Road Fremont, CA 94538 USA
1
wafer diameters and expanding into the device's electrical performance
various end-market products. With the (including electrical parasitic and
WLP infrastructure and high volume operating frequency) [3].
production already in place, a major eWLB is an interconnection system
focus area now is cost reduction. processed directly on the wafer and
One of the most well known compatible with motherboard
examples of a FOWLP structure is technology pitch requirements. It
eWLB technology [1]. This technology combines conventional front- and back-
uses a combination of front- and back- end manufacturing techniques with
end manufacturing techniques with parallel processing of all chips.
parallel processing of all the chips on a
wafer which can greatly reduce
manufacturing costs. The benefits of
eWLB include a smaller package
footprint compared to conventional
leadframe or laminate packages, medium
to high I/O count and maximum
connection density as well as desirable
electrical and thermal performance.
eWLB also offers a high-performance,
power-efficient solution for the wireless
market [2]. Furthermore, 2.5D/3D (b)
eWLB technology enables 2.5D
interposer packaging, 3D IC, and 3D SiP
(System-in-Package) with vertical
interconnection. 2.5D/3D eWLB can be
implemented with heterogeneous
integration of IPD, MLCC or discrete
component embedding.
3
interposer configuration is critical to assembly process flow as well as
enable a more cost effective packaging reliability/yield issues in multi-chip
solution. Combining LSI with the wide assembly with thin TSV interposers.
I/O memory interfaces or high From a test view point, extended eWLB
bandwidth memory (HBM) with the has a number of advantages in final
TSV packaging capability can provide testing such as handling, logistics and
an optimum solution for achieving the compatibility of current test
best performance in thin multi-die stacks environments.
for very high volume manufacturing. A
comparison of a TSV interposer solution
to an eWLB based solution is shown in
Figure 3.
4
Figure 4. Schematics of (a) flip chip SMDs, dark gray in center is for Si
packaging and flip chip eWLB with device.
decoupling capacitor for a high
performance application; (b) capacitor SUBSTRATE DESIGN
on substrate and (c) capacitor embedded OPTIMIZATION WITH
in flip chip eWLB. COMBINING eWLB
TECHNOLOGY
Flip chip eWLB
As advanced technology nodes move eWLB technology has fine line
beyond 28nm, there are more challenges width and spacing capability of
in flip chip assembly with smaller bump 10um/10um as well as lower intrinsic
pitches and ELK (extreme low-k) electrical parameters, providing
materials in ILD (interlayer dielectric flexibility in routing designs as
materials) structures in a device. compared to substrate technology.
Standard flip chip assembly needs to Figure 6 shows the package routing
address bump structure/materials, UBM design with eWLB (2-L RDL) for 4-
designs, underfill processes/materials as layer (1-2-1) substrate. This was verified
well as substrate materials and package by a signal integrity study for high speed
design to secure good solder joint digital applications which included
reliability with flip chip bump simulation and a functional test that
interconnects. proved a 2-L RDL eWLB design is
Flip chip eWLB provides a fan-out comparable to at least 4-layer substrate
area that has a larger pad pitch and RDL designs.
layer, providing an I/O reconfiguration
that minimizes substrate layer numbers (a) (b)
while optimizes electrical performance
such as combined power and ground. As
shown in Figure 4 (c) and Figure 5, flip
chip eWLB has the option to integrate a
decoupling capacitor and place it closer
to the device for better electrical
performance.
Figure 6. Design optimization with (b)
(a) (b)
2-layer RDL in eWLB for (a) 4-layer
organic substrate.
5
pad and via hole size as well as flip Table 2. Flip chip eWLB approach with
chip/solder ball pitch. eWLB converted less number of layers of organic
designs should be approached with more substrate.
actual data to meet electrical
performance and signal integrity. eWLB Flip chip PKG Flip chip eWLB
RDL designs provide an optimized and flipchip eWLB (2-layer
efficient signal integrity in RDL)
interconnection routing with a coarse Organic substrate Organic substrate
bumping pitch. With this coarse bump (14-layer) (8-layer)
pitch in flip chip eWLB, we expect a
lower cost organic substrate having a
large pad pitch and reduced number of ENHANCED SOLDER JOINT
metal layers. RELIABILITY WITH RDL IN
A previous study [5] shows a EXTENDED EWLB/ FLIP CHIP
comparison of parasitic values of RLC EWLB [6]
for fcBGA and eWLB at 1GHz. For
resistance, eWLB has 68% less value In this study, two different interconnect
than fcBGA. Moreover, eWLB has a 66% schemes of direct bump and RDL
less inductance value and 39% less approaches were studied with
capacitance value as compared to mechanical simulation as shown Figure
fcBGA. This is mainly due to the shorter 7. Shearing force was simulated for each
interconnection in an eWLB package. bump case. Figure 7 and Table 3 show
For fcBGA, there are flip chip solder the results from FEM (Finite Element
bumps and substrate interconnections Method) mechanical simulation.
that all contribute to signal delay. eWLB According to the results, the overall
has shorter interconnections with the stress level was much higher in the
RDL process, thus it has improved direct bumped model. When it comes to
electrical performance over fcBGA. a Cu / ELK ILD stacked area, an RDL
Even in unit parasitics, eWLB has lower approach produces a smaller stress value
resistance and inductance values than that is approximately 30% of the direct
fcBGA at all frequencies. eWLB shows bump. The RDL approach was more
less reflection noise and better stable and safer than direct bump with
transmission performance than fcBGA respect to the bump shearing condition.
over all frequency ranges. fcBGA has a In this case, the additional dielectrics
resonance near 7.5~8GHz due to the layers in an eWLB RDL provide stress
mutual factor of inductance and relaxation and pad rerouting, resulting in
capacitance elements. This resonance lower stress on the ELK ILD area. As a
affects crosstalk of neighbor signal, result, better interconnection reliability
signal distortion/reflection, power can be accomplished with the RDL
integrity, signal integrity as well as approach in eWLB technology.
EMI/EMC. However, eWLB shows no
resonance and better electrical Table 3. FEM results for maximum
performance, therefore, eWLB can be stress at solder bump and Cu/ELK ILD
applicable for higher frequency stacked area for direct bump and RDL
applications. model.
6
Simulation Models
Max. Shear Stress eWLB packages are also a promising
(MPa) approach to improving package
Direct C4-bump 114.2 reliability of Cu/ELK interconnects in
C4-bump on RDL 25.9 flip chip packaging. Figure 9 shows the
Cu column on RDL 27.12 FEM simulation results of Figure 7(a)
ELK ILD @ Direct and Figure 7(c). With RDL layers, bump
151.2
C4-bump
ELK ILD @ RDL C4- stress does not directly affect ELK stack
8.97
bump layers, therefore, there would be less
ELK ILD @ RDL-Cu mechanical damage as compared to
3.529
column
standard flip chip bump.
(a)
(b)
7
mobile applications require. The References
advantages of eWLB include a multi-die
package design, thin 3D solution, higher 1. M. Brunnbauer, et al., Embedded
performance from reduced interconnect Wafer Level Ball Grid Array (eWLB),
lengths, ultra fine pitch capability and Proceedings of 8th Electronic Packaging
superior warpage control. Technology Conference, 10-12 Dec
Extended eWLB and flip chip eWLB 2006, Singapore (2006).
technology provide a proven integration 2. Graham pitcher, Good things in
platform as well as a lower cost solution small packages, Newelectronics, 23
without sacrificing electrical June 2009, p18-19 (2009).
performance. Extended eWLB can be an 3. S.W. YOON, Meenakshi
alternative solution for 2.5D TSV PADMANATHAN, Andreas BAHR,
interposer technology for mid/low-end Xavier BARATON and Flynn
applications. Flip chip eWLB provides a CARSON, 3D eWLB (embedded wafer
cost-effective solution with a reduced level BGA) Technology: Next
number of layers and a more relaxed Generation 3D Packaging solutions,
design rule in flip chip substrates. In San Francisco, IWLPC 2009 (2009).
addition, eWLB provides enhanced 4. Dr. Raj Pendse, Semiconductor
bump solder joint reliability with an Device and Method of Forming
RDL approach for advanced node Extended Semiconductor Device with
Cu/ELK flip chip devices. Fan-Out Interconnect Structure to
eWLB will provide more exciting Reduce Complexity of Substrate, Patent
developments in the future as the Pending 2011.
scalability of its carrier size will drive 5. S. W. Yoon, Roger Emigh , Kai Liu,
greater cost effectiveness. Extended Sin Jae Lee, Ray Coronado and Flynn
eWLB and flip chip eWLB technology Carson, Thermal and Electrical
are successfully enabling semiconductor Characterization of eWLB (embedded
manufacturers to provide the smallest, Wafer Level BGA), ECTC2010, Las
highest-performing semiconductors to Vegas (2010).
meet the ever increasing demands of the 6. 150-um Pitch Cu/Low-k Flip Chip
converging products in the market today Packaging With Polymer Encapsulated
and in the future. Dicing Line (PEDL) and Cu Pillar
Interconnects, IEEE TRANSACTIONS
ACKNOWLEDGEMENT ON ADVANCED PACKAGING, VOL.
Authors appreciate Jang Tae Hoan, Kim 31, NO. 1, pp58-65 FEBRUARY 2008
Kyung Eun, Song Hyun Jin, Park Soo (2008).
Han and Dr. Liu Kai in design and
characterization team, STATS ChipPAC
for design optimization study, electrical
simulations and characterization study of
eWLB technology.