FPGA Based Implementation of Variable-Voltage
Variable-Frequency Controller for a Three Phase
Induction Motor
Krishna Chandran Vinay, Shyam H N, S. Rishi and S. Moorthi*
AbstractThis paper presents the design and implementation
of a Variable-Voltage Variable-Frequency (VVVF) Controller
based on Sinusoidal Pulse Width Modulation (SPWM) Technique
for a 3 Phase Induction Motor using a Field Programmable Gate
Array (FPGA). The work involves implementation of an Open
loop control scheme for an induction motor. The technique is used
extensively in the industry as it provides the accuracy required
at minimal cost. Voltage/ frequency (v/f) controlled motors fall
under the category of Variable Voltage Variable Frequency
(VVVF) drives. To maintain maximum torque for a given working
condition, the flux in the machine must be maintained constant.
In other words, the ratio of Voltage to frequency must be
held constant. For Variable Voltage Variable Frequency (VVVF)
drives, there is a need to control the fundamental voltage of
the inverter if its frequency (and therefore the frequency of the
induction motor), need to be varied. To vary the fundamental
component of the inverter, the Modulation Index of the carrier
signal has to be changed. The speed at rated supply frequency
is normally used as the base speed. At frequencies below the
base speed, the supply magnitude needs to be reduced so as to
maintain a constant Volt/Hertz. The FPGA controller is used to
generate SPWM pulses based on the frequency input, that are
used to control the inverter. The VVVF output of the inverter can
be used as supply to a three phase induction motor and thereby
speed of the motor can be controlled.
I. INTRODUCTION
Controlling the speed of induction motors has ever since
been an important topic of research. The control methodolo-
gies have evolved from electromechanical switching to high
speed digital controllers using DSP and FPGA [1]. Of late,
Pulse-Width Modulation techniques have been the subject
of intensive research; as PWM controlled power electronic
devices find increasing applications in many new industrial
processes involving more stringent performance specifications
Krishna Chandran Vinay is a Masters student in the Department of
Electrical Engineering: Systems, University of Michigan, Ann Arbor, USA,
with a concentration in Control Systems and Power. He received his Bachelors
degree from National Institute of Technology, Trichy, India. His areas of inter-
est include Feedback Control Design, Power Electronics, and Battery Systems,
especially for Electric Vehicle applications. (e-mail: kcv@umich.edu)
Shyam H N completed his B.Tech (EEE) in the Department of Electrical
and Electronics Engineering, National Institute of Technology, Tiruchirappalli,
INDIA during April 2010. His area of interest includes research and analysis
of alternative and sustainable energy systems.
Rishi S. is a B.Tech student in the Department of Electrical and Electronics
Engineering, National Institute of Technology, Tiruchirappalli, INDIA. His
area of interest includes VLSI Systems and Electronic circuit design.
Dr. S. Moorthi is a faculty in the Department of Electrical and Electronics
Engineering, National Institute of Technology, Trichy, India. He completed
his Ph.D in the area of VLSI for Communication circuits. His area of interest
includes VLSI for signal processing and Embedded systems. (*Corresponding
author: srimoorthi@nitt.edu).
978-1-61284-764-1/11/$26.00 2011 IEEE
[2]. This is particularly true in case of high performance drive
systems, uninterruptible power supply and programmable AC
power sources. Since PWM inverters play an important role
in each of these applications, the whole system is depen-
dent on the algorithm controlling the PWM inverter [3]. In
recent years, Field Programmable Gate Arrays have drawn
much attention due to its short design cycle, low cost and
high flexibility in terms of programmability. The Field Pro-
grammable Gate Arrays (FPGAs) offer significant advantages
over microprocessors and DSPs for high performance, low
volume applications, particularly for applications that can
exploit customized bit-widths and massive instruction-level
parallelism. The innovative development of FPGAs whose
configuration could be re-programmed an unlimited number
of times spurred the invention of a new field in which many
different hardware algorithms could execute, in turn, on single
device, just as many different software algorithms can run on
a conventional processor [4]. When comparing the dynamic
performance, control capabilities and concurrency in PWM-
controlled Power Converters, FPGA based digital techniques
are better than DSPs [5] [6]. The paper is organized with
the Introduction in section I, followed by a brief report on
speed control of three phase induction motor in section II.
The capability of the proposed system is explained in Section
III. Section IV includes the results obtained from the FPGA
controller with the conclusion in section V.
II. SPEED CONTROL OF INDUCTION MOTOR
The synchronous speed of the induction motor is given by:
120f
Ns = (1)
p
where f is frequency and p is number of poles.The running
speed of the induction motor is given by the equation:
Nr = Ns (1 s) (2)
where s is slip of the induction motor expressed in terms
of percentage. The speed control can be performed using
open loop algorithms or closed loop algorithms. The most
commonly used open loop algorithm is Voltage/ frequency
control method [7]. Closed loop algorithms include sensor and
sensorless feedback using scalar or vector control. Open loop
control of induction motor is used extensively in the industry
as it provides the accuracy required at minimal cost. Voltage/
frequency controlled motors fall under the category of Variable
Voltage Variable Frequency drives which are fed by an inverter
Fig. 1. Modes of operation of VVVF drives under V/ f control method
Fig. 2. Variation of Voltage V with respect to frequency f
[8]. For maximum torque production, motor flux should be
maintained at its rated value.
= m sin(1 t)
But the back emf is:
d load is proportional to the amplitude of the signal (assumed
e1 = N = N 1 m cos(1 t)
dt
In RMS,
e1 = 4.44N f1 m
The modes of operation of a VVVF drive working under
Constant V/f control method is given in Figure 1. Figure 2
shows the variation of Voltage V with respect to frequency
in a V/f control scheme. At all frequencies above the rated
frequency, the voltage is maintained at the rated value. At
low frequencies below 5 Hz, the Voltage is maintained at a
minimum fixed value. Voltage/ frequency control is based on
the following assumptions: The motor impedance increases
when the frequency increases and there should be a fixed
current as much as possible. So that it is simple to increase the
motor speed by increasing the frequency and the related volt-
age. Variable-frequency drives are widely used in ventilation
systems for large buildings, variable-frequency motors on fans
save energy by allowing the volume of air moved to match the
system demand. They are also used on pumps, conveyor and
machine tool drives. In the most straightforward implementa-
tion of Sinusoidal Pulse Width Modulation, generation of the
desired output voltage is achieved by comparing the desired
reference waveform (modulating signal) with a high-frequency
triangular carrier. wave as depicted schematically in Figure.3.
Depending on whether the signal voltage is larger or smaller
than the carrier waveform, either the positive or negative
Fig. 3. Basic Implementation of SPWM
Fig. 4. Harmonic profile comparisons between SPWM and Multiple Pulse
technique
(3)
DC bus voltage is applied at the output. Note that, over the
period of one triangle wave, the average voltage applied to the
(4)
constant) during this period. The resulting chopped square
waveform contains a replica of the desired waveform in its low
(5) frequency components, with the high frequency components
being at frequencies close to the carrier frequency [8]. Also,
the root mean square value of the AC voltage waveform is
still equal to the DC bus voltage and hence the total harmonic
distortion is not affected by the PWM process. The harmonic
components are merely shifted to the high frequency range and
are automatically filtered due to inductances in the AC system.
When the modulating signal is a sinusoid of amplitude Am ,
and the amplitude of the triangular carrier is Ac . The ratio
of the amplitude of the modulating signal to the amplitude of
the carrier signal is called the modulation index. Therefore,
controlling the modulation index controls the amplitude of the
applied output voltage. Modulation index,
Am
m= (6)
Ac
From figure 4, it can be seen that Distortion Factor is about 4-5
in case of multi-pulse, and this value is considerably reduced
to about 0.8-1 in case of SPWM. Hence, SPWM is preferred
over multi-pulse for producing gate-pulses for inverters.
III. THE PROPOSED SYSTEM
The system block diagram with various modules is shown
in Figure 5. The FPGA controller produces the SPWM pulses
 Oscillator Clock

Frequency,
Multiplexed Initial Phase
Data (8 bit)
(Frequency, Oscillator
Amplitude,
Initial Phase)
Interface
Input Selection
(2 bit) Phase Value
(0 to 360 deg )
Enable
(1 bit)

Add 120 deg Add 120 deg

to Phase value to Phase value

Phase 3 Phase 2 Phase 1

Fig. 5. System Block Diagram

Calculate Sine of Calculate Sine of Calculate Sine of
Phase with given Phase with given Phase with given
Amplitude Amplitude Amplitude

which are at a voltage of 3.3V. The voltage shifting from 3.3V

to 12V requires a voltage-level shifting circuit. The voltage-
level shifted pulses will be fed to the three phase inverter to
convert the DC supply to a three phase supply which is in turn
Counter and Counter and Counter and
fed to the induction motor. The variation in the duty cycle and Comparator Comparator Comparator

the number of SPWM pulses determines the amplitude and

frequency of the inverter. This can be achieved by varying
either the amplitude or frequency of the carrier signal (trian- PULSE 1 PULSE 2 PULSE 3 PULSE 4 PULSE 5 PULSE 6

gular wave). A model for the controller was designed using

VHDL and figure 6 describes the basic design flow of the
VHDL code. The VHDL code developed to generate a three
phase sinusoidal pulse width modulated signal is divided into
seven entities, namely: Interface Module, Oscillator, Addition
of 120, Amplitude Module, PWM Module, Top Level Module
and Clock Divider Module. The inputs to the program as a
whole are an 8 bit multiplexed data signal, a 2 bit selection
signal and an enable signal. The outputs are three pulsewidth
modulated sinusoidal signals; each signal being phase shifted
120 with respect to the previous signal in a cyclic manner.
The 8 bit data input is given to the FPGA directly from the
PC using a Virtual Input-Output Module. This makes use of
Xilinx Chipscope Pro tool. The enable and selection signals
are given through switches on the board and outputs are taken
from six of the general-purpose inputoutput pins.
A. Interface module
The purpose of this entity is to interface the FPGA with the
inputs. The input to the FPGA is an 8 bit multiplexed data
signal, a 2 bit selection signal and an enable signal. The data
signal is demultiplexed with the help of the selection signal
when the enable signal is high. The following rules are used
to demultiplex the data signal: If the selection signal is 00,
the data lines represent amplitude. If the selection signal is
01, the data lines represent frequency. If the selection signal
is 10, the data lines represent the 8 lower bits of the phase.
If the selection signal is 11, the data lines represent the 2
higher bits of the phase. Clearly, signals 10 and 11 can be
used to set an initial phase value.If the enable signal is low, the
frequency and amplitude values remain the same until enable
is made high again. The entity has another input, a 10 bit
phasein . When enable is low, the phase output is the same
as phasein . Thus, the outputs of this entity are: Frequency (8
bits), Amplitude (8 bits) and Phase (10 bits).
Fig. 6. Flow diagram of VHDL Model
Fig. 7. Saw tooth waveform generated by oscillator
B. Amplitude lookup table
This entity is used to calculate the value of modulation index
from the value of frequency input to the FPGA. It generates
a Modulation Index of 1 for frequencies of 50 Hz and above.
For frequencies below 50 Hz, it varies linearly. The modulation
index is a value between 0 and 1, and hence can be represented
by cos(). This is done to reduce the FPGA resources used
by changing a multiplication to an addition. This is described
in detail in the Amplitude Module. The output of the look-up
table is an 8 bit value which represents .
C. Oscillator
This entity is used to generate phase values increasing from
0 to 360 , and then reset back to zero, resulting in a shape
resembling a sawtooth as shown in figure 7 with a minimum
value of 0 and maximum value of 360 . The entity takes the
frequency, initial phase and a clock as inputs. The whole entity
is basically a D-flip flop as shown in figure 8. The value of
phase is initialised to a given value using the data signal and
selection signals 10 and 11, or to zero by default. The Phase
value here is 10 bits wide with 0000000000 representing
0 and 1111111111 representing 360 . The 8 bit frequency
value determines the phase increment that is the value of phase
is incremented by the frequency value every clock cycle. When
Fig. 8. Schematic of the oscillator
the phase value reaches 360 , it is reset to zero, thus effectively
producing a sawtooth. Clearly, if the value of frequency input
is larger, the phase value reaches 360 faster and thus produces
a saw tooth of higher frequency. Note that the adder here adds
an eight bit frequency value to a 10 bit phase value. Thus, the
output of this entity is a ten bit phase value which increases
and decreases in the shape of a sawtooth. It has to be noted
that the clock signal for the oscillator should have a frequency
1/512 times that of the frequency of clock signal used in the
counter-comparator, since the counter counts from 0 to 511
for each pulse of the PWM output.
D. Addition of 120
This entity takes a ten bit phase value as input, increments
it by 120 (i.e. 0101010101). The output is also a ten bit
phase value. Thus when a phase value, say P1 , is incremented
by 120 once to get P2 and then P2 is incremented by 120 to
get P3 ; three values of phase are obtained that can be arranged
in a cyclic manner resembling that of a three phase system.
E. Amplitude module
This entity is used to calculate the value of the sine of the
phase taking into account the value of the amplitude input.
It takes as inputs 10 bit phase, 8 bit amplitude and a clock
signal, and gives an 8 bit value as output. The value of Acos(),
should be calculated where A is the amplitude and is the
phase. The value of the cosine can be computed using a cosine
lookup table. However, using a multiplier to multiply the value
of amplitude would use too much of the FPGAs resources.
Thus an alternate method is suggested. The amplitude is coded
as an angle from zero to 90 , where 00000000 represents
zero and 11111111 represents 90 . The cosine of this angle
can be used to represent amplitude. Thus cos()*cos() has
to be computed, where is the amplitude angle. Using
simple trigonometric transformations, this becomes [cos(+)
+ cos(-)]/2, and thus avoiding the need to use a multiplier.
The schematic of the amplitude module is shown in figure 9.
The lookup table is generated for cos() where is the ten
bit phase value converted to an angle. 127 represent decimal
1, and is added so that all resulting values are positive. For
example, if the phase value is 0101010101 (ie. 120 ) the
output of the lookup table is 63, ie. 00111111, when the
actual value of cosine is -0.5. The lookup table utilises eight
most significant bits of the phase to give an eight bit cosine
output. Only half of the phase values (from 0 to 127) need
to have entries in the table because of the symmetry of the
Fig. 9. Schematic of Amplitude module
Fig. 10. Sinusoidal Pulse Width Modulation
cosine curve. A separate entity GenericSelectableInverter is
used so that the same table can be used for the other half
of the phase values. The input to the lookup table is 7 bits
wide. The most significant bit is used as an input to the
GenericSelectableInverter. If it is 1, the other seven bits
are inverted. If it is 0 they are left unaltered. The output
of the GenericSelectableInverter is the input to the lookup
table. For example consider 00000000 and 11111111. Both
have the same lookup table output value, ie. 127. Clearly,
GenericSelectableInverter gives an output of 0000000 for
both the values, hence facilitating the use of a reduced half-
table. The lookup table has to be used six times, two times
for each phase. In an ordinary case, the lookup table would
be instantiated six times, resulting in the unnecessary use of
excess resources. The lookup table has to be instantiated only
once for the most efficient code. This is done in the following
way. A counter counting from 0 to 11 is made. When the value
of the counter is 0, the value of (A+) for the first phase is
taken as input for the table. When it is 1, the output of the
table is taken as cos(A+). When it is 2, the value of (A-
) for the first phase is taken as input for the table. When it
is 3, the output of the table is taken as cos(A-). A similar
operation is carried out for the other two phases. This simple
modification results in the number of lookup tables being used
in a Xilinx Spartan 3E FPGA from 1230 to 695, thus almost
halving the number of resources for the same operation.
F. PWM module
This entity is a counter-comparator pair used to generate
the sinusoidal PWM output (as shown in figure 10) from a
cosine input given by the Amplitude Module. Normally, the
counter would count from 0 to 255 for an 8 bit input, but
Fig. 11. SPWM pulses for one of the inverter branches
V cc = +12V
1K 1K
10 K
Output
1K
2N2222 2N2222
Input
GND
Fig. 12. Voltage Level Shifting Circuit
here, to have both half wave and quarter wave symmetry,
the counter counts from zero to 512. Such symmetry greatly
reduces inverter harmonics. The comparator outputs low if the
value of the count is between (256-input) and (256+input), and
high otherwise, thus resulting in both half wave and quarter
wave symmetry. This entity also generates the clock for the
oscillator which clearly has to have a frequency 1/512 times
the clock used for the countercomparator pair. From the three
SPWM signals, six gate driving pulses have to be generated.
The pulses for one of the branches of the inverter have to be
phase shifted by 180 and those for two adjacent branches
have to be phase shifted 120 . Thus, to generate the two out-
of-phase pulses from a single pulse, the following steps are
done: 1. Zero crossing is detected, 2. the pulses representing
the positive half cycle of the Sinusoid form the first pulse are
generated. 3. The pulses representing the negative half cycle
are inverted to form the second pulse are generated. 4. The
process is repeated for the other two phases. The final pulses
generated for two the IGBTs in any one of the branches will
be as shown in figure 11.
G. Top level module
This is the top-level entity in which copies of all the other
entities are instantiated. In other words, this is the entity that
takes the inputs to the FPGA, viz. The 8 bit data signal, the
two bit selection signal, the enable signal and the clock, and
gives the three PWM sinusoids as outputs, using instances of
each of the above mentioned entities.
Fig. 13. Experimental Setup of the proposed system
Fig. 14. Inverter IGBT Gate pulse for f=25 Hz
H. Clock divider module
The internal clock on the Spartan 3 E FPGA has a frequency
of 50 MHz, which would result in a PWM signal with
switching frequency approximately 200 kHz, which is too high
for the inverter being used. To bring this switching frequency
down to about 10 kHz, the internal clock frequency has to be
divided by 250. This is done by the entity clock divider, using
a counter that counts from 0 to 249 and outputs high when
the counter value less than 125 and low otherwise. Thus this
entity takes a clock signal as input and gives a clock signal
of (1/256) times the frequency of the input as output.
I. Voltage level shifting circuit
The FPGA outputs PWM Pulses consisting of highs and
lows, where a high is 3.3 V and a low is 0. However, to drive
the inverter model in use, the high of the pulses must be at 12
V. Hence a circuit, as shown in figure 12, to shift the voltage
level of the pulses from 3.3 Volts to 12 Volts was designed.
Hence, upon using a Vcc of 12 V, the level shifted pulses can
be obtained and fed to the inverter.
J. Inverter module
The three Phase Inverter Module (as shown in figure 13)
consists of a three phase voltage source inverter with its gate
driver circuits. All six SPWM gate-driving pulses have to
 inverter to produce a proper supply voltage which is fed to
drive the three phase induction motor.

R EFERENCES
[1] R.Nandhakumar, S.JeevananthanP.Dananjayan, Design and Implementa-
tion of an FPGA-Based High Performance ASIC for Open Loop PWM
Inverter, IICPE, 2006, pp.349-354.
[2] Arulmozhiyal, R. Baskaran, K. Devarajan, N. Kanagaraj, Space Vector
Pulse Width Modulation Based Induction Motor Speed Control Using
FPGA, ICETET, 16-18 Dec 2009, pp 242-247.
[3] Nitish Patel, UdayaMadawala, A Bit stream based scalar control of an
Fig. 15. Phase Voltages at f=50 Hz Induction Motor,IECON, 2008, pp. 1071-1076.
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be given to the module, along with a 15V supply for the

gate driver circuits. The output of the inverter is given to a
star connected load, which is composed of three 50 ohm, 5A
rheostats.

IV. EXPERIMENTAL RESULTS

The experimental results were obtained with the help of
Digital Storage Oscilloscope and Power Quality Analyser to
check the functionality and the performance of the controller
is verified by obtaining the inverter output voltages. Figure
14 illustrates the inverter IGBT gate pulses at a frequency
of 25Hz. Figures 15 and 16 show the inverter output phase
voltages at frequency of 50Hz and line voltage at a frequency
of 12.5Hz respectively.

V. C ONCLUSION
The open loop control scheme for a three phase inverter is
implemented using FPGA. The versatility in FPGA program-
ming makes the designer to implement an efficient controller
in it. The most important factor in support of using FPGA
based designs is that it can be started from scratch and the
design can be improved along the way by continuously testing
and improving the code. One noteworthy fact is that the
first version of the VHDL model used 64 per cent of the
FPGA resources, and the final version uses only 8 per cent
of the resources. Furthermore, using a digital controller make
the system less susceptible to noise, temperature and other
environmental factors. More significantly, the controller size
and complexity is considerably reduced. The reconfigurable
feature of FPGAs makes it more flexible. In conclusion, the
VVVF controller is successfully implemented using FPGA and
the experimental results show that the controller enables the