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CD4013B
SCHS023E NOVEMBER 1998 REVISED SEPTEMBER 2016
Logic Diagram
4 (10)
CL All inputs are protected by
RESET MASTER SECTION SLAVE SECTION CMOS protection network
CL
p VDD
p TG
5 (9) TG n
DATA n CL
CL
CL
CL p
p TG
TG n
n
CL
CL VSS
6 (8)
SET
Q
1 (13)
CL CL
Buffered Outputs
3 (11)
Q
CL 2 (12)
VDD = Pin 14
VSS = Pin 7
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4013B
SCHS023E NOVEMBER 1998 REVISED SEPTEMBER 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 1 8 Application and Implementation ........................ 11
3 Description ............................................................. 1 8.1 Application Information............................................ 11
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 11
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 12
6 Specifications......................................................... 4 10 Layout................................................................... 12
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................ 12
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 12
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 14
6.4 Thermal Information .................................................. 5 11.1 Documentation Support ........................................ 14
6.5 Electrical Characteristics: Static................................ 5 11.2 Receiving Notification of Documentation Updates 14
6.6 Electrical Characteristics: Dynamic........................... 7 11.3 Community Resources.......................................... 14
6.7 Typical Characteristics .............................................. 8 11.4 Trademarks ........................................................... 14
7 Detailed Description ............................................ 10 11.5 Electrostatic Discharge Caution ............................ 14
7.1 Overview ................................................................ 10 11.6 Glossary ................................................................ 14
7.2 Functional Block Diagram ....................................... 10 12 Mechanical, Packaging, and Orderable
7.3 Feature Description ................................................ 10 Information ........................................................... 14
4 Revision History
Changes from Revision D (March 2005) to Revision E Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Added Thermal Information table ........................................................................................................................................... 5
D, J, N, NS, PW Package
14-Pin SOIC, CDIP, PDIP, SO, TSSOP
Top View
Q1 1 14 VDD
Q1 2 13 Q2
CLOCK1 3 12 Q2
RESET1 4 11 CLOCK2
D1 5 10 RESET2
SET1 6 9 D2
VSS 7 8 SET2
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 Q1 O Channel 1 output
2 Q1 O Inverted channel 1 output
3 CLOCK1 I Channel 1 clock input
4 RESET1 I Channel 1 reset
5 D1 I Channel 1 data input
6 SET1 I Channel 1 set
7 VSS Ground
8 SET2 I Channel 2 set
9 D2 I Channel 2 data input
10 RESET2 I Channel 2 reset
11 CLOCK2 I Channel 2 clock input
12 Q2 O Inverted channel 2 output
13 Q2 O Channel 2 output
14 VDD Power supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
DC supply voltage, VDD (2) 0.5 20 V
Input voltage, all inputs 0.5 VDD + 0.5 V
DC input current, any one input 10 mA
TA = 55C to 100C 500
Power dissipation, PD (3)
mW
TA = 100C to 125C 200
Device dissipation per output transistor 100 mW
Operating temperature, TA 55 125 C
Storage temperature, Tstg 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages reference to VSS terminal
(3) Derate linearity at 12 mW/C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) If more than one unit is cascaded in a parallel clocked operation, trCL must be made less than or equal to the sum of the fixed
propagation delay time at 15 pF and the transistion time of the output driving stage for the estimated capacitive load.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
40 20
Gate-to-Source Voltage = 5 V Gate-to-Source Voltage = 5 V
35 Gate-to-Source Voltage = 10 V 17.5 Gate-to-Source Voltage = 10 V
25 12.5
20 10
15 7.5
10 5
5 2.5
0 0
0 5 10 15 20 25 0 5 10 15 20 25
Drain-to-Source Voltage (V) D001
Drain-to-Source Voltage (V) D002
Figure 1. Typical Output Low (Sink) Current Figure 2. Minimum Output Low (Sink) Current
0 0
Gate-to-Source Voltage = -5 V Gate-to-Source Voltage = -5 V
Output High (Source) Current (mA)
-15
-20 -10
-25
-30 -15
-35
-40 -20
-25 -20 -15 -10 -5 0 -25 -20 -15 -10 -5 0
Drain-to-Source Voltage (V) D003
Drain-to-Source Voltage (V) D004
Figure 3. Typical Output High (Source) Current Figure 4. Minimum Output High (Source) Current
150 150
100 100
50 50
0 0
0 20 40 60 80 100 0 20 40 60 80 100
Load Capacitance (pF) D023
Load Capacitance (pF) D024
CLOCK or SET to Q, CLOCK or RESET to Q SET to Q or RESET to Q
Figure 5. Typical Propagation Delay Time Figure 6. Typical Propagation Delay Time
vs Load Capacitance vs Load Capacitance
40 10k
30 1k
Clock Frequency (MHz)
25
20 100
e
15
10 10 Supply Voltage = 5 V
Supply Voltage = 10 V (CL = 15 pF)
5 Supply Voltage = 10 V (CL = 50 pF)
Supply Voltage = 15 V
0 1
0 5 10 15 20 25 100 1k 10k 100k 1M 10M
Supply Voltage (V) D025
Input Clock Frequency (kHz) D026
Figure 7. Typical Maximum Clock Frequency Figure 8. Typical Power Dissipation vs Frequency
vs Supply Voltage
7 Detailed Description
7.1 Overview
The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent
data, set, reset, and clock inputs and Q and Q outputs. These devices are ideal for data and memory hold
functions, including shift register applications, or by connecting Q output to the data input, this device is used for
counter and toggle applications. The CD4013B is a positive-edge triggered device, meaning that the logic level
present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting
or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.
VDD
6
SET1
5 2
D1 Q1
3 F/F1 1
CLOCK1 Q1
4
RESET1
8
SET2
9 12
D2 Q2
11 F/F2 13
CLOCK2 Q2
10
RESET2
VSS
Copyright 2016, Texas Instruments Incorporated
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
3V
3V
NC VCC
A
GND Y CLK VCC
SN74LVC1G17 D SET
Q RESET
GND Q TO MCU
CD4013B
Copyright 2016, Texas Instruments Incorporated
80
60
40
20
0
0 5 10 15 20 25
Supply Voltage (V) D037
Figure 10. Typical Transition Time vs Load Capacitance
10 Layout
VCC Input
Unused Input Output Unused Input Output
Input
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 17-Mar-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
CD4013BE ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4013BE
(RoHS)
CD4013BEE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4013BE
(RoHS)
CD4013BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4013BF
CD4013BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4013BF3A
CD4013BM ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
& no Sb/Br)
CD4013BM96 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
& no Sb/Br)
CD4013BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
& no Sb/Br)
CD4013BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
& no Sb/Br)
CD4013BME4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
& no Sb/Br)
CD4013BMG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
& no Sb/Br)
CD4013BMT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
& no Sb/Br)
CD4013BNSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013B
& no Sb/Br)
CD4013BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013B
& no Sb/Br)
CD4013BPW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
& no Sb/Br)
CD4013BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
& no Sb/Br)
CD4013BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
& no Sb/Br)
CD4013BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
JM38510/05151BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05151BCA
M38510/05151BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05151BCA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Catalog: CD4013B
Military: CD4013B-MIL
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Nov-2014
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Nov-2014
Pack Materials-Page 2
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
7 8
C SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A
1 14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
7 8
SYMM
METAL
4214771/A 05/2017
www.ti.com
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