ARRAY SuBsyatT EMS Memosy elements, my “be dintdak ‘wile CV Random : : aces Memory ci’) Serta Qecem Memory GY) Contertt acacn TEMoIY ram ot chip Level ds ‘clase as memos that ho» acees time independent of the phyeteak Jocation ok the = dolla. Whee as Serial- acces memories hove. terme tartencty arsociatid with teading or writting of particular dato anh wet content odduessable memories. Rome hove waite time qrester than read tines, But RAMe very Similar read andl tsvtle tines thse ae divided tuto . < Stotic- load a Synchonous have “reqs mo .clock, teguite clk! edge ts enable memory — operition,. * Asynehtonows ayn. RAMS ecogniize address Changes & olp new date akter any auch. change. > Statice lead & destan & blook . Synehiono us emerpmes aro earter ty best choice for system loved building 2 Memory celle un RAMs further altvidad try < car Static Structures (&) Dynamic &trachure..talc celle use gore form of alehedk |~ n-k Drow decode }> [|| | | oor S\wow decsdu [> eed Sp ll ie wit kK-Ht decoder . "Vadose Col: roux, Senne amp, write buffers Peg: Memory chip architecture - RAM i Clocks RAM cel) Covite-dale tead- dota ig Genete RAM Ciweulit.cxoee- copld teat ckt the op. Tre may be veplaced with high value er——“—C—r—S—“ieiCOCrtiC“( ‘ECs 9 tt preverl, denkage from changing ony Valuo Bored an RAM celle Grenerally lole to 1000's ok Ma. tworcl — L = ~bit (a2 SRAM CB SRAM word vt bit> HIGH DENSITY MEMorY ELEMENTS On-chip memory is important as Levele of integration imesease te alle both Processors and useful am of mem t be tact gr ahed on oO Single chip. Rom Flash memory : dominant form of elecbicaly evasable PRom Memory, RAN SRAM Een gram a faster, Larger 4 uses more pow, DRAM hos Srnaller layout & Uses Less puis. DRAM Celle require Petodicely wrefreshis . "e of Aynasically Sted values. A design that eqs high- density Rom ov RAM is partitioned info Several chipe . Medium demsity memory, ov the order of one ’ bytes often be pub on tame chp Leith Logte thet weg tt, giving Faster access times, , 0 well as great integvalion,,5 The btt limes ore typically precharged, So the 5 cell dis charges one of the Lines. The bit Umes axe vead by ck& that sense the Value on the Line, amplify, t peel tt up & westre the Signals te the proper vy levels. A write is - performed setting the bit limes +o the desived caer ding thet " value from -the bit limee tail the cell, Roto decoders wertealy tse NOR gates % decode the adds, Followed by ain of buffs to allow ckt te dhtve Large cap ce of the word ime. ck to amplement wor: -> Peeudo- M08 > Prechagedt. Precharged ckt provide beter performance Rox Large memory arrays compared ‘to Pseudo - nMos-aya sifnsar IY oBeI[OA UT oBueyo [JeUIS oy} esas sroyT{dUIE esudg “(2)zZG°R pur (p)zo"g ‘SBhy Ur UMOYS sv JoISISUEN ese porUdUIo[dutt aq ULD IONORdeD YL ‘Joyoedvo v uo paiojs Ulese st anjea KroweW ay], 97 TSS “Sty ur UMOYS ST [[29 JOISISUe-] Y ‘pasn oq Aeul sassnq wep o1Lim;pue peor pasiou @ synods ] | ‘ 189 WWH Ones OS"g eunB} a —— prom © wa aa prom NOISAG WALSASENS 8 HALldVHO 99S568 CHAPTERS SUBSYSTEM DESIGN iu Figure 8.52 Dynamic RAM circuits: (a) 4-transistor; (b) 3 word ot be © @ pass anssor woe OE a ( ne Say transistor; (c) 1 transistor with Wo wh ‘fe capacitor; (d) transistorwith sage transistor capacitor; (e) rep- a at galt as resentative layout for (d) Seseee> +1 Rvabudd duit al | the RAM circuit concentrates on pulling the bit lirie from high to low. Thus j ‘one method of reading a RAM cell would be to precharge the bi \ and then enable the word-line decoder. For a given pair of bit lines, one RAM cell will attempt to pull down either the bit or ~bit line depending on the stored data. The bit-line pull-up circuit may use p-channel transistors to precharge each bit line (Fig. 8.53a). In this example, the sense amplifier is an inverter that forms a single-ended-sense amplifier, The sense time is roughly vy =}. op To vead, vead-dele FF ed te Yop & sebreda gf tis gate has Stered chaye, ty PA vead-dals wt. wd dita has complement of value stored83 MEMORY ELEMENTS 569 Ul peechoe \ ARH Y Pe —_ come) | yo @) “ a? Fat ne | [5 7 Jttety waa | am ta » the time it takes one RAM cell pull-down and access transistor to reach the inverter threshold. To optimize speed, one might set the inverter threshold above the Vpp midpoint, but below an adequate noise margin down from the Vpp rail. Alternatively, one can precharge the bit lines with n-channel tran- sistors, which results inthe bt lines being precharged to an n threshold down from Vpp (Fig. 8.53b). This can dramatically improve the speed of the RAM cell access. In addition, it reduces power dissipation because the bit lines do not change by the supply vollage-The Key 2SpECT of the precharged RAM Gad cycle Is the Uiting relationship between the RAM addresses, the pre- charge pulse, and the enabling of the row decoder. Ifthe word-line assertion precedes the end of the precharge cycle, the RAM cells on the active word- line will see both bit lines pulled high and the RAM cells may flip state. If “en FIGURE 8.53 RAM read options: (a) Vap precharge; (b) Voo-Vin precharge bit, ait?Figure 8.54 RAM read oper- ation model to amplity this bit-line change. Design margins must be valid over all pro- Cess, temperature, and voltage extremes. Figure 8.55 shows the zero bit volt- age (Vpiqo) and the pull-down voltage (Vputtdown) for various ratios of pull- up beta to pull-down betas. As the pull-up becomes weaker, the Voinco) Volt- age approaches Vs and the differential voltage between a high and a low on the bit lines increases. However, as the pull-down transistors are limited in size by the desire to keep the RAM cell small, a design trade-off has to be made between speed and the differential bit voltage, which affects the noise sense common | o> v (a) o)572 CHAPTER8 SUBSYSTEM DESIGN Figure 8.56 Static RAM- read waveforms Y(vots) ‘Sense Common Current mode sensing may also be used.?%331 In this technique, the current change in the bit lines is detected using special circuits. The theory is that by using low-impedance circuits, the RC delay inherent in driving the bit lines may be decreased. 8.3.1.1.2 Static RAM—write The objective of the RAM write operation is to apply. voltages to the RAM8.3 MEMORYELEMENTS 573 FIGURE 8.57 Static RAM- write circuits: (a) n-channel pass transistors; (b) circuit ‘model during write; (c) com- plementary transmission gate version wirte. enable Tre ny Ny ag erabld % allow AL k Comp & more te bit Kine574 CHAPTER8 SUBSYSTEM DESIGN Figure 8.58 Static RAM- write waveforms and circuit ‘model wt. Oo wee data 5 4 a Vives) 2 1 wea x 0 Via (-Wite-Data) ® 8.3.1.1.3 Row decoders ‘The simplest row decoder is an AND gate. Figure 8.59 shows two straight: forward implementaticns. The first in Fig. 8.59(a) is a static complementary NAND gate followed by an inverter. This structure is useful for up to 5-6 inputs or mote if speed is not critical. The NAND transistors are usually made minimum size to reduce the load on the buffered address lines because there ate 2" (Noad + Proad)’s on each address Tine. The second implemen- tation, shown im FIE-€59(b), uses a pseudo-nMOS NOR gate buffered with two inverters. The NOR gate transistors can be made minimum size, and the inyetters can be sealed appropriately to drive the word line. Large fan-in AND gates can also be constructed from smaller NAND and NOR gates, as shown in Fig. 8.59(c). Figure 8.60 shows two possible layout styles (in sym-83 MEMORY ELEMENTS 575 Has = SR o_o TD | Ik ee & 4 sets acto . ce . fore fr oe fee 1 al Te o| Peel y i fen o » FIGURE 8.59 Row-decoder wos circuits: (a) complementary e AND gate; (b) pseudo-nMOS ~ gate; (c) cascaded NAND, NOR gates bolic form) for the row decoders. One passes the address lines over the decode gates, while the other uses @ more standard cell style. Choice would depend on the size of the decoder in relation to the size of the RAM cell, Often, speed requirements or size restrict the use of single-level decoding, such as that shown in Fig. 8.59, The alternative is a predecoding scheme, which is illustrated in Fig. 8.61 (a). Here the (n-k) row address ines are split into a p-bit predecode field and a g-bit direct decode field. The q-bit decode field requires a gate per word line, so q is chosen to suit the pitch of the RAM cell. The p-bit predecode Tield geMrates 2? predecode lines (4 in this exam- ple), each which Wed MI Tete, (8 in this exam- ple). Figure 8.61(b) shows a possible implementation of a.predecode scheme, where the predecode gate is a NAND gate and the word-decode gate isa NOR gate. An additional input (~clk) has been included in the NOR gateeo T ft [>o——wrs © 1 via pass gates enabled by the column-address lines. The address decoding is in essence distributed. Decoders for bit and ~bit lines are shown, although one of these may be omitted for single-ended read operations. The read (and. usually of lesser importance, write) operations are somewhat delayed by the series-transmission gates. However, in comparison with gate delays these 8.3 MEMORY ELEMENTS 57 FIGURE 8.61 ‘Predecode circuits: (a) basic approach: (b) actual imptementation, (6) pseudo-nMOS example83 MEMORY ELEMENTS 579 Cer 4 selcted data bee — It T mas Le Tose amps and wre ce “esos data wacts | acts | -2ee> + ae ees If the delay of the series-pass gates was troublesome, the decoder shown ir Fig. 8.64 could be used. Here a NAND decoder is employed on a bit-by- bit basis to enable complementary transmission gates (single transistors may be used whére possible) onto a common pair of data lines, These are then routed to a sense amplifier and write circuitry. 8.3.1.1.5 Sense amplifiers Many sense amplifiers have been invented to provide faster sensing, smaller layouts, and lower power-dissipation sensing.°> The simple inverter sefise amplifier provides for low power sensing at the expense of speed. The differ- ential sense amplifier can consume a’significant amount of DC power (Fig. 8.54). Alternatively, one can employ clocked sense amplifiers similar‘ to the SSDL gate shown in Fig. 5.40. 8.3.1.1.6 RAM timing budget The critical path in a static RAM read cycle includes the clock to address delay time, the row address driver time, row decode time, bit-line sense time, and the setup time to any data register. The column decode is usually not in DECODER, - FIGURE 8.63 Tree-style column decoder Selecting 2k out of 2™ btte off aecened Bou.CYOMIGNT MUR KESSHBLE Memory She cam — poalion, ezantnes’ a dala word and compares thi dita. twitth “internally ‘stored’ data. af any deta word baternally matches the lp data word » the cam signals Mhet “there t2 @ watch. Shee match grok, ean be pameh ar word liner a specific She stractwe T—r———C—C=t look-orxide — bucPfer tin the = virtual m™memoaty dook up ta ® anieropan cemor- CAM Memory firea : ee sf Yet tt ie J Fig i Boxte cary ‘ Morteh, t Ram to emable data word tb be olp. —— eam Memory Array dota ~ | Nom bit twoordsy “TUTTIP TTT 20% tetek ts ae RAM toord dines | RAM Mem. Ara! N Me? bit eootds, Data out fa: applics™ as translation lookaside + babbed. ‘ A emMoz CAM cell consul of normal static RAM cell with transitive oN, and No » Which form — XOR get, & Neg which ws dixbtbultd nog pul coon, Waiter are ued to store the mabeh clot tm the celle, Whereas rArads are wed for textingaf +7 \ fy: CMos cay | cel] % tg cae Novinall RAM ReodJtosit, ektn a trl a a - a _ al mH tet Sieh ~modenls) 5 Fe fet : LH Re 1E+ omateh ls) et raateh() HE a 2 Bl i He te Louth), = Lr mateh- Prechawe, PES oay Ae — 7 1 CAM cell g eq: oray Corcuit,A mMalben epee presen my ty be tatechet on the bit lines buck met aveerting woad line, A \ oppeare on gate of MZ i¢ the dota un the aell is mot equal t dot on wo bit dines» She chairs of NZ Tre of celfy ln the = Sore = FU axe Commoned , Yhese form Qixbvibubed Nor gale, Each match lime Cmateh> remains high UP the dots Un the wow watches rr ——“—NOS—NC—s—C—C==—=N may be used do anertt the word limee on a RAM. Seria Accese MEmMoRY Sezal aeaex, memories C shift regs) ate. of we im Signal- proeewing application for Storage and delaying Signal St can be simulated by a rem & the provides — Smallest tmplernentatign Hees. cmos Static RAM ds ety Area ebpictent . eam ih Swapunded by countere. Some. time, a dedicated shift register Memory may be oppaoprlale, from donsity, Speed oy floorp Lanning viewpt. fig > Blocks of byte Shift vege ae dalayod by Go,16,8)4,2 & t elk ogeles L omnzes Contro) the pow- wound of dlay becks tp yietd appanpatata delay amount. Fach mem cell a & ave0e wn. nddolayes> aatay <4> © AMAYCS> -dlalny C2> jalayer> 72 {4 - 04, 2-Sk Qo-clage — 16-Sbage B-stoge b-Clage , 2-Sloge, oa er? cry ak eR oa big: Tapped delay dine architerlure. fig ext Cmem cele), oh a : Rom Creap only memory) > St can be tmplemented bit of Atovage, 98 a in that the Stole a even power. Sb ds Dror. . 5D Cam wre array for ultra. Small Rome Slow. with only one Tr Per a etatic memory ruil. sotaime L Endefinetely without generally Emp lemenicd ag Q Nor NOND but wilh be.atta ©) Wastey dati C2>, Hg: Basic Rom archictectine. Domino logic. ROM can low down btt- line tramilin for re fone. co Ose dynamic, Rom, NOR avoy 0 ie C Row | aan 4 H Prec} bit {| £eg: dynamic ROM Cktyy, Hee toord diner ae forced oe being precharged. Sin enuree that pe current doesnot flow. After bbt- line pull-upe have been tuned oft, the lwoed- line diverge are axerted and one tword dime de active. She vege cawfal destgre Obs ‘toning chain of Seqtuance of every, bw while bit Ene.