MIPI Test and Debug Interface Framework

White paper
Approved Version: 3.2 7 April 2006

Copyright 2006 MIPI Alliance, Inc. All rights reserved.

NOTE: This is an informative document, not a MIPI Specification.

Various rights and obligations which apply solely to MIPI Specifications
(as defined in the MIPI Membership Agreement and MIPI Bylaws) including,
but not limited to, patent license rights and obligations, do not apply
to this document.

Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:

MIPI Alliance, Inc.

c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
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1. Introduction
The IEEE 1149.1 (JTAG) standard has proven to be a very robust solution to a variety of test and debug
systems, enabling a rich ecosystem of compliant products to evolve across virtually the entire electronics
industry. Yet increasing chip integration and rising focus on power management has created new
challenges that were not considered when the standard was originally developed. Hence, an obvious need
has emerged for a new test and debug access technology, which tackles these new possibilities, while
preserving compatibility with the original JTAG standard.

To meet this need, the Mobile Industry Processor Interface (MIPI) Test and Debug Working group has
selected a new test and debug interface, called P1149.7 1 , which builds upon the IEEE1149.1 standard.
P1149.7 enables critical advancements in test and debug functionality while maintaining compatibility with
IEEE 1149.1. In addition to P1149.7, the MIPI test and debug interface specifies how multiple on-chip TAP
controllers can be chained in a true IEEE1149.1 compliant way. It also specifies a System Trace Module
(STM). STM consists of a System Trace Protocol (STP) and the Parallel Trace Interface (PTI). STM is
used to aid in software debugging: it collects software debug and trace data from internal buses which is
encapsulated and output to an external trace capture device using a minimum set of ASIC pins. The
signals and pins required for these interfaces are given through the MIPI Alliance Recommendation for
Test & Debug - Debug Connector, also part of the MIPI test and debug interface.

The main blocks of the MIPI Debug and Trace Interface (DTI), seen from outside of the system, are shown
in Figure 1. To summarize, these are:
The Debug Connector
The basic debug access mechanism: JTAG and / or P1149.7
A mechanism to select different TAP controllers in a system (Multiple TAP control)
The System Trace Module (STM - System Trace)

Debug Connector

JTAG and/or
P1149.7

S O C
System
Trace

Multiple TAP
Control

MIPI DTI Components

Figure 1 Overview of the MIPI DTI components

Although this effort was motivated by needs of the mobile industry, the requirements which drove the
specification development are universally applicable to virtually all market segments.

1
P1149.7 was previously called compact JTAG (cJTAG) and is currently in the process of standardization at IEEE.

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2. IEEE1149.1 compatibilty
The P1149.7 specification creates a superset of the IEEE1149.1 interface standard for test and debug,
while remaining compliant. A primary objective of P1149.7 was to preserve the industrys hardware and
software investments in this standard. With P1149.7, existing tools or Debug and Test Systems (DTS),
such as an IEEE1149.1 emulator, and Target System (TS) chips, can simply be extended with adapters to
convert to the P1149.7 interface (= The Link) as shown Figure 2(a).

The Link
IEEE
1149.1 Core 0
Interface
IEEE 1149.1 4 or 5
P1149.7 2, 4 or 5, 6
Core 1
Adapter Core 2
Debug and Test External
System Upgrade Aux 0
P1149.7
Aux 1
Circuitry

(a) Standard IEEE 1149.1 emulator with an external P1149.7 Adapter

The Link
IEEE
1149.1 Core 0
Interface
P1149.7 2, 4 or 5, 6
Core 1
Standard ICE Core 2
Adapter
Circuitry Circuitry Aux 0
P1149.7
Aux 1
Circuitry

(b) P1149.7 Capable Emulator

Figure 2: P1149.7 Overview.

A high level diagram of the DTS and TS connectivity is shown in Figure 3. The DTS P1149.7 adapter
(circuitry) and the Targets P1149.7 circuitry communicate using either JTAG (TCK, TMSC, TDI, TDO) or
P1149.7 (TCK, TMSC) signals. An operating mode change is synchronized and happens concurrently in
both the DTS and TS. Collectively, this circuitry is called the The Bridge.

The Bridge
The Link
Host System Target System
TCK
TCK TCK
Host TMSC
TMSC TMSC Target
IEEE P1149.7 IEEE
TDI P1149.7
Adapter TDO TDI
1149.1 or Circuitry TDI TDO Circuitry 1149.1
TDO
RTCK
RTCK RTCK

Although TCK is shown as bi-directional, it is actually sourced by the system or debug and test equipment
P1149.7 and IEEE 1149.1 IEEE 1149.1
Modified IEEE 1149.1
with RTCK

Figure 3: The Bridge.

The P1149.7 operating mode provides a compact version of the IEEE1149.1 interface, using only two pins
TCK and TMSC. The P1149.7 architecture maintains the underlying JTAG-compliant control mechanism

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while at the same time providing several extensions to JTAG. Instead of a radical departure from the
existing standard, P1149.7 represents the natural evolution of the standard.

The P1149.7 operating mode is JTAG-compliant from power-up. Conventional JTAG control sequences
are used to switch between JTAG-compliant standard mode and the P1149.7 advanced mode. The DTS
debug software can automatically determine whether it is communicating with existing JTAG components
(legacy), a mix of legacy and P1149.7 components, or a system built with only P1149.7 components. It can
also determine whether the components are configured in a Star or Series configuration.

2.1. Extended functionality and reduced pin count

The P1149.7 architecture supports the following features:

2 pin operation (as compared to 4 / 5 pins of standard JTAG or 5 / 6 pins if also JTAG Return Test
Clock [RTCK] is included). The latter interface is referred to as Modified IEEE 1149.1.
Target operating frequencies (TCK) from DC to 100 MHz
Compatible with all hardware/software that uses the JTAG standard
Provides debug access that is independent of CPU and debug technology
Supports multi-device communications ports with up to 16 devices per port
Creates data transport channels superimposed on JTAG stable states such as Idle and the two
Pause states. The stays in these states may be used to move background or custom instrumentation
data using P1149.7 or private protocols. (BDX/CDX)
Power domain awareness at target and board level
Comprehends synchronized operations across multiple debug ports
Tolerates slow system response e.g., power save modes or component clock limitations
Includes failsafe and robustness features

The P1149.7 architecture builds on existing technology and legacy hardware/software. This evolutionary
approach maintains the value of the vast majority of IP created since the JTAG standards inception.

2.2. Device types

SoCs can be designed with a P1149.7 Wide interface (4 pins) or a P1149.7 Narrow interface (2 pins).

The P1149.7 Wide devices have the normal TCK, TMCS, TDI, TDO pins and can be used as a normal
JTAG device, but can also be switched to advanced operating mode (2-pin protocol).
Devices with a P1149.7 Narrow interface only have the TCK and TMSC pins and will only carry out
advanced messages.

At board level, chips with mentioned P1149.7 interfaces can be mixed with ICs that have a standard JTAG
interface as shown as example in Figure 4. Various configurations of Chips and DTS interface connections
are possible. This configuration is an example where the DTS has two ports (Port A and Port B) that share
TMSC and have separate TCKs.

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Chip with Chip with P1149.7 Chip with P1149.7

JTAG WIDE NARROW

T T
T T T T T M T T T M
C M D D C S D D C S
K S I O K C I O K C

Multi-use
Port A Port B
pins
Figure 4: Chips with JTAG and P1149.7 interfaces mixed on the same board.

2.3. Single and multiple P1149.7 devices

An example of the Debug and Test System connected to a Target System containing P1149.7 Narrow
devices is shown in Figure 5 and Figure 6.

Figure 5: Single Port, Single Device Target System.

In the multi-device configuration the Target System devices share TCK and TMSC. The multi-device
protocol aspects of the P1149.7 architecture have provisions to assign Link IDs to each device connected
to the TMSC pin. These Link IDs are then used to select a device when the Debug and Test System needs
to address the targeted device.

Figure 6: Single Port, Multi-device Target System.

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2.4. Data formats

Several data formats (also called P1149.7 packets) between the DTS and TS are possible. These packets
consist of serialized TDI, TMS and TDO information bits on the TMSC pin, sent/received by the DTS
to/from the Target System. For example, in Figure 7(a) a data write/read type of transfer is shown where
(inverted) TDI and TMS bits are made available at the TMSC pin during TCK periods. A RDY bit, driven by
the selected P1149.7 device, extends the packet until the TDO bit is ready to transfer to the DTS. The use
of RDY-bits provides for synchronizing operations where the TS data availability may be variable. These
serialized JTAG signals from the DTS are reconstructed to JTAG signals in the Target System P1149.7
adapter. Other data formats, such as the one shown in Figure 7(b), transfer data (nTDI bits) only e.g. for a
fast data download to the target system. Other packet formats address other use cases.

TCK

Precharge Precharge
TMSC nTDI bit TMS bit to 1
RDY bit to 1
TDO bit
0..n TCKs
DTS to TS DTS to TS TS to DTS TS to DTS
delay
(a) Write/read data type of message

TCK

TMSC nTDI bit nTDI bit nTDI bit nTDI bit nTDI bit nTDI bit nTDI bit nTDI bit
DTS to TS DTS to TS DTS to TS DTS to TS DTS to TS DTS to TS DTS to TS DTS to TS

(b) Fast download of data from DTS to TS

Figure 7: Example of two P1149.7 data formats.

2.5. JTAG extensions

There is a facility within P1149.7 that allows hot connect to the Target System without system disturbance.
This facility, called Firewall, disconnects the JTAG devices from the TS P1149.7 adapter by gating off the
adapters TCK output to the connected JTAG devices. Debug software can use a standard JTAG
sequence to disable this firewall.

Another capability, called Super Bypass, may be used in the JTAG mode of a P1149.7 enabled chip. Super
Bypass provides a one-bit bypass between TDI and TDO for both instruction and data scans, thus reducing
the scan path length in a system.

Another P1149.7 capability, the BDX/CDX (Background Data Transport / Custom Data Transport) mode
can be used for transferring data between the DTS and target system when stable. Transfers occur when
stable TAP states are reached (e.g. Idle, Pause-IR/DR, or Shift-DR/IR). These transfers support e.g. user
I/O, outputting instrumentation trace information, and custom protocols like those for non-JTAG debug
technologies.

3. P1149.7 and Multiple On-Chip TAP Controllers

Conventional chaining of TAP controllers, which are part of the cores in a SoC, may lead to non-
compliancy to the IEEE1149.1 standard. Within the MIPI WG, an approach has been defined that uses a
Multiple TAP Control module to address this issue (see Figure 8).

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The Multiple TAP Control module ensures that after a JTAG reset, the device strictly adheres to the IEEE
1149.1 standard. It does so by connecting the Chip level TAP between the SoCs TDI and TDO pins. The
Chip level TAP is responsible for providing the SoCs boundary scan operation, control of and access to
any internal test scan logic, and the SoCs identification code. Through private and undocumented means,
it is allowed to control the Multiple TAP Control from the Chip level TAP controller to include other
embedded TAP controllers between the SoCs TDI and TDO pin as well, as may be required for particular
test and/or debug operations.

TS P1149.7 Chip level SoC

adapter TAP TAP TAP TAP
TCK
control
TMSC

CK
S

TKMS

S
TDO

TDO

TDO

TDO
TDO
TMS

TCK
TMS

TK
TCK

K
TDI

TKM

TM
TC
TDI

TDI

I I

I
TC
TM

TM
TD
TD

TD
TD

TC
S

S
TC

TC

TD
TD
I

I
TDO

T
Multiple
MultipleTAP
TAPController
Control

Figure 8: SoC with P1149.7 adapter and Multiple TAP Control.

4. STM System Trace Module

The System Trace Module (STM) helps in software debugging (see Figure 9). It collects software debug
and trace data from internal ASIC buses, encapsulates the data, and sends it out to an external trace
device.

STM supports the following features:

Highly optimized for SW generated traces
Automatic time stamping of messages
Allows simultaneous tracing of 255 threads without interrupt disabling
Configurable export width 1/2/4 pin + dedicated clock + optional return channel
o Minimal pin usage 2 pin (1 data + 1 clock)
o Maximum pin usage 6 pins (4 data + 1 clock + 1 return channel)
Maximum planned operating frequencies 166 MHz (double data rate clocking)
Provides a maximum bandwidth of slightly above 1 Gbit/s (theoretical max. 1.6 Gbit/s)
Supports up to 255 HW trace sources
Support for 8,16,32 and 64bit data types

A maximum of 255 different bus masters can be connected to the STM trace port via a bus arbiter. The bus
masters can be configured for either SW or HW type to optimize the system for different types of trace
data.
SW type master messages are used to transmit trace data from OS processes / tasks on 256 different
channels. The different channels can be used to logically group different types of data so that it is easy to
filter out the data irrelevant to the ongoing debugging task. The message structures in STM are highly
optimized to provide an efficient transport especially for SW type master data. An example of a trace data
output is given in Figure 10.

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Processors and SW data

DMA controllers
Arbiter PTI/
Trace External
Trace data
bus STM trace PC
device
Trace HW data
peripherals DTS

Return channel
(serial bus / P1149.7)
ASIC (optional)

Figure 9 Example of STM high-level connections

Clock

Data Master C8 D8 NULL

M[7:4] M[3:0] C[7:4] C[3:0] D[7:4] D[3:0]
out 0001 0011 0100 0000

Clock

Data D8TS NULL NULL Master

D[7:4] D[3:0] T[7:4] T[3:0] M[7:4]
out 1000 0000 0000 0001

Figure 10 Example timing of the STM output signals on a 4-bit double data rate interface

5. System Overview
Figure 11 shows an example of a MIPI system. This system can be implemented either as a single chip or
a set of chips inside a System-in-Package (SiP) or on a board. In the system shown in Figure 11, we have
two subsystems, each of which contains the same MIPI functionality. A P1149.7 module provides JTAG-
compliant control over the in-subsystem TAP controllers. The CDX, BDX, and STM modules allow a variety
of streaming real-time data out of the subsystem to the host environment. In this example, each subsystem
has a dedicated trace port.

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JTAG-compliant control
RTCK TDO TMS(C) TCK TDI

MIPI System

RTCK TD TMSC TCK TDI TDO TMSC TCK TDI

STM P1149.7 P1149.7 STM

CDX/BDX Multiple TAP Control CDX/BDX Multiple TAP Control

TAP1 TAP2 TAPN TAP1 TAP2 TAPP

IP1 IP2 IPN IP1 IP2 IPP
subsystem 1 subsystem M
Data[3:0] Clk Data[3:0] Clk

PTI PTI

Parallel Trace Interface

Figure 11: Example MIPI System Overview.

It is however not always possible to have dedicated pins for each subsystems parallel trace interface. In
those cases, an in-system Pin Manager/Multiplexer module has to be used to select which STM module
can output on the parallel trace interface pins, as shown in Figure 12.

JTAG-compliant control
RTCK TDO TMS(C) TCK TDI

MIPI System

RTCK TDO TMSC TCK TDI TDO TMSC TCK TDI

STM P1149.7 P1149.7 STM

CDX/BDX Multiple TAP Control CDX/BDX Multiple TAP Control

TAP1 TAP2 TAPN TAP1 TAP2 TAPP

IP1 IP2 IPN IP1 IP2 IPP
subsystem 1 subsystem M
Clk DataI[3:0
Data[3:0] Clk
Pin Manager/Multiplexer

Parallel Trace Interface

Figure 12: MIPI system overview with trace pin sharing.

When using a P1149.7-compliant Debug and Test System, the required number of control pins goes down
to two, as is shown in Figure 13.

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P1149.7-compliant control
TMSC TCK

MIPI System

TMSC TCK TMSC TCK

STM P1149.7 P1149.7 STM

CDX/BDX Multiple TAP Control CDX/BDX Multiple TAP Control

TAP1 TAP2 TAPN TAP1 TAP2 TAPP

IP1 IP2 IPN IP1 IP2 IPP
subsystem 1 subsystem M
CLK Data[3:0]
DataI[3:0] Clk
Pin Manager/Multiplexer

Parallel Trace Interface

Figure 13: MIPI system overview with trace pin sharing and P1149.7-compliant control

6. Basic Debug Connector

As the connector was not part of the original JTAG standard, a large number of different JTAG connectors
have emerged. The recommendation of a standard connector for P1149.7 tries to avoid this for the future.
Different applications and use cases have different requirements for the connector.
The definition must be flexible enough to handle all these requirements. A scalable 0.05 inch connector
provides a cheap, small and robust target connection and is available in many variants (including lockable
ones) from multiple connector vendors. The pin out allows scaling the connection to meet different
requirements. This includes very small footprint connections (down to 6 pins), legacy JTAG support
(including vendor specific pins) and system level trace support (STM). The picture below shows the
contrast between the size of the recommended 0.05 inch connector (10-pin variant as example) and that of
the often used 20-pin 0.1 inch JTAG connector for the same test and debug functionality.

20-pin 0.1 inch JTAG

connector

10-pin 0.05 inch Basic

Debug connector

7. Conclusion
Often the developer needs to debug an end product, e.g. a mobile phone, with very limited interconnect
and board space options. For these applications, the MIPI Test and Debug P1149.7 interface and Basic
Connector represent a convenient and board space saving replacement for the conventional 5 pins JTAG
interface. The System Trace Module, part of the MIPI Test and Debug Framework, provides the user with
sufficient trace and debug features, whereas P1149.7 and the Multiple-TAP Control allow the companies

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throughout the industry to continue to leverage their substantial investments in JTAG-compliant tooling and
methodologies.

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