TUTORIAL 6

1. Realize Full Subtractor using 3x8 decoder and basic logic gates

2. Implement Full Adder using minimum number of NOR gates only.

3. Realize 2 bit magnitude comparator, using one bit comparator as black box, which is having two
inputs A and B, each of 2 bits, and produces three outputs G, L and E for A>B, A<B and A=B, respectively.

4. Implement the four Boolean functions using three half-adder circuits.

D= ABC, where is XOR gate.
E= ABC +ABC
F= ABC + (A + B) C
G= ABC

Q. 5 Implement the following the multiple output combinational logic circuit using a 4 line-to- 16 line
decoder:

1 = (0, 1, 4, 7, 12, 14, 15)

2 = (1, 3, 6, 9, 12)

3 = (2, 3, 7, 8, 10)

4 = (1, 3, 5)

Q. 6 Design a combinational circuits that compares two 4-bit numbers to check if they are equal. The
circuit has one output x, so that x=1, if A=B and x=0 if A is not equal to B.

Q. 7 Implement a Full adder circuit using two half adders and one OR gate. If the gates for realization of
the complete circuit having following delays: XOR gate 20 ns, AND gate 10 ns, and OR gate 10 ns,
then determine the propagation delay to obtain the sum and carry outputs.

Q. 8 A 4-bit parallel adder is implemented using full adders. It is known that each full adder takes 20ns
and 10 ns to produce sum and carry output, respectively. Determine the time required to complete the
4-bit addition.

Q9.Without any initial carry, determine the number of half adders and OR gates for making a 4-bit
parallel full adder.
Q 10. A 1-bit full adder takes 20ns to generate carry-out bit and 40ns for the sum bit. What is the
maximum rate of addition per second when four 1-bit full adders are cascaded?

Q 11. Design a 5-bit comparator using a single 7485 and one gate.

Q 12. Considering active low outputs of decoder, implement the following multiple output
combinational circuit using a 4-line to 16-line decoder.

1 = (1, 2, 4, 7, 8, 11, 12, 13)

2 = (2, 3, 9, 11)

3 = (10, 12, 13, 14)

4 = (2, 4, 8)

Q 13. Design a BCD to Seven Segment Decoder.

Q14. Design a 4*16 Decoder using 3*8 decoders.

Q15. Design a combinational circuit that accepts a 4-bit BCD number and generates an output number in
binary form equal to the square of the input number.