This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2017.2727551, IEEE Access
A Fundamental Frequency Hybrid Control
Technique Based Three Phase Cascaded
Multilevel Inverter Topology
Sidharth Sabyasachi, Student Member, IEEE, Vijay B. Borghate, Member, IEEE, Raghavendra Reddy
Karasani, Student Member, IEEE, Santosh Kumar Maddugari, Student Member, IEEE and Hiralal M.
Suryawanshi, Senior Member, IEEE
AbstractA three phase cascaded multilevel inverter topology
and a hybrid control technique are presented in this paper. The
topology is derived from a proposed module of addition and
subtraction of sources (MASS). An attempt is made to optimize
the component count, viz., power switches count, gate drive
count, capacitor count, diode count and source count. The
operating modes of basic module and the proposed three phase
topology are explained. The analysis is presented for both
symmetrical and asymmetrical configurations. The fundamental
frequency hybrid control technique, which is derived from
Nearest Level Control (NLC) and Switching Frequency Optimal
(SFO) algorithms, is presented. The power semiconductor
switches in the topology are driven by gating signals generated
with hybrid SFO-NLC technique. The necessary comparisons are
done to show the enhanced features with the view of optimized
component count and power quality. The simulation results are
carried out by MATLAB/SIMULINK software tool under both
steady state and dynamic conditions. Experimental results are
presented to validate the simulation results.
Index TermsModular multilevel inverters, Nearest level
control (NLC), Switching frequency optimal (SFO), Total
harmonic distortion (THD).
I. INTRODUCTION
T HE features of multilevel inverters (MLIs) have made
them a superior candidate for the DC-AC power
conversion [1]-[2]. The bias towards the distributed generation
(DG) is getting increased recently. The renewable energy
systems (RES) play a vital role in fulfilling the increased
power demand. The power quality is one of the key parameter
in this emerging area of power generation. The power quality
is improved by adapting the MLI technology for DC-AC
Sidharth Sabyasachi is with the Visvesvaraya National Institute of
Technology, Nagpur, India (e-mail: sidharth.mana@gmail.com).
Vijay B. Borghate is with the Visvesvaraya National Institute of
Technology, Nagpur, India (e-mail: vijay_borghate@rediffmaill.com).
Raghavendra Reddy Karasani is with the Visvesvaraya National Institute of
Technology, Nagpur, India (e-mail: raghu.vnitnagpur@gmail.com).
Santosh Kumar Maddugari is with the Visvesvaraya National Institute of
Technology, Nagpur, India (e-mail: msanthu245@gmail.com).
Hiralal M. Suryawanshi is with the Visvesvaraya National Institute of
Technology, Nagpur, India (e-mail: hms_1963@rediffmail.com).
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power conversion stage [3]. The three basic topologies used
for RES are Cascaded H-bridge (CHB) [4], Neutral point
clamped (NPC) [5]-[6] and Flying capacitor (FC) [7]. The
CHB is fed with multiple sources, whereas the other
aforementioned are of single source type. The single source
topologies lack in modularity and have the tendency to
increase the additional components viz., capacitor count, and
diode count other than switching devices for higher level
generation. The modular multilevel converters (MMCs) [8]-
[9] are introduced for HVDC power transmission. The MMCs
are associated with voltage balancing issues across DC-link
capacitors, which are connected to a single source. The RES
enabled the use of multiple source topologies like CHB, which
are free from capacitor balancing issues. To enhance the
efficiency by reducing the switching losses, many topologies
with reduced switching device count are presented in [10].
The MLI configurations are classified as symmetrical or
identical sources fed and asymmetrical or unequal sources fed.
A three phase topology in symmetrical configuration is
proposed in [11] for renewable energy applications. A three
phase power cells topology with restructured CHB is
presented in [12] to enhance the even distribution of power
across the each power cell and modularity. The high frequency
direct grid connected RES with MMCs are presented in [13].
A Three phase five level enhanced structure is reported in
[14]-[15]. The hybrid three phase structures are proposed with
improved control technique in [16]-[17]. A single DC source
hybrid seven level three phase topology is presented in [18]
with hybrid control technique to enhance efficiency. A three
phase symmetrical topology with reduced component count is
proposed in [19]. As asymmetrical configuration generates
more level than symmetrical operating mode but the readily
availability of DC sources of different magnitudes is a
concern. So single phase topologies are proposed, which can
work in both the configurations. An asymmetrical structure
with lower source count is presented in [20]. These single
structures can be extended to three phase operation. In [21] a
three phase hybrid cascaded modular multilevel inverter
(HCMMLI) is presented, which reduced the switch count, gate
drive count compared with classical topologies.
In this paper, a three phase cascaded structure with
optimum component count is presented. A simple fundamental
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frequency hybrid control technique is introduced to generate
the gate pulses for the switching devices.
II. PROPOSED TOPOLOGY
The proposed topology is basically derived from MASS and
polarity reversal unit (PRU) as discussed below, for
synthesizing multi-levels in the phase output voltage
waveform of the load.
C. Three phase cascaded multilevel inverter topology
The proposed modular multilevel inverter is developed from
MASS. One module is connected with PRU in each phase as
shown in Fig. 3. The MASS modules can be cascaded to
generate L levels in the phase load voltages VA, B, C and (2L-1)
levels in the line-to-line voltages VAB, BC, CA as depicted in Fig.
4.

A. Module of Addition and Subtraction of Sources (MASS)

The MASS is the building block of the level generation in
the proposed converter equipped with two DC voltage sources
V1 and V2 (>V1). It is constructed with four unidirectional
switches S1, S4, S12 and S11 and one bi-directional switch S2
(with single drive control) as shown in Fig. 1 (a). The
switching device pairs (S1, S11) and (S4, S12) should operate in
complementary mode to avoid the short circuit of voltage
sources. The Fig. 1 (b) shows the voltage across MASS VM
generated with five levels viz., 0, V1, V2-V1, V2, and V1+V2.
The corresponding switching modes are shown in Fig. 2 (a)-
(f).
B. Polarity Reversal Unit (PRU)
As discussed in the above section, the MASS has produced
five positive voltage levels including zero level in the module
voltage VM. The bi-polar voltage levels in the load voltage of
each phase are acquired by connecting H-bridge at the load
end. The H-bridge connected in phase of Fig. 3 functions as
polarity reversal unit. The simultaneous switching on the
devices pair (Ta1, Ta2) and (Ta3, Ta4) on the opposite arms
enables the voltages levels of both polarities in the phase load Fig. 2 Switching modes of MASS (V2>V1) for levels: (a) 0, (b) V1, (c) V2-
V1, (d)-(e) V2 and (f) V1 +V2.
voltage VA. The zero voltage level is attainable at the module
level itself unlike the topologies reported in [22]-[23]. This
facilitates to operate higher rated PRU switching devices at
fundamental frequency.

Fig. 3 Proposed three phase cascaded modular multi-level inverter.

Fig. 1 (a) Proposed module of addition and subtraction of sources

(MASS) and (b) Voltage across proposed MASS VM.

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Va11 = Va12 = = Va1M

Vb11 = Vb12 = = Vb1M = 4 M 1V (2.a)
Vc11 = Vc12 = = Vc1M
Va 21 = Va 22 = = Va 2 M

Vb 21 = Vb 22 = = Vb 2 M = 22 M 1V (2.b)
Vc 21 = Vc 22 = = Vc 2 M
2) Case 2
As per (3.a)-(3.b), the DC sources of distinct magnitudes
are employed in MASS of each phase. It generates 9 levels in
the load phase voltages VA,B,C and 17 levels in the line to line
voltages VAB,BC,CA. The possible switching combinations for
phase A are presented in TABLE III.
Va11 = Va12 = = Va1M

Vb11 = Vb12 = = Vb1M = 5M 1V (3.a)
Vc11 = Vc12 = = Vc1M
Va 21 = Va 22 = = Va 2 M

Vb 21 = Vb 22 = = Vb 2 M = 3 5M 1V (3.b)
Vc 21 = Vc 22 = = Vc 2 M
Fig. 4 Generalized three phase cascaded multi-level inverter for L levels.
TABLE I
SWITCHING COMBINATIONS FOR SYMMETRICAL OPERATION
Va11=Va12=V
III. MULTILEVEL INVERTER CONFIGURATIONS L.No. Sa1 Sa11 Sa2 Sa12 Sa4 Ta1 Ta2 Ta3 Ta4 VA
The magnitude of DC sources decides the number of levels 1 1 0 0 1 0 1 1 0 0 2V
L in load voltage VA. The proposed structure works well with 1 0 0 0 1 1 1 0 0
2 1 0 1 0 0 1 1 0 0 V
both symmetrical and asymmetrical configurations. The
0 1 0 1 0 1 1 0 0
possible operating configurations of the MLI shown in Fig. 3 3 0 1 0 0 1 1 1 0 0 0
and key parameters are analyzed in the following section, 1 0 0 0 1 0 0 1 1
considering M number of MASS shown in Fig. 4. 4 1 0 1 0 0 0 0 1 1 -V
0 1 0 1 0 0 0 1 1
A. Symmetrical Configuration 5 1 0 0 1 0 0 0 1 1 -2V
The MASS in each phase is supplied with equal magnitude TABLE II
of DC sources and can produce 5 levels in the load phase SWITCHING COMBINATIONS FOR ASYMMETRICAL CASE 1 OPERATION
voltages VA,B,C and 9 levels in the line to line voltages Va11= V and Va12=2V
L.No. Sa1 Sa11 Sa2 Sa12 Sa4 Ta1 Ta2 Ta3 Ta4 VA
VAB,BC,CA. The switching combinations for phase A are
1 1 0 0 1 0 1 1 0 0 3V
presented in TABLE I. The switching operations for other
1 0 1 0 0 1 1 0 0
phases B and C are displaced by 1200 and 2400, respectively. 2
0 1 0 1 0 1 1 0 0
2V
Va11 = Va12 = = Va1M 3 1 0 0 0 1 1 1 0 0 V
=V (1.a) 4 0 1 0 0 1 1 1 0 0 0
Va 21 = Va 22 = = Va 2 M
5 1 0 0 0 1 0 0 1 1 -V
Vb11 = Vb12 = = Vb1M 6
1 0 1 0 0 0 0 1 1
-2V
=V (1.b) 0 1 0 1 0 0 0 1 1
Vb11 = Vb12 = = Vb1M 7 1 0 0 1 0 0 0 1 1 -3V
Vc11 = Vc12 = = Vc1M
=V (1.c) TABLE III
Vc11 = Vc12 = = Vc1M SWITCHING COMBINATIONS FOR ASYMMETRICAL CASE 2 OPERATION
Va11= V and Va12=3V
B. Asymmetrical Configuration L.No. Sa1 Sa11 Sa2 Sa12 Sa4 Ta1 Ta2 Ta3 Ta4 VA
1 1 0 0 1 0 1 1 0 0 4V
The MASS in each phase is supplied with distinct 1 0 1 0 0 1 1 0 0
magnitude of DC sources. 2 3V
0 1 0 1 0 1 1 0 0
1) Case 1 3 0 1 1 0 0 1 1 0 0 2V
4 1 0 0 0 1 1 1 0 0 V
The MASS in each phase is supplied with DC sources of 5 0 1 0 0 1 1 1 0 0 0
magnitude as per (2.a)-(2.b) and can produce 7 levels in the 6 1 0 0 0 1 0 0 1 1 -V
load phase voltages VA,B,C and 13 levels in the line to line 7 0 1 1 0 0 0 0 1 1 -2V
voltages VAB,BC,CA. The switching combinations for phase A are 1 0 1 0 0 0 0 1 1
8 -3V
presented in TABLE II. 0 1 0 1 0 0 0 1 1
9 1 0 0 1 0 0 0 1 1 -4V

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In comparison with symmetrical, the asymmetrical structures presented in the literature and hybrid modular type
configuration produces more levels. structures with possible MLI configurations are also included
The rating of the inverter mainly depends on voltage and in comparative analysis. The total component count in each
current ratings of switching devices. The load decides the structure CTotal (7) in terms of L is listed in the TABLE VI.
current rating, where as the voltage rating depends on the CTotal = G + GD + S + D + Cc (7)
circuit operating conditions. The standing voltage VSV is the The Fig. 5 shows CTotal characteristic curves of proposed
parameter to analyze the voltage rating of inverter. The VSV is topology in comparison with various three phase topologies in
related to maximum voltage Va,max of MLI and voltage across terms of level count L. The Fig. 5 (a) represents the CTotal
all switches in each MASS. These are mathematically curves of various topologies in symmetrical configuration.
expressed as follows The FC and NPC topologies have more CTotal due to the
Va ,max = VaH = Va11 + Va 21 + Va12 + Va 22 + + Va1M + Va 2 M (4) requirement of higher diode count D and capacitor count CC
for producing more levels, respectively. The proposed MLI
M
Va ,max = VaH = (Va1i + Va 2i ) (5) structure CTotal curve P has less count compared to classical
i =1 and other existing topologies in symmetrical configuration.
M M TABLE IV
VSV = 3 PRU SV + MASS SVi =3 4Va, max + MASS SVi (6) GENERALIZATION OF PARAMETERS PER PHASE WITH M MODULES
i =1 i =1 Symmetrical Asymmetrical configuration
Parameter
configuration Case 1 Case 2
The switch count (G), Source count (S), Gate drive count
(GD) are the key parameters which reduce the circuit
switching losses, circuit complexity and cost. These
Level count (L) 4M +1 22M+1 1 25M 1

parameters are expressed in terms of number of MASS count Vmax(p.u) 2M 4M 1 5M 1

M as listed in Table IV and in terms of level count (L) as
presented in Table V for the earlier discussed MLI
Vsv (p.u.) 14 M 6 4M 4 (
6 .5 5 M 1 )
configurations.
Source count (S) 2M
IV. COMPARISON WITH OTHER THREE PHASE TOPOLOGIES
Switch count (G) 6M + 4
The proposed MLI structure is designed keeping with the Gate drive count
5M + 4
view of maintaining optimum component count CTotal for (GD)
synthesizing L number of levels in the phase voltage. The
comparison is done with classical topologies like CHB, NPC
and FC in symmetrical configuration. The emerging modular
TABLE V
PARAMETERS OF PROPOSED THREE PHASE MLI IN TERMS OF LEVEL COUNT L

Symmetrical Asymmetrical configuration

Parameter
Configuration (P) Case 1 (P1) Case 2 (P2)

L 1 log 2 ( L+1) 1
L+1
Vmax(p.u)
2 4 2
1 log 2
5 5 1
L +1

log2 ( L+1) 1 lo g 2
Vsv (p.u.) 3.5( L 1) 6 .5 5 5 1
6 4 2
4

L 1 L +1
Source count (S) 3 3( log 2 ( L + 1) -1) 6log 5
2 2
3L + 5 L +1
Switch count (G) 3 3( 3log2 (L +1) +1) 18log5 + 12
2 2
5L + 11 5log 2 ( L + 1) + 3 L +1
Gate drive count (GD) 3 3 15log5 + 12
4 2 2
Component count 13L + 19 13log2 ( L + 1) + 3 L +1
(CTotal)
3 3 39log5 + 24
4 2 2

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TABLE VI
COMPONENTS COMPARISON OF PROPOSED MLI WITH OTHER TOPOLOGIES
R.No. S G GD D CC CTotal
L 1 L 1
[4] 3 6 ( L 1) 6 ( L 1) 27
2 2
12 log 2 ( L + 1) 12 log 2 ( L + 1) 27 log 2 ( L + 1)
[4] A1 3log 2 ( L + 1) 3
12 12 27
3 ( L 1)
[5]-[6] 1 6 ( L 1) 6 ( L 1) ( L 1) 3L2 + 4 L 6
( L 2)
( L 1)
6 ( L 1) 6 ( L 1) 3L2 + 17 L 18
[7] 1 ( 3L 4 ) 2
4
[12] 3 ( L 1) 6 ( L 1) 6 ( L 1) 15 ( L 1)
[19] 3L 5 6 ( L 1) 6 ( L 1) 15L-17
[20] A1 3log 2 ( L + 1) 3 9log 2 ( L + 1) 6log 2 ( L + 1) + 6 18log 2 ( L + 1) + 3
3L 1 3L + 1
[21] C1 3 ( L + 3) 3L + 6 9 L + 15
2 2
3L 7 3L 5
[21] C2 3 ( L + 1) 3L 9L 3
2 2
3L 5 3 ( L + 5) 3 ( L + 3) 3L 1 9 L + 21
[21] C3
4 2 2 4 2
3L 3 9L + 3 9L + 3 21L + 3
[22]
2 2 2 2
3L + 3 9 L + 33 9 L + 33 21L + 69
[22] A1
4 4 4 4
L+3 3L + 21 3L + 21 7 L + 45
[22] A2
2 2 2 2
L 1 15 L + 33
[23] 3 3 ( L + 3) 3 ( L + 3)
2 2
3L + 27 3L + 75 3L + 75 L +1 5 L + 89
[33] A1
4 4 4 4 2
A1-Asymmetrical binary configuration, A2-Asymmetrical trinary configuration, C1-Asymmetrical configuration case 1, C2-Asymmetrical
configuration case 2, C3-Asymmetrical configuration case 3.

The asymmetrical configuration CTotal characteristic curves

of other three phase topologies and proposed topology with
respect to level count L are presented in Fig. 5 (b). The
proposed MLI topology has less component count as
compared to other topologies in asymmetrical case 1 and case
2 configurations, designated as P1 and P2, respectively.

Fig. 5 Comparison of component count with level count: (a) symmetrical

configuration and (b) asymmetrical configuration.

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V. FUNDAMENTAL FREQUENCY HYBRID CONTROL

TECHNIQUE
The various control techniques have been reported in the
literature to generate switching pulses to optimize the
performance of the converters. Broadly, these are categorized
as high switching frequency and fundamental switching
frequency modulation techniques. The sinusoidal pulse width
modulation (SPWM) technique [24] is easy to realize. The
switching frequency optimal (SFO) technique [25]-[26] is
similar to SPWM with injected offset bias in the reference to
enhance the fundamental value and improve the total
harmonic distortion (THD). The other most widely used high
switching frequency technique in industry is space vector
modulation (SVM). The major advantage of SVM over
SPWM and SFO is more dc bus utilization. The SVM
realization to higher level is complex and memory
requirement is more to store the lookup table data [27]. These Fig. 6 (a) Block diagram of proposed fundamental frequency hybrid SFO-
issues are overcome by simplified SVM without lookup tables NLC control technique and (b) Signals at various stages.
[28]. The switching loss incurred is a concern in earlier high
The amplified signal at the input of round function is
frequency techniques. The following fundamental frequency
expressed in (12). The load phase voltage VA,B,C is synthesized
techniques are producing less switching losses. The selective
upon rounding the (12) with respect to V (13).
harmonic elimination (SHE) is the first fundamental switching
frequency introduced [29]. In this process the methods of
finding switching angles is a concern for higher levels with an Vn2 V
2
n=2
increase in the number of simultaneous equations and %THD = 100 = rms 1 100 (11)
V1 V1
variables. The THD is analyzed for single and three phase
inverters to optimize the performance of inverter [30]-[32]. L -1
The nearest level control (NLC) is simple and easy to realize Vr,a ,b,c = KVa,b,c where K= (12)
2
for any number of levels [33]-[34]. The fundamental SFO is
used in drives applications to acquire the high fundamental VA, B ,C = V round (Vr,a ,b,c V ) (13)
value with lower switching losses [35]-[36].
The fundamental frequency hybrid control technique is VI. SIMULATION RESULTS
presented in this paper capitalizing on the advantages of both The simulations results are performed in
SFO and NLC as depicted in Fig. 6. The reference signals for MATLAB/SIMULINK environment. The topology is
each phase Va, Vb and Vc for SFO block are expressed with a simulated by considering asymmetrical source configurations
modulation index m, variable p as (8) and offset Vo is with one basic module followed by H-bridge in each phase.
calculated as per (9). The load is considered as 3-phase star connected R-L Load
Va = mp sin(t ) with R=120 and L=120mH per phase. The results are taken

for load phase voltages, load line voltages, THD of phase and
Vb = mp sin(t 120 ) (8)
line voltages and dynamic of NLC to hybrid SFO-NLC. The
Vc = mp sin(t + 120 ) comparison between NLC and Hybrid SFO-NLC are executed
Max(Va ,Vb ,Vc ) + Min(Va ,Vb ,Vc ) to get a clear idea about the performance related to power
Vo = (9) quality improvement.
2
With asymmetric configuration, the Fig. 7 shows the
Va = Va Vo
dynamic results of 9-level load phase voltages and 17-level

Vb = Vb Vo (10) load line voltages with transition of control technique from
NLC to Hybrid SFO-NLC at time=3.98 sec. The modulation
Vc = Vc Vo
index is kept constant at m=1 with source configuration of
The optimized reference signals (10) of SFO block are Va11=50 V and Va21=150 V. The harmonic spectra of
applied as modulating signal to the NLC block. The variable p corresponding phase and line voltages for both the control
indicates the choosing constant value so as to obtain the techniques are provided in Fig. 8.
optimum value of %THD (11) in line-to-line voltages of load The Fig. 8 (a) and (b) show the harmonic spectra of load
VAB, BC, CA. phase voltage for NLC and Hybrid SFO-NLC control
techniques, respectively. The same for load line-to-line
voltage is shown in Fig. 8 (c) and (d) respectively. The line-

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Fig. 7 Simulation results in asymmetrical case 2 with NLC and hybrid

SF0-NLC techniques at m=1.0: (a) Load phase voltages and (b) Load
line-to-line voltages.

Fig. 9. The dynamics in asymmetrical case 2 configuration with hybrid

SFO-NLC technique: (a) variation of modulation index m, (b) Load phase
voltages, (c) Load line-to-line voltages and (d) Load currents.

VII. EXPERIMENTAL RESULTS

After validation of the theoretical analysis in simulation, the
Fig. 8 Harmonic spectra in asymmetrical case 2 at m=1.0 with control hardware set-up for three-phase system is developed in
technique of : (a) phase voltage with NLC, (b) phase voltage with hybrid, laboratory to realize it experimentally. The prototype set-up in
(c) line voltage with NLC and (d) line-to-line voltage with hybrid. laboratory is shown in Fig. 10 with the labeling of various
components. The component details are shown in Table VII.
The experimental results with all possible conditions are
to line voltage THD in NLC is 6.61%. The same in Hybrid
shown in Figs. 11-13 to verify the proposed analysis. The
SFO-NLC is 5.08%, which is 23.15% less as compared to
results are taken in steady state and dynamic state conditions
NLC. By comparing their fundamental voltages, SFO-NLC
to make sure the circuit operation in any condition.
technique gives 417 V which is 19.114% more than that of
NLC technique. Thus, hybrid SFO-NLC control technique is
showing better performance in three-phase system.
The Fig. 9 shows the load phase voltages, load line-to-line
voltages and load currents with variation of modulation index
m from 1 to 0.2 for asymmetrical source configuration and
Hybrid SFO-NLC control technique. For 20 millisecond of
time period from 0.96 sec to 0.98 sec and m=1, it shows the 9-
level load phase voltages and 17-level load line-to-line
voltages. From 0.98 sec to 1 sec at reduced m to 0.7, the phase
and line voltage levels are reduced to 7 and 13, respectively.
When the modulation index m is reduced to low value of 0.2,
the phase voltage is reduced to 3 levels, whereas the line
voltage is reduced to 5 levels shown in the time frame of 1 sec
to 1.02 sec for one cycle. After 1.02 sec, the voltages and
currents are restored to original values with m=1. Fig. 10 Experimental prototype set up in the laboratory.

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TABLE VII
EXPERIMENTAL SETUP
Item Specification

DC Sources 0-30V

MOSFETs IRF640N

DSP TMS32F28335

Digital Oscilloscope Tektronix DPO3054, 500MHz, 2.5GS/s

GATE Driver IC TLP250

RLoad /phase 120

LLoad /phase 120 mH

Software Code Composer Studio 6.1.0

The asymmetrical source configurations are considered with Fig. 11 Experimental results in asymmetrical case 2 with NLC and hybrid
Va11=10V and Va21=30V for phase A. The same is followed SF0-NLC techniques at m=1.0: (a) Load phase voltages and (b) Load
line-to-line voltages.
for phase B and phase C. MOSFETs IRF640N are taken as
switches in the circuit. The control algorithm is developed in
Code Compressor Studio 6.1.0 and dumped into DSP board of
TMS32F28335. The magnitude of gate signals generating
from DSP board is not sufficient to operate the switches. So,
the gate driver circuit is build with driver IC TLP250 to
provide the gate pulses required for the switches. The three
phase R-L load is connected and the results are captured in
DPO3054 with the help of differential voltage probes and
current probes.
The 9-level load phase voltages and 17-level load line-to-
line voltages in both NLC and hybrid SFO-NLC operations for
asymmetric sources at modulation index of m=1 are shown in
Fig. 11 (a) and (b), respectively. To analyze the waveforms,
the harmonic spectra are taken as shown in Fig. 12 (a) and (b)
for phase voltage in NLC control and hybrid SFO-NLC
control technique, respectively. It can be observed that the rms
voltage is increased to 34.2 V in second control technique as
Fig. 12 Harmonic spectra in asymmetrical case 2 at m=1.0.: (a), (b) Load
compared to 28.3 V in first one. But, due to the presence of phase voltage VA ,(c),(d) Load line-to-line voltage VAB , with NLC and
lower order harmonics in phase voltage of hybrid control hybrid SFO-NLC respectively.
technique, the THD is increased from 8.22% to 21.7%.
As three phase topology is concerned, focus is given to the
quality of line-to-line voltage as shown in Fig. 12 (c) and (d)
for both the control techniques. Fig. 12 (c) shows the
harmonic spectra of line-to-line voltage for NLC control
technique where the rms voltage is 47.1 V and the THD is
6.61%. Whereas, with hybrid SFO-NLC control technique, as
shown in Fig. 12 (d), the rms voltage is 56.3 V, which is
19.53% more than that of NLC technique. While comparing
the THD values, it is improved from 6.61% to 5.05% which is
23.6% less in the proposed technique.
The dynamic performance of proposed topology and control
technique is checked with the variation in m at 1.0, 0.7 and
0.2, respectively. From Fig. 13(a) and (b), it is observed that
the experimental results are generating the expected same
levels in phase and line voltages as seen in simulations, with
reduction in m. The current also varies with m as shown in
Fig. 13 (c).

2169-3536 (c) 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2017.2727551, IEEE Access
Fig. 13 The dynamics during experimental verification of proposed MLI
in asymmetrical case 2 configuration with hybrid SFO-NLC technique:
(a) Load phase voltages, (b) Load line-to-line voltages and (c) Load
currents.
VIII. CONCLUSION
A cascaded multilevel inverter topology with hybrid SFO-
NLC control technique is proposed for three phase system.
The topology is well suitable for both symmetrical and
asymmetrical source configurations. The circuit is simulated
in MATLAB/SIMULINK and then tested with experimental
set up. Both the simulation and hardware results are provided
to validate the mathematical analysis. The hybrid SFO-NLC
control technique is compared with the conventional NLC
technique. The better comparative results for this technique
are found in both simulation and hardware. The various
comparisons of proposed topology with other topologies,
provided in terms of tabular and graphical forms for both
symmetrical and asymmetrical configurations, show the better
results.
REFERENCES
[1] H. Abu-Rub, J. Holtz, J. Rodriguez and G. Baoming, Medium-Voltage
Multilevel Converters-State of the Art, Challenges, and Requirements in
Industrial Applications, IEEE Trans. Ind. Electron., vol.57, no.8, pp.
2581-2596, August 2010.
[2] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franqucelo, Bin
Wu, J. Rodrigues, M. A. Perez and J. I. Leon, Recent advances and
industrial applications of multilevel converters, IEEE Trans. Ind.
Electron., vol. 57, no. 8, pp. 2553-2580, August 2010.
[3] Alireza Nami and Firuz Zare, Multilevel Converters in Renewable
Energy Systems, INTECH Open Access Publisher, pp. 271-297, ISBN:
978-953-7619-52-7 (2009).
[4] R. H. Baker and L.H. Bannister, Electric power converter, U.S. Patent
3 867 643, Feb 1975.
2169-3536 (c) 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
[5] R. H. Baker, Switching circuit, U.S. Patent 4 210 826, Jul. 1980.
[6] A. Nabae, I. Takahashi and H. Akagi, A New Neutral-Point-Clamped
PWM Inverter, in IEEE Transactions on Industry Applications, vol. IA-
17, no. 5, pp. 518-523, Sept. 1981.
[7] T. A. Meynard and H. Foch, Multi-level conversion: high voltage
choppers and voltage-source inverters, Power Electronics Specialists
Conference, 1992. PESC '92 Record., 23rd Annual IEEE, Toledo, pp.
397-403 vol.1, 1992.
[8] A. Lesnicar and R. Marquardt, An innovative modular multilevel
converter topology suitable for a wide power range, Power Tech
Conference Proceedings, 2003 IEEE Bologna, , Vol.3, 2003.
[9] M. A. Perez, S. Bernet, J. Rodriguez, S. Kouro and R. Lizana, Circuit
Topologies, Modeling, Control Schemes, and Applications of Modular
Multilevel Converters, IEEE Trans. Power Electron., vol. 30, no. 1, pp.
4-17, Jan. 2015.
[10] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. Kumar Sahu and S. Jain,
Multilevel Inverter Topologies With Reduced Device Count: A
Review, IEEE Trans. Power Electron., vol. 31, no.1, pp.135-151, Jan.
2016.
[11] G. M. Martins, J. A. Pomilio, S. Buso and G. Spiazzi, Three-Phase
Low-Frequency Commutation Inverter for Renewable Energy Systems,
IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1522-1528, Oct. 2006.
[12] G. Waltrich and I. Barbi, Three-Phase Cascaded Multilevel Inverter
Using Power Cells With Two Inverter Legs in Series, IEEE Trans. Ind.
Electron., vol. 57, no. 8, pp. 2605-2612, August 2010.
[13] M. R. Islam, Youguang Guo and Jianguo Zhu, A High-Frequency Link
Multilevel Cascaded Medium-Voltage Converter for Direct Grid
Integration of Renewable Energy Systems, IEEE Trans. Power
Electron., vol. 29, no. 8, pp. 4167-4182, August 2014.
[14] C. I. Odeh, Enhanced three-phase multilevel inverter configuration,
IET Power Electronics, vol. 6, no. 6, pp. 1122-1131, July 2013.
[15] Charles Ikechukwu Odeh, Balancing Switching Losses in Three-phase,
Five-level Pulse-width Modulation Switched Voltage Source Inverter
Using Hybrid Modulation Techniques , Electric Power Components
and Systems, vol. 42, no. 11, pp. 11941200, Nov.2014.
[16] S. Mekhilef, M. N. Abdul Kadir and Z. Salam, Digital Control of Three
Phase Three-Stage Hybrid Multilevel Inverter, IEEE Trans. Industrial
Informatics, vol. 9, no. 2, pp. 719-727, May 2013.
[17] M. Hasan, S. Mekhilef, M. Ahmed, Three-phase hybrid multilevel
inverter with less power electronic components using space vector
modulation, IET Power Electronics, vol. 7, no. 5, pp. 1256-1265, May
2014.
[18] Kai-Ming Tsang and Wai-Lok Chan, Single DC source three-phase
multilevel inverter using reduced number of switches, IET Power
Electronics , vol. 7, no. 4, pp. 775-783, April 2014.
[19] A. Salem, E. M. Ahmed, M. Orabi and M. Ahmed, New Three-Phase
Symmetrical Multilevel Voltage Source Inverter, IEEE Journal on
Emerging and Selected Topics in Circuits and Systems, vol. 5, no. 3, pp.
430-442, Sept. 2015.
[20] K. R. Reddy, S. Sabyasachi, P. M. Meshram and V. B. Borghate, An
asymmetrical multilevel inverter topology with reduced source
count, IEEE Students' Conference on Electrical, Electronics and
Computer Science (SCEECS), pp. 1-6, Bhopal, 2016.
[21] R. Karasani, V. B. Borghate, P. M. Meshram, H. M. Suryawanshi and S.
Sabyasachi, A Three Phase Hybrid cascaded Modular Multilevel
Inverter for Renewable Energy Environment, IEEE Trans. Power
Electron., vol.32, no. 2, PP.1070-1087, Feb. 2017.
[22] Y. Hinago and H. Koizumi, A Single-Phase Multilevel Inverter Using
Switched Series/Parallel DC Voltage Sources, IEEE Trans. Ind.
Electron., vol. 57, no. 8, pp. 2643-2650, Aug. 2010.
[23] M. F. Kangarlu and E. Babaei, A Generalized Cascaded Multilevel
Inverter Using Series Connection of Submultilevel Inverters, IEEE
Trans. Power Electron., vol. 28, no. 2, pp. 625-636, Feb. 2013.
[24] M. M. Renge and H. M. Suryawanshi, Multilevel inverter to reduce
common mode voltage in AC motor drives using SPWM technique, J.
Power Electron., vol. 11, no. 1, pp. 2127, Jan. 2011.
[25] J. K. Steinke, Switching frequency optimal PWM control of a three-
level inverter, IEEE Trans. Power Electron., vol. 7, no. 3, pp. 487-496,
Jul 1992.
[26] N. Chellammal, R. Abirami, Tatipamula Mohana, Subhransu Sekar
Dash, Switching Frequency Optimal PWM Based Three Phase Hybrid
Multilevel Inverter, Procedia Engineering, vol. 64, pp 302-311, 2013.
[27] I. Ahmed and V. B. Borghate, Simplified space vector modulation
technique for seven-level cascaded H-bridge inverter, IET Power
Electronics, vol. 7, no. 3, pp. 604-613, March 2014.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2017.2727551, IEEE Access

10

[28] I. Ahmed, V. B. Borghate, A. Matsa, P. M. Meshram, H. M. Raghavendra Reddy Karasani (S15) received
Suryawanshi and M. A. Chaudhari, Simplified Space Vector his B.Tech degree in Electrical and Electronics
Modulation Techniques for Multilevel Inverters, IEEE Trans. Power Engineering from Sri Chundi Ranganayakulu
Electron., vol. 31, no. 12, pp. 8483-8499, Dec. 2016. Engineering College (SCREC), Guntur, India,
[29] G. S. Buja and G. B. Indri, Optimal Pulsewidth Modulation for Feeding in 2003; and his M.Tech in Power Control and
AC Motors, IEEE Trans. Industry Applications, vol. IA-13, no. 1, pp. Drives from the National Institute of
38-44, Jan. 1977. Technology (NIT), Rourkela, India, in 2008. He
[30] A. Ruderman, B. Reznikov and S. Thielemans, Tutorial-time averaging completed his Ph.D. work at Visvesvaraya
methods in PWM multilevel power converters analysis: Application to National Institute of Technology (VNIT),
voltage quality evaluation and flying capacitors average voltage Nagpur, India, in 2017. He worked as an
balancing dynamics, 2010 IEEE International Symposium on Industrial Assistant Professor in the Department of
Electronics, Bari, pp. 4468-4531, 2010. Electrical and Electronics Engineering, E V M
[31] A. Ruderman, B. Reznikov and S. Busquets-Monge, Asymptotic Time College of Engineering and Technology, Narasaraopet, Guntur during 2008-
Domain Evaluation of a Multilevel Multiphase PWM Converter Voltage 12 and Sir C R Reddy College of Engineering, Eluru, West Godavari, Andhra
Quality, IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1999-2009, May Pradesh, India during 2012-14. He is currently working as faculty in the
2013. department of Electrical Engineering at Sagi Ramakrishnam Raju (SRKR)
[32] A. Ruderman, About Voltage Total Harmonic Distortion for Single- Engineering College, Bhimavaram, West Godavari, Andhra Pradesh, India.
and Three-Phase Multilevel Inverters, IEEE Trans. Ind. Electron., vol. His current research interests include power electronic converters, electrical
62, no. 3, pp. 1548-1551, March 2015. drives, FACTS and renewable energy systems.
[33] R. R. Karasani, V. B. Borghate, P. M. Meshram, and H. M.
Suryawanshi, A Modified Switched-diode Topology for Cascaded Santosh Kumar Maddugari (S16) received
Multilevel Inverters, Journal of Power Electron., vol. 16, no. 5, pp. his B.Tech degree in Electrical and Electronics
1706-1715, Sept. 2016. Engineering from Vignans Institute of
[34] P.M. Meshram and V. B. Borghate, A Simplified Nearest Level Control Information Technology (VIIT),
(NLC) Voltage Balancing Method for Modular Multilevel Converter Visakhapatnam, India, in 2012; and his M.Tech
(MMC), IEEE Trans. Power Electron., vol. 30, no. 1, pp. 450-462, Jan. in Eletrical Drives from the Maulana Azad
2015. National Institute of Technology (MANIT),
[35] A. Edpuganti and A. K. Rathore, Fundamental Switching Frequency Bhopal, India, in 2014. He worked as an
Optimal Pulsewidth Modulation of Medium-Voltage Nine-Level Assistant Professor in the Department of
Inverter, IEEE Trans. Ind. Electron., vol. 62, no. 7, pp. 4096-4104, July Electrical and Electronics Engineering, Gayatri
2015. Vidya Parishad College of Engineering for
[36] A. Edpuganti and A. K. Rathore, Fundamental Switching Frequency Women, Visakhapatnam, during 2014-15. He is
Optimal Pulsewidth Modulation of Medium-Voltage Cascaded Seven- presently working towards his Ph.D. degree at Visvesvaraya National Institute
Level Inverter, IEEE Trans. Industry Applications, vol. 51, no. 4, pp. of Technology (VNIT), Nagpur, India. His current research interests include
3485-3492, July-Aug. 2015. power electronic Inverters, Fault Tolerance, electrical drives, and renewable
energy systems.
Sidharth Sabyasachi (S15) was born in
Odisha, India, in 1988. He received the
H. M. Suryawanshi (M06SM12) received
B.Tech. degree in electrical engineering
his B.E. degree in Electrical Engineering from
from the Synergy Institute of Engineering
Walchand College of Engineering, Sangli,
and Technology, BPUT, Dhenkanal, India,
India, in 1988; his M.E. degree in Electrical
in 2008, and the M.Tech. degree in power
Engineering from the Indian Institute of
control and drives from the National
Science, Bangalore, India, in 1994; and his
Institute of Technology (NIT), Rourkela,
Ph.D. degree from Nagpur University, Nagpur,
India, in 2010. He is currently working
India, in 1999. He is presently working as a
toward the Ph.D. degree at the
Professor in the Department of Electrical
Visvesvaraya National Institute of
Engineering, Visvesvaraya National Institute of
Technology, Nagpur, India. From 2010 to 2014, he was an Assistant Professor
Technology, Nagpur, India. His current research
in the Department of Electrical and Electronics Engineering, Centurion
interests are in the field of power electronics,
University of Technology and Management (CUTM), Odisha, India. He was
emphasizing developmental work in the area of
an SRF in IIT Delhi and NIT Rourkela for six months each in 2011 and 2014,
resonant converters, power factor correction,
respectively. His research interests include power electronics, multilevel
active power filters, FACTS devices, multilevel converters, high-frequency
converters, and renewable energy systems.
electronic ballasts, and electric drives. Prof. Suryawanshi is an Associate
Editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS.
Vijay B. Borghate (M12) was born in 1960. He He is a Fellow of the Indian National Academy of Engineering (FNAE),
received his B.E. (Electrical), M.Tech. IETE(I), and IE(I). He was the recipient of the Bimal Bose Award in 2009
(Integrated Power System), and Ph.D. degrees from the IETE for his leadership in power electronics in India.
from Visvesvaraya National Institute of
Technology (VNIT), Nagpur, India, in 1982,
1984, and 2007, respectively. He worked as an
Engineer for the Maharashtra State Electricity
Board, India, from 1985 to 1985. He became a
Lecturer at VNIT (then VRCE), Nagpur, India, in
1985; where he is presently working as an
Professor in the Department of Electrical
Engineering. His current research includes
resonant converters and multilevel converters.

2169-3536 (c) 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.