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Solar Energy Production - Controlling & Monitoring in the Smart Grid Using Heterogeneous Dual Core

MCU

K .Aarthi(3rd year) U .Priyanga(3rd year)


Department of Electrical and Electronics Engineering, Department of Electrical and Electronics For Women,
Vivekanandha College of Technology for Women, Vivekanandha College of Techology For Women,
Elayampalayam Elayampalayam
Email id: ajiaarthi17@gmail.com Email id: santhibuvi1506@gmail.com

installation must make sure that it operates at the


Abstract Energy from renewable sources such as
maximum
solar and
power point (MPP) of this curve. In addition the current
wind are gaining interest as the worlds power that the inverter feeds into the grid must be clean and in
demands increase and non-renewable resources phase with the grid. Several disturbances exist on the
deplete. Solar energy nodes vary in power ratings grid, like voltage swells and dips, phase jumps and
from 100-200W micro inverter, 2-3 KW multi string noise from appliances running etc, thus the system must
inverter and Mega watts Central Inverters. With be able to estimate the phase of the grid accurately along
the renewable content growing as a percentage of the with rejecting these disturbances on the grid. This is
total utility power, increased control and monitoring of typically done using a phase lock loop.
the power produced, irrespective of the power Fig 1 shows a typical PV inverter that feeds power into
ratings, is desired. Control and communication the gird. It consists of two stages, one DC-DC stage for
pose unique challenges on system designs with these boosting the voltage and tracking the MPP, and DC-AC
energy nodes. This paper discusses the design of a stage to feed current into the grid. Depending on the
smart grid-enabled renewable energy node using a installation (power rating) several different topologies
heterogeneous dual core microcontroller. Real-time have been presented.
control of extracting the energy from the renewable When connecting to the grid isolation plays a key factor
source is done on one core and the Ethernet server is in selection of power topology and system design.
run on the other core. Hardware design for the energy Isolation requirements depend on the type of PV Panel
node to extract maximum power from the solar used and the local grid codes. Isolation can be at the grid
panel is discussed along with communication connection stage Fig 2 (a), which uses low frequency
interface. Software design and integration challenges transformer. In this case both the boost and the inverter
for control and communication are presented and stages may be controlled using a single
microcontroller. However, low
the solution using dual core microcontroller frequency transformers are heavy, bulky and lossy.
illustrated. Therefore cannot be used for low power PV inverters. Fig
I. INTRODUCTION 2 (b) shows PV inverter topology with isolation at high
Depleting non renewable sources have raised interest frequency. Due to the isolation boundary such inverters
in sourcing power from renewable and cleaner power use two or more microcontrollers. Transformer less
sources. A large component of energy expended in the designs are becoming increasingly popular, as they offer
world is used by industries and houses that are connected several advantages with the reduced volume, weight and
to the electrical grid. Thus attempts are being made to also efficiency of the inverter. Fig 2 (c) depicts
raise the percentage of energy sourced from transformer less PV inverter where control of both DC-
renewable sources in the grid. Photovoltaic DC and DC-AC is done using a single controller.
(PV) energy sources are considered
quintessential factor in increasing this percentage due
to ubiquitous nature of solar power and absence of any
moving parts and hence extended life time. Also as PV
panels can be installed in a distributed way close to
where the energy is consumed for example in
residential, it eliminates
transmission losses.
Feeding power into the grid has its unique set Fig 1 PV Grid Tied Inverter
of challenges, to name a few: the PV panel is a DC source
hence a PV system needs to convert this into AC and feed
into the grid. Therefore inverter technology is
quintessential for success of PV inverters. For the
inverter to feed power into the grid it must maintain a
DC bus greater than the max instantaneous voltage of
the grid, thus a boost stage may be required. Also as PV
shows a unique V vs I characteristics the
communication medium, like Zigbee, Ethernet and power
line communication are used to gather information from
the PV installation. Ethernet is particularly a good
choice as an Ethernet server enables control of the unit
remotely (even by the utility) and the number of Ethernet
capable devices like smart phones, laptops, tablets etc is
rising.
However, combining closed loop control of all the
three power stages needed to process power from the PV
panel for a PV system shown in Fig 2 (d) along with
Ethernet stack is challenging. Typically another
controller is then added to perform the communication
tasks in the system. However, this adds additional
challenges to the system design and cost. This paper
discusses construction of a smart grid capable PV
Inverter using a heterogeneous dual core microcontroller
from Texas Instruments (TMS320F28M352HC1), where
the closed loop control of the power processing stages
is done using C28x core, which is optimized for control
tasks, and the Ethernet stack is run on a M3 ARM core.
This offers a single chip solution with a clean partitioning
of the system software for control and communication.
The paper discusses the hardware platform design along
with the control design for the PV Inverter. Challenges of
inter processor communication are discussed and software
design presented.

II. HARDWARE PLATFORM


which can take different Fig 3 gives a block
forms like LCD screen, diagram of the hardware
Fig 2 PV System web page etc. As the platform designed to
Classification based inverter installation is not implement the PV inverter.
on Isolation in a readily accessible The board is designed to
area a more convenient interface with a 50W
As energy from PV is communication medium solar panel and the power
not available throughout is needed. Different stages designed
the day, energy storage accordingly. The power
with help of battery is rating is kept low so that
added to the PV inverter new users can work with
system. Fig 2 (d) shows a the board to experiment
transformer less PV with PV systems.
inverter with battery
backup where control of all
three stages is done using a
single controller. Thus it
can be observed there is a
growing trend towards
transformer less designs,
especially for residential
PV installations. For
which a single controller
solution is of interest
given the cost sensitivity
of the application.
In addition, with the
renewable content in the
grid increasing,
requirements to control
and monitor the power
generated from these
distributed power
generation units is also
rising. The type of control
and monitoring function
desired from the installation
are currently subject to the
power ratings. For example Fig 3 Solar Explorer
high power central Platform Block
inverters communicate to Diagram
the utility such that the
power can be modulated
dependent on the grid
requirements. On the other
hand in residential
installation impetus is for
the user to be able to see
the energy production,
measure the power, and
for feed in tariffs know
the revenue the PV
installation generates.
Utility interaction for
these installation is gaining
interest with concept of
microgrids and macrogrids
come into play and the
residential distributed
generation units actively
play part in the local grid.
For the user to see
data from PV inverter a
Human Machine
Interface(HMI) is needed,
Fig 4 Details of Power Stages on the Solar Explorer Board

PV Panels have a unique V vs I characteristics, to


enable understanding and quick development of PV
systems, a low cost panel emulator is integrated on the
board. The panel emulator is based on a DC-DC stage
which is operated in voltage mode. As PV is a light
dependent source the light sensor integrated on the board
can be used to change the look up table curves for the
panel emulator. PV emulator control scheme is shown in
Fig 5.

Fig 5 PV Emulator Control Scheme


The control of the PV panel emulator is kept separate
from the control of the power processing stages of the PV Fig 6 Solar Explorer
inverter. Fig 6 shows the board with the different power Board
stages marked.
Fig 4 shows the detail of the power stages present on
A. DC-DC Boost with MPPT
the board along with sense signals. The board follows a
macro based approach and the input and output of each As shown in Fig 4 a single phase boost stage is used to
power stage is kept in form of connectors, this enables easy boost the voltage from the panel and track the MPP of
debug of each the panel.
stage. Also, the blocks can be connected in different The input I pv is sensed before the input
fashions to implement different PV systems. current capacitance
along with the panel voltage V pv . These two values are
then
III. CONTROL & COMMUNICATION DESIGN
The aim from a PV inverter installation is to used by the MPPT algorithm. The MPPT is realized using
feed maximum power it can into the grid form what is an outer voltage loop that regulates the input voltage to the
available from the panel. Fig 7 shows the control boost stage i.e. the output of the panel, by modulating
scheme used for the PV inverter. the current reference for an inner current loop of the boost
stage, see Fig
7. Increasing the current reference of the boost, i.e.
current drawn through the boost loads the panel and hence
results in the panel output voltage drop. Therefore the
sign for the outer voltage compensator reference and
feedback are reversed.
Fig 7 Control of Grid Tied PV Inverter
It is noted that the output of the boost is not Ethernet capable devices. This enables integration of
regulated. However to prevent the output voltage from this smart node into the grid of the future, where the
rising higher than rating of the components, the utility can connect and interact with large number
voltage feedback is mapped to the internal comparators of distributed resources to keep the grid working and
which can do a cycle by cycle trip of the PWM in case of stable.
over voltage.
IV. HETEROGENEOUS DUAL CORE MCU
B. DC-AC Inverter Single With the above discussion, unique challenges of
Phase control and communication in design of PV inverters for
The PV inverter feeds current into the grid. This smart grid have become clear. As the switching frequencies
is accomplished by a current loop. Reference for for the power stages being controlled rises, along with
which is calculated by multiplying the phase of the grid added functionality using a single controller (single cpu)
and the output of the DC Bus regulation loop. The for both control and communications becomes
inverter controller then modulates the duty cycle so as to complicated. Addition of Ethernet style application layers
get the desired current flow. Eq. (1) gives the relation of the adds more complexity to the system design. A typical
current fed from the inverter to the grid and the duty applied way of solving this is to use a two chip solution where
at the inverter stage [7]. one chip handles the control and the other
communication. Having a two chip solution increases
the complexity of the board and the design along with
(Vdc vgrid ).D (0 vgrid )(1 D) Vdc * D vgrid increasing the total cost.
igrid = + =
Z LCL Fsw ) Z LCL Fsw ) Z LCL Fsw ) (1)
( ( (

The phase is estimated by a phase locked loop [8] and


current reference is only changed around the zero crossing
detection of the AC mains to prevent distortion.
C.
Communication
Information that needs to be communicated to and
from the renewable node can be split into two parts,
Control and Diagnostics. Control information is for
instructing the PV installation to perform certain tasks,
such as starting and stopping production of power.
Diagnostics include the current power production figures,
panel diagnostics etc.
An Ethernet server is run on the communication core Fig 8 Heterogeneous Dual Core MCU (TMS320F28M
of the heterogeneous dual core MCU, details of
which are presented in the next section. This server
enables access to the control and diagnostics of the
energy node from various
Dual core MCU can offer an integrated single chip A. PV Inverter under varying light
solution for such applications, where one core handles conditions
the communication and other core handles the control
tasks. However, using the same core for control and
communication, leads to compromise on performance of
one or the other because control and communication have
different processor requirements. Texas Instruments
TMS320F28M35x series controller are heterogeneous dual
core MCUs which have two different CPU cores on a single
chip [4]. One of the CPU core is the Texas Instruments C28x
which is optimized for control tasks and the other CPU is an
ARM Cortex M3. Fig 8 shows the architecture of the chip. a. b.
The control peripherals such as pulse width modulators, Fig 11 PV Inverter under different luminance
time capture modules etc are mapped to the C28x. The conditions, Ch1:Grid, Ch2:DC Bus, Ch3: Current
communication peripherals such as Ethernet and USB are
mapped to the M3 core. A single analog to digital reference, Ch4:PLL
converter is shared by both the processors. Having ADC
access by both cores with different ISAs adds features of Fig 11 (a) and (b) illustrate the control of the PV
redundancy in the system, for safety critical checks. system under varying lighting conditions. It is observed
This split of control and communication tasks from Fig 11 (a) & (b) that the DC bus is maintained at a
constant value with changing light conditions, whereas the
and peripherals between the two cores provides a clean
current reference for the inverter is changed to match the
system partitioning. Communication between the two
reduced power of the panel. This illustrates the working of
processors is handled using an Inter Processor the outer DC bus voltage loop and the inner current loop as
Communication (IPC) peripheral which can configure and in Fig 7.
acknowledge interrupts on either core. Data is exchanged
between the two cores with means of shared RAMs. B. PV Inverter under varying
The shared RAMs allow read accesses from the two load
cores but only one core has privileges to write. Fig 9
Fig 12 (a) and (b) illustrate the current fed from the
shows the software structure used to pass messages and board and the grid voltage, Fig 12(a) shows the grid
commands between the two CPUs through the shared current and the inverter current to be in phase, this
RAMs. The IPC peripheral can configure interrupts for implies power from the grid and the solar explorer load is
the data to be read immediately and provide summed at the load. In Fig
acknowledgement. 12(d) the local load requirements are reduced, such that
the power from the panel is greater than what is needed
by the local load. Thus the grid current changes phase,
showing current feed into the grid from the board.

Fig 9 Software structure for message passing


V. RESULTS
a. b.
Fig 10 illustrates the setup used with the
hardware platform, with a step down transformer to step Fig 12 PV inverter under changing load; Ch1:Grid
down the grid voltage, that is used to test the PV inverter Voltage, Ch2: PLL Lock, Ch3:Grid Current, Ch4:
system. Inverter current
VI. CONCLUSION
In this paper system integration challenges for a
PV inverter for smart grid are discussed. The unique
control and communication challenges are described, with a
solution using a heterogeneous dual core MCU presented.
The design of the hardware platform for the PV inverter is
discussed and results of the grid connection under
varying light conditions and loads highlighted.
Fig 10 Grid connect setup using Solar Explorer Board
REFERENCES
[1] Soeren Baekhoej Kjaer, John K. Pedersen &
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Gird Converters for Photovoltaic and Wind Power
Systems, John Wiley and Sons,2011
[3] Tamas Kerekes, Analysis and Modeling of
Transformerless Photovoltaic Inverter Systems,
Department of Energy Technology , Aalborg
University, 2009
[4] Texas Instruments TMS320F28M35x Datasheet and Techincal
Reference Manual
[5] Zhang Housheng; Zhao Yanlei; , "Research on
a Novel Digital Photovoltaic Array Simulator,"
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[6] Britton, Lunscher, and Tanju,A 9KW High-
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[7] Soeren Baekhoej Kjaer ,Design and Control of
an Inverter for Photovoltaic Applications,
Department of Energy Technology , Aalborg
University, 2009
[8] Francisco D. Freijedo et al, Robust Phase Locked
Loops Optimized for DSP implementation in Power
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