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SN54 / 74LS75
N SUFFIX
PLASTIC
16 CASE 648-08
1 2 3 4 5 6 7 8
Q0 D0 D1 E23 VCC D2 D3 Q3 1
Q0 Q1 E01 GND NC Q2 Q3
D SUFFIX
14 13 12 11 10 9 8
SOIC
16
1 CASE 751B-03
SN54 / 74LS77
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
D0 D1 E23 VCC D2 D3 NC 1
TRUTH TABLE
(Each latch)
ORDERING INFORMATION
tn tn + 1 NOTES:
tn = bit time before enable SN54LSXXJ Ceramic
D Q negative-going transition SN74LSXXN Plastic
H H tn+1 = bit time after enable SN74LSXXD SOIC
negative-going transition
L L
LOGIC SYMBOLS
SN54/74LS75 SN54/74LS77
2 3 6 7 1 2 5 6
D0 D1 D2 D3 D0 D1 D2 D3
13 E01 12 E01 VCC = PIN 4
VCC = PIN 5
E23 E23 GND = PIN 11
4 GND = PIN 12 3
NC = PIN 7, 10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q0 Q1 Q2 Q3
16 1 15 14 10 11 9 8 14 13 9 8
VIK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
D Input 0.4
IIL Input LOW Current mA VCC = MAX, VIN = 0.4 V
E Input 1.6
IOS Short Circuit Current (Note 1) 20 100 mA VCC = MAX
ICC Power Supply Current 12 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
tPLH 12 20
Propagation Delay, Data to Q ns
tPHL 7.0 15 VCC = 5.0 V
tPLH 15 27 CL = 15 pF
Propagation Delay, Enable to Q ns
tPHL 14 25
tPLH 16 30
Propagation Delay, Enable to Q ns
tPHL 7.0 15
VIK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
D Input 0.4
IIL Input LOW Current mA VCC = MAX, VIN = 0.4 V
E Input 1.6
IOS Short Circuit Current (Note 1) 20 100 mA VCC = MAX
ICC Power Supply Current 13 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
LOGIC DIAGRAM
DATA
Q (SN54/74LS75 ONLY)
Q
ENABLE
TO OTHER LATCH
AC WAVEFORMS
D 1.3 V 1.3 V
ts th
tPHL tPLH
DEFINITION OF TERMS
SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
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