- Convension:

- _ notation
- i_ and o_ in front of inputs and outputs
- rising_edge instead of 'event and =
- Use AXI-Stream convention for communicating between modules.
- data, valid, ready
- data could be any composite type (record or array)
- Example:
i_sorted_symbols : in t_sorted_symbols
i_sorted_symbols_valid : in std_logic
i_sorted_symbols_ready : out std_logic
- Reset
- negative
- in_ and n_ as prefixes.
- Use reset only when realy needed.
- That means reset stuff which impact on valid and ready signals,
so we don't send garbage to the output.
- Use reset bridge
- External async reset is applied to async reset of two
syncrhonization flip-flops which propagate logic 1
which is further appied to async reset of the
system flip-flops.
- Async flip-flops are cheaper.
- Asynchronous assertion, synchronous deassertion
- Synchronize reset to clock domain.
- Localize reset
- Use small amount of logic on one synchronized reset.
- Small fan-out and small reset skew.

- Verification:
- Transaction level verification
- Check bit-exact data between pipe modules.
- For AXIS that means when valid && ready
- Common file format.
- CSV
- char per bit
- space as separator between fields and elements of array
- First field is always one bit last, others are real data
- Every line is new transaction.
- One file per bus between modules.
- In VHDL testbench make random de-assertions on valid and ready signals
to test robustness of AXIS handshaking protocol.

- Refactoring algorithm to SystemC model:

- Refactoring C++-typed algorithm to SystemC-typed algorithm
- Change integer types with SystemC exact bit sized types.
- It is good to keep same file names, so changes on algorithm
could be easily merged to model.
- Refactoring SystemC-typed algorithm SystemC modulated system.
- Usual text prints stay in code, but interface between modules is printed
binary as test vectors for HDL.

- Observations & Conclusions:

- AXIS channel is point of transaction. If master don't want to be blocked
by waiting slave to be ready in could save data and proceeed to
process. But if it come next time and it is still waited for slave
then it will stop. This is practicaly FIFO of depth 1 and user
shouldn't bother to implement that in SystemC, but to use AXIS FIFO.