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WEAK INVERSION IN
ANALOG AND DIGITAL CIRCUITS
Eric A.Vittoz
CSEM, Centre Suisse d'Electronique et de Microtechnique SA
Jaquet-Droz 1, CH 2007 Neuchtel, Switzerland
eric.vittoz@csem.ch
p local substrate G
n-channel VG
W,L width, length of the channel S D ID
Cox gate capacitance per unit area VS VD
UT = kT/q ( = 26 mV at 300K) B
V = local non-equilibrium voltage in channel : channel voltage
(quasi-Fermi potential of electrons)
at source end of channel: V = VS
at drain end of channel: V = VD
Qi local mobile inversion charge in channel (electrons)
VT0 gate threshold voltage for V=0.
CSEM, E. Vittoz, 2003
Weak inversion page 3
DRAIN CURRENT
VD
ID =
Qi with = Cox W (=mobility)
Given by: - dV
C ox L
VS
- Qi /Cox
VG-VT0 V G const.
strong inversion, slope factor n =1.2 to 1.6
slo
-Qi VP -V
exponential
pe
V
0 VS VD
VG - VT0
Pinch-off voltage VP
n
Weak inversion already possible for VS=0 if VG<VT0 ("subthreshold")
CSEM, E. Vittoz, 2003
Weak inversion page 4
VG-VT0>0
slope
slope
-n
ID/ ID/
-n
0 V 0
VS VD VD V
VP<0 VS
VP>0 VG-VT0<0
=
ID IF
IR
V V V
VS VD VS VD
VP-V VP -VS,D
-Qi/Cox = 2nUT e UT 2nUT thus: IF,R = IS e UT
2
Definition: specific current of the transistor: IS = 2nUT
VG-VT0 V V
- S - D
ID = IS e nUT (e UT - e UT ) for IF and IR IS
IF IR
VG VS VD VT0
- -
ID = ID0 e nUT ( e T - e UT
U ) where ID0=IS e- nUT
1
VD-VS pe VG
e
VS
slo
op
UT U T -
sl
0 UT
0 1 2 3 4 5 6
VD-VS VG VS
ID ~ 1-e - U ID ~ e nUT -
T
ID~ e UT
IF,R VP -VS,D
b. Interpolation formula: = ln2 (1 + e ) [9]
IS 2U T
IF,R VP -VS,D
IS = e U T for VP -VS,D UT (weak inversion)
IF,R VP -VS,D 2 for VP -VS,D UT (strong inversion)
IS = 2UT
Only 3 parameters: VT0, n (inside VP) and IS (or ) to model the current
from weak to strong inversion.
CSEM, E. Vittoz, 2003
Weak inversion page 9
IF,R b with:
IS 102 strong
a VP =(VG-VT0)/n
current
1
ID = IF - IR
weak
10-2
10-4 VP -VS,D
-20 0 20 40 60 UT
voltage
Definition: Inversion coefficient: IC = the larger of IF/IS and IR/IS
weak inversion: IC 1
moderate inversion: IC 1
VDSsat 2
strong inversion: IC = 2U 1
T
VDSsat 2
decreased by k2
2U
IC =
T
- digital circuits: VB decreased by k, thus
VB -VT0 2 2
ICon = decreased by k
2nUT
Weak inversion approached for constant temperature T.
VDSsat
Transition frequency: fT = 2 increased by k
2L
- weak inversion with L=100nm : fT >4 GHz
CSEM, E. Vittoz, 2003
Weak inversion page 13
for P = M = 8 : VDS1=5UT,
V+ I2 mirror T1-T2
T3
K
slope
T6 T4T3
I2 P(stable)
source I1
4
3 -T
T
sink T2KT1
or
irr
T5
m
T1 R VR I1
Q (unstable)
V-
yields: 2
I = 2n8UT.Aln2K = IS8.Aln2K
In weak inversion:
linearity of currents even for different gate voltages
VGi
with Gi = 1/Ri ~ ISi exp
nUT
ground 0 IN I
0* 0*
GN GN GN* GN*
I Ik
IN Ik
Gk 0*
Gk G Gk* Gk*
I1 I1
0*
G1 G1 G1* G1*
V- V-
resistive prototype pseudo-resistive version
(0*=pseudo-ground)
1
Series combination of Gi : G =
1/Gi harmonic mean
1 Ihm
Same voltage across G and Gi, thus I = =
1/Ii N
Can be used as a fuzzy AND gate.
CSEM, E. Vittoz, 2003
Weak inversion page 18
TRANSLINEAR CIRCUITS
With bipolar transistors: With MOS transistors in weak inversion: [16,17]
Ii [15]
+ (VGi - VSi) = (VGi - VSi) VGi
+ +
VBEi VSi
+ Ii -1
with: Ii
+ VGi Ii
+ common substrate
n -VSi = UT ln ID0i
+ and - directions of BEi If + and - are alternated then: pairs of equal
(any sequence) VGi both sides of equation:
VBEi = VBEi VGi VGi /n for each pair,
+ and then
Ii
with: VBEi= UT ln I
si
Otherwise: separate wells connected to
Ii Isi sources to impose VSi = 0
+ + =
=
Ii Isi Precision degraded by VT0 mismatch
CSEM, E. Vittoz, 2003
Weak inversion page 19
Vi Vo
C
le
n=1.6
ab
6
st
vH (high) V-
4 ble
sta
ta
vB me
swing
2
bistable for VB > 1.91UT
stable vL (low) 95% swing for VB = 4UT
0 2 4 6 8
normalized supply voltage vB
Since VL=VB-VH >0, static current Istat at each state is larger than I0
1.2
0.9
0.8
1 2 4 6 8
normalized supply voltage vB
0 vL
0 1 2 3
normalized time t /T0
Characteristic time : T0=CUT/I0
Transitions become standard after a few stages
Normalized delay time Td/T0 only depends on VB and n.
CSEM, E. Vittoz, 2003
Weak inversion page 23
Td n = 1.6
T0 Approximation:
0.1 CVB CVB
Td
Ion I0eVB/nUT
CVB -V /nU
or I0 e B T
0.01 Td
3 4 5 6 7 8 9 10 11 (for calcul. of Pstat)
normalized supply voltage vB
10-2 n = 1.6
Qsc
QC
0
3 4 5 6 7 8 9 10
normalized supply voltage vB
0.2
8 n =1.6
0.1
normalized
6
4 0.05
2 0.03
0.01
0 0.003
2 4 6 8 10 12
normalized supply voltage vB
Pdyn dominates for large min. VB for min. PTd
Pstat dominates for small increase VB to increase Ion/Ioff
CSEM, E. Vittoz, 2003
Weak inversion page 26
POWER/FREQUENCY RATIO
-v /n
By re-using =2f Td : P/f = C(nUT)2 (vB/n)2(1+
2
e B )
10-3
100 10-2
e-3 parameter
10-4
10 1 Pstat
10-3
Pdyn e-3 10-2
1
1
4 6 8 2 10 12 14
normalized supply/slope factor vB/n
VBopt and Pmin increase for decreasing
At Pmin : PdynPstat
Increasing I0 does not allow to reduce VB significantly for Td const.
For > 5%, power reduction by >20 compared to Pdyn at 1V.
CSEM, E. Vittoz, 2003
Weak inversion page 27
MAXIMUM SPEED
CVB
Since Td and Ionmax ICon IS (inv. coeff* spec. current), thus:
Ion
VB C
Tdmin
ICon IS
Tdmin(weak) VB C
IS
VGS swing
to obtain Ion/Ioff Ion/Ioff
20 10
from continuous current model:
0
10-1 1 101 102 103
"on" inv. coeff. ICon
Degeneration of logic states:
4 vH vB=4
3 n=1.6
reduction of logic swing logic
large increase of static current Istat 2 swing
loss of bistability vL
1 Istat
more supply voltage needed. IS
0
0 1 2 3 4 ICon
CSEM, E. Vittoz, 2003
Weak inversion page 29
NUMERICAL RESULTS
Simple inverter replaced by 3-input NAND-gate:
approx. equivalent to inverter with
L = 3-time that of n-ch transistor
C VB
C = 6-time that of min. inverter
(includes Cinterconnect=C/2).
parameter process A process B unit
min. channel length Lmin 500 180 nm
equiv. spec. current IS 200 400 nA
equiv. load capac. C 20 4 fF
specific energy C(nUT)2 28 4.2 aJ
P/f for =1 VB=4UT 228 44 aJ
(P/f)min for =0.01 and VBopt=6nUT 1.46 0.22 fJ
Pdyn/f at VB=1V 20 4 fJ
fmax1 for =1 and VB=4UT 50 500 MHz
fmax2 for =0.01 and VB=VBopt 0.22 2.56 MHz
Pmin at fmax2 32.5 56.3 nW
CSEM, E. Vittoz, 2003
Weak inversion page 30
CONCLUSION
Low speed, but keeps increasing with 1/L2 in scaled down processes.
REFERENCES
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CSEM, E. Vittoz, 2003