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ZZZ
PCB
MB
DA80000TI10
ZZZ1
1 1
DDR
Samsung
X76-S@
X76418BOL01
ZZZ1
DDR
Hynix
X76-H@
Compal Confidential
X76418BOL02
S1
Frame
2 2
Nvdia(T30L) + DDRIIIL
V0JET (A210)_ LA8981P
2012-06-11 REV: 1.0
3
The content in this document contains confidential information of Compal Electronics, Inc. 3
that is protected under all applicable trade secrets laws and regulations.
If you are not the intended recipient or otherwise authorized to receive such information,
please do not copy, distribute or otherwise use the information contained herein and please
destroy this communication accordingly.
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 1 of 35
A B C D E
A B C D E
Compal Confidential
Model Name : NVIDIA T30L System Block Diagram
12MHz
32KHz
1
DDR3L 1
1GB
PMU CORE_PWR_REQ
TPS6591104
Power ON CPU_PWR_REQ JTAG Debug
Test Point
VIN SYS_RESET_N
PWR_I2C
PMU_32K_IN
PWR_I2S
Nvidia
T30L MIC & HP Jack Audio AMP Speaker x 2
Touch Panel GEN2_I2C APA2010 (1W)
Control
SDMMC4 SDMMC1
(1.8V) (3.3V) GYRO Sensor IME G-Sensor
MPU-3050 KXTF9-4100
eMMC HS uSD slot
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SYSTEM BLOCK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 2 of 35
A B C D E
5 4 3 2 1
V0JET (A210)
Voltage Rails
V0JET EVT DVT PVT MP
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 3 of 35
5 4 3 2 1
5 4 3 2 1
+VDD_3V3_GMI_TEGRA
+VDD_3V3_GMI_TEGRA
R453 L49 27NH_LQG15HS27NJ02D_5%_0402
NV_LCD_PCLK 2 1 LCD_PCLK_R 1 2
LCD_PCLK (15)
47_0402_5% 1 1 U1D NAND_D0 R1 2 1 100K_0402_5%
C165 C164
4/22 GMI BOOT_PD R2 2 1 100K_0402_5%
12P_0402_50V4Z 12P_0402_50V4Z (1.8/3.3V)
2 2 +3VS 110mA C1 F8 Z NAND_D0
VDDIO_GMI_1 GMI_AD00 Z NAND[D0:D3] -- boot strap EMMC 0001
RF C2
VDDIO_GMI_2 GMI_AD01
G6 BOOT_PD
NAND[D4:D7] -- ram code
Change BOM structure to DDR3L
Z
3300P_0402_50V7K
D1 D3
VDDIO_GMI_3 GMI_AD02 Z For Boost Strap
2 1 2 GMI_AD03
E4 K4B2G0846D-HYH9 [7..4] -->0000
Z H5TC2G83CFR-H9A [7..4] -->0001 +VDD_3V3_GMI_TEGRA
4.7U_0402_6.3V6M
0.1U_0402_10V7K
G2 NAND_D4
+VDD_3V3_LCD_TEGRA U1I GMI_AD04 Z
C3
C147 C4 D2 NAND_D5
GMI_AD05 B3 Z NAND_D6 X76@
8/22 LCD
1 2 1 GMI_AD06 G1 Z NAND_D7 NAND_D4 R38 2 1 100K_0402_5%
GMI_AD07 H6 PD
+3VS 20mA PD GMI_AD08 PD LCD_PWM_OUT (15)
AB13 AG11 NV_LCD_PCLK F4 NAND_D5 R43 2 X76@ 1 100K_0402_5%
VDDIO_LCD_1 LCD_PCLK GMI_AD09 PD DISPOFF# (15)
AC13 E7
0.1U_0402_10V7K
1
AC12 PD D6
LCD_D13 PD LCD_D13 (15) GMI_CS4* PU
AD12 J5 @ R18
LCD_D14 PD LCD_D14 (15) GMI_CS6* TEMP_ALERT# (7)
AE18 J7 100K_0402_5% PCB_ID0 R63 2 1 100K_0402_5%
LCD_D15 PD LCD_D15 (15) GMI_CS7*
AF13 A210@
LCD_D16 PD LCD_D16 (15)
AH15 PCB_ID1 R87 2 1 100K_0402_5%
LCD_D17 (15)
2
LCD_D17 AE9 PD E6 1 BOOT_PD NH660@
LCD_D18 AE10 PD GMI_ADV* PCB_ID2 R100 2 1 100K_0402_5%
LCD_D19 AH13 PD A4 0 A210@
LCD_D20 AH9 PD GMI_CLK 100K_0402_5% BOARD_ID0 R78 2 1 100K_0402_5%
LCD_D21 PD
LCD_D22
AE13
GMI_RST*
D4 2 1 R24 +VDD_3V3_GMI_TEGRA V10 M
AK13 PD B4 TS_PWR_EN BOARD_ID1 R88 2 1 100K_0402_5%
LCD_D23 GMI_WAIT D5 0_0402_5%
GMI_WP* R403 R12
1
C3 1 2 PCB_ID0 R152 2 1 100K_0402_5%
PD GMI_IORDY SD_DET# (21,7) +VDD_3V3_GMI_TEGRA
100K_0402_5%
AG12 A211@
LCD_M1 F2 1 FORCE_RECOVERY# PCB_ID1 R153 2 1 100K_0402_5%
GMI_OE* G4 1 NOR_BOOT R22 2 1 100K_0402_5% A211@
AJ9 PD GMI_WR* PCB_ID2 R154 2 1 100K_0402_5%
2
LCD_PWR0 AG10 PD R14 1 2 100K_0402_5% +VDD_3V3_GMI_TEGRA A211@
LCD_PWR1 AH12 PD G3 Z BOARD_ID0 R79 2 1 100K_0402_5%
C C
LCD_PWR2 LVDS_SHTDN# (15) GMI_DQS +VDD_3V3_GMI_TEGRA TS_RST# (15)
@
AG15 PU BOARD_ID1 R89 2 1 100K_0402_5%
LCD_SCK AJ15 PU @
LCD_CS0* PU
LCD_CS1*
AC10 EN_WIFI_VDD V10 M
1
AJ13 PU
LCD_SDOUT PU
100K_0402_5%
AH10 R11 R10
LCD_SDIN
1
2.2K_0402_1% 2.2K_0402_1% R17 DVT BOARD_ID[1..0] -->0..1
AE15 PD
EN_3V3_EMMC1 (14)
2
LCD_DC0 PD Z
LCD_DC1
AE12
EN_3V3_SDCARD (21) GEN2_I2C_SCL
G5
GEN2_I2C_SCL (15) DVT PCB_ID[3..00] --> 1111
G7 Z
2
GEN2_I2C_SDA GEN2_I2C_SDA (15)
AD13 PU
CRT_HSYNC AJ16 PU
CRT_VSYNC
AG14 Z
DDC_SCL AJ10 Z
DDC_SDA +VDD_3V3_GMI_TEGRA
T30L-P-A3-1.2G_FCBGA728
AG13 Z
HDMI_INT
1
R23
47K_0402_1%
+VDD_1V8_SYS_TEGRA
2
T30L-P-A3-1.2G_FCBGA728 9/29 Leakage Issue
R90 47K_0402_1%
Modify R10&R11 from mount to unmount 1 2 FORCE_RECOVERY#
5
U55
D
1
1
G Vcc
(22,7) VOL_UP# B 4 2 Q44
Y
1
U1K 2 G S TR DMN3150LW-7 1N SOT-323-3
(22,7) VOL_DOWN# A R54 S
3
10/22 HDMI 1M_0402_1% Vth=1.4V
3
74AUP1G02GW_TSSOP5
B B
AE4 AK3
2
AF4 AVDD_HDMI_1 HDMI_TXCN AK4
AVDD_HDMI_2 HDMI_TXCP
(3.3V)
1
AJ4
@R420 HDMI_TXD0N AH4
HDMI_TXD0P
0_0402_5%
AH6
HDMI_TXD1N AJ6
2
HDMI_TXD1P
AK7
HDMI_TXD2N AJ7
HDMI_TXD2P +VDD_1V8_SDMMC4_TEGRA
AF7
AVDD_HDMI_PLL
U1E SDMMC4 : eMMC
(1.8V) AG1
HDMI_PROBE
1
5/22 SDMMC4
@R425 (1.2/1.8V)
0_0402_5% AH3 HDMI_RSET VDD_1V8_GEN 20mA D8 B9 Z
HDMI_RSET VDDIO_SDMMC4 SDMMC4_DAT0 B6 Z EMMC_DA0 (14)
SDMMC4_DAT1 C6 Z EMMC_DA1 (14)
2
0.1U_0402_10V7K
A6
@ R26 SDMMC4_DAT3 B7 Z EMMC_DA3 (14)
1 2 SDMMC4_DAT4 EMMC_DA4 (14)
T30L-P-A3-1.2G_FCBGA728 1K_0402_1% A7 Z
C5 C6 SDMMC4_DAT5 D7 Z EMMC_DA5 (14)
SDMMC4_DAT6 D9 Z EMMC_DA6 (14)
4.7U_0402_6.3V6M
2
A9 PU
SDMMC4_CLK C7 PU EMMC_CLK (14)
SDMMC4_CMD EMMC_CMD (14)
+VDD_1V8_SYS_TEGRA U1J
C9 Z
SDMMC4_RST* EMMC_RST# (14)
PN:SA00004KS00
0.1U_0402_10V6K
9/22 VDAC
2
2k bit C115
AK6
AVDD_VDAC VDAC_R
AB7
AA9
(2.8V)
U54 VDAC_G AA7
1 VDAC_B
A 1 8 A
2 A0 VCC 7
A1 WP BOARD_ID_WP (7)
3 6
4 A2 SCL 5 PWR_I2C_SCL (16,17,29,31,33,7)
GND SDA PWR_I2C_SDA (16,17,29,31,33,7) AA5
VDAC_VREF
need check with WC of GPIO
AT24C02C-XHM-T_TSSOP8 AA6 T30L-P-A3-1.2G_FCBGA728
VDAC_RSET
need check with SW Roger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
T30L-LCD/CRT/HDMI/NAND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 4 of 35
5 4 3 2 1
5 4 3 2 1
+VDD_1V35_MEM_TEGRA
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
+VDD_1V35_MEM_TEGRA U1C
1 1 1 1 50OHM_NETCLASS2
3/22 DDR3/LPDDR2 DDR_DQ[31..0] (11,12)
D D
C10
C11
C12
C13
740mA G16 (1.2/1.25/1.35/1.5)
D24 DDR_DQ0 0
2 2 2 2 G19 VDDIO_DDR_01 DDR_DQ00 B25 DDR_DQ1 1
H15 VDDIO_DDR_02 DDR_DQ01 A25 DDR_DQ2 2
VDDIO_DDR_03 DDR_DQ02
SDMMC1 : SD card VDD_1V35_DDR3_MEM H16
VDDIO_DDR_04 DDR_DQ03
D21 DDR_DQ3 3
H18 A24 DDR_DQ4 4
H19 VDDIO_DDR_05 DDR_DQ04 A21 DDR_DQ5 5
H21 VDDIO_DDR_06 DDR_DQ05 A22 DDR_DQ6 6
+VDD_3V3_SDMMC1_TEGRA U1P H22 VDDIO_DDR_07 DDR_DQ06 B22 DDR_DQ7 7
J15 VDDIO_DDR_08 DDR_DQ07 C15 DDR_DQ8 8
17/22 SDMMC1
J16 VDDIO_DDR_09 DDR_DQ08 A13 DDR_DQ9 9
VDD_PMU_LDO5 20mA (1.8/2.8 ~ 3.3V) PU VDDIO_DDR_10 DDR_DQ09
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
J1 K1 J18 C12 DDR_DQ10 10
VDDIO_SDMMC1 SDMMC1_DAT0 K3 PU SDMMC_DAT0 (21) J19 VDDIO_DDR_11 DDR_DQ10 B13 DDR_DQ11
SDMMC1_DAT1 SDMMC_DAT1 (21) 1 1 1 VDDIO_DDR_12 DDR_DQ11
11
PU
C14
C22
C15
C17 1 K2 J21 C13 DDR_DQ12 12
SDMMC1_DAT2 PU SDMMC_DAT2 (21) VDDIO_DDR_13 DDR_DQ12
4.7U_0402_6.3V6M
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
33.2_0402_1% F22 DDR_DQ23 23
+3VS 50mA DDR_DQ23
C18
C19
C20
C21
(2.8/3.3V)
L4 SDMMC1_COMP_PUR29 1 2 1 1 1 1 A27 F13 DDR_DQ24 24
SDMMC1_COMP_PU VDD_DDR_RX DDR_DQ24 G13 DDR_DQ25 25
DDR_DQ25
4.7U_0402_6.3V6M
K6 SDMMC1_COMP_PDR30 1 2 G10 DDR_DQ26 26
SDMMC1_COMP_PD 33.2_0402_1% DDR_DQ26 D13 DDR_DQ27 27
2 2 2 2 1 DDR_DQ27 G9 DDR_DQ28 28
DDR_DQ28
C23
F10 DDR_DQ29 29
DDR_DQ29 D10 DDR_DQ30 30
M5 Z 2 DDR_DQ30 F12 DDR_DQ31 31
GPIO_PV2 M1 Z DDR_DQ31
GPIO_PV3
K5 PD C22 50OHM_NETCLASS2
CLK2_OUT Z CP_GPIO (27) +VDD_1V0_DDR_HS_TEGRA DDR_DM0 DDR_DM0 (11)
N5 D12 50OHM_NETCLASS2
CLK2_REQ DDR_DM1 DDR_DM1 (12)
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
C E22 50OHM_NETCLASS2 C
DDR_DM2 DDR_DM2 (11)
C30
C111
C109
C110
1 1 1 1 G12 50OHM_NETCLASS2
VDD_PMU_LDO8 30mA (1.00V) DDR_DM3 DDR_DM3 (12)
T30L-P-A3-1.2G_FCBGA728 E10
H9 VDD_DDR_HS_1
VDD_DDR_HS_2 B24 DDR_DQS0_PAIR
2 2 2 2 DDR_DQS0N DDR_DQS0_PAIR DDR_DQS0N (11)
C24
DDR_DQS0P DDR_DQS0P (11)
4.7U_0402_6.3V6M
B12 DDR_DQS1_PAIR
1 DDR_DQS1N DDR_DQS1N (12)
A12 DDR_DQS1_PAIR
DDR_DQS1P DDR_DQS1P (12)
C24
E24 DDR_DQS2_PAIR
2 DDR_DQS2N DDR_DQS2_PAIR DDR_DQS2N (11)
D23
DDR_DQS2P DDR_DQS2P (11)
0.1U_0402_10V7K
+VDD_1V35_MEM_TEGRA
1 Note:Place at the T-point
C482
A V8 A
IC_USB_REXT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
T30SL-OSC/PLL/SYS/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 5 of 35
5 4 3 2 1
A B C D E
U1L
11/22 USB
+AVDD_3V3_USB_TEGRA
W5 +T30S_USB1
USB1_VBUS
(3.3V)
130mA U12
+3VS AVDD_USB
U1Q is not place on grid , need check connection USB1_DN
W3
W2 USB1_DN (21)
For CLIENT USB
USB1_DP USB1_DP (21)
1 1 1
4.7U_0402_6.3V6M
C27
+VDD_1V8_AUDIO_TEGRA T7 1
R1422 @ 2 1K_0402_5%
ACC1_DETECT USB1_ID (21)
U1Q 2
13/22 AUDIO
RF note
20mA C30 C27 AUDIO_CLK R37 1 2 0_0402_5% Option
VDD_1V8_GEN VDDIO_AUDIO CLK1_OUT AUDIO_CLK_R (17)
F26
(1.8/3.3V) CLK1_REQ VDD_1V8_GEN
0.1U_0402_10V7K
+AVDD_1V8_USB_PLL_TEGRA
1
PD
C28
G29
DAP1_SCLK D28 PD AUDIO_SEL (16) 1 2
DAP1_FS PD AUDIO_RST# (16)
G26 @ R399 0_0402_5%
2 DAP1_DOUT ES305_INT_R (16)
G25
DAP1_DIN L4
(1.8V)
4 3 1 2 10mA U4
AVDD_USB_PLL
PD
0.1U_0402_10V7K
C28 2 MPZ1005S300CT_2P
DAP2_SCLK C29 PD AUDIO_SCLK2 (16) 5
DAP2_FS AUDIO_FS2 (16) 1
1
PD
C29
G27 V5
DAP2_DOUT F27 PD AUDIO_DOUT2 (16) R323 6 USB2_VBUS
DAP2_DIN AUDIO_DIN2 (16)
1M_0402_1% 1
2 T6
FDG6331L_SC70-6 USB2_DN T5
2
PU USB2_DP
SPDIF_IN
H27
PU
SB00000SM00 Q34
A28
SPDIF_OUT W4
CORE_PWR_REQ ACC2_DETECT
(31,7) CORE_PWR_REQ
B28 PU
SPI1_SCK J24 PU
SPI1_CS0* F29 PU BATT_LEARN (27)
SPI1_MOSI F28 PD
SPI1_MISO COMPASS_DRDY (19)
2 2
D29 PU
SPI2_SCK G28 PU
SPI2_CS0* F25 PU
SPI2_CS1* HP_DET# (17) Vth = 1.5
E27 PU
SPI2_CS2* PD CDC_IRQ# (17)
B27
SPI2_MOSI D30 PD EN_ES305_OSC (16)
SPI2_MISO GYRO_INT_R (19)
SC400003Z00 R1432 1 @ 2 0_0402_5% USB3_VBUS
R5 R1423 1 @ 2 0_0402_5% +T30S_USB1
T30L-P-A3-1.2G_FCBGA728 +USB_CLIENT V3
+T30S_USB1 Q18 USB3_DN USB_HOST_DN (21)
AO3413_SOT23-3 USB3_DP
V2
USB_HOST_DP (21) For HOST USB
10MIL 0.1A 1 3 V4
S
ACC3_DETECT
0.1U_0402_10V6K
1
1
1
C2673 D18 @
G
R39
2
R42
1M_0402_1% 2 BZT52-B5V6S_SOD323-2
Y4 USB_REXT 2 1
USB_REXT
2
2
EN_T30S_USB1 1K_0402_1%
T30L-P-A3-1.2G_FCBGA728
+AVDD_3V3_USB_TEGRA
1
+AVDD_1V2_DSI_CSI_TEGRA U1H 2 Q5
G BSS138W-7-F_SOT323-3
7/22 DSI & CSI
S
3
(1.2V)
VDD_PMU_LDO6 56mA AB6 AC4
AVDD_DSI_CSI CSI_CLKAN AD4 +VDD_1V8_CAM_TEGRA
CSI_CLKAP
C32
0.1U_0402_10V7K
CAM_I2C_SCL CAM_I2C_SDA
C31
4.7U_0402_6.3V6M
1 1 AD3
CSI_D1AN AD2
CSI_D1AP 1 1
CSI_D2AN
AE2 USB VBUS overvoltage protection C186
@
C187
@
1
3 2 2 AE3 3
2
(1.8/2.8 ~ 3.3V)
VDD_1V8_GEN 20mA Z
AD9
VDDIO_CAM CAM_I2C_SCL
AG5
AH7 Z CAM_I2C_SCL (20) RF note
CAM_I2C_SDA CAM_I2C_SDA (20)
Z R72
0.1U_0402_10V7K
AG3 AD5 1 2 0_0402_5%
CSI_CLKBN 2M_CAM_CLK#_R (20) CAM_MCLK CAM_MCLK (20)
AG2 1 1 1
CSI_CLKBP 2M_CAM_CLK_R (20)
C35
4.7U_0402_6.3V6M
C372
Z
C34
AD1 AF6
CSI_D1BN 2M_CAM_DA1#_R (20) GPIO_PBB0 Z 2M_CAM_RST# (20)
10P_0402_25V8K
AE1 AD6
CSI_D1BP 2M_CAM_DA1_R (20) 2 2 GPIO_PBB3 AG7 Z 2
AH2 GPIO_PBB4 AE5 Z
CSI_D2BN GPIO_PBB5 Z 2M_CAM_PWDN (20)
AH1 AE6
CSI_D2BP GPIO_PBB6 AE7 Z
GPIO_PBB7 2M_CAM_RST# 2M_CAM_PWDN
2
AC6 PU
GPIO_PCC1
2
2
AG6 PU @ R25 R27 @
GPIO_PCC2 @ R16 R15 @ 100K_0402_5%
100K_0402_5% 100K_0402_5%
100K_0402_5%
1
T30L-P-A3-1.2G_FCBGA728
1
1
AA1
V10 Add
DSI_CLKAN +VDD_1V8_CAM_TEGRA
AB1
DSI_CLKAP +AVDD_1V2_DSI_CSI_TEGRA
AB2
DSI_D1AN AB3
DSI_D1AP
1
AA2
DSI_D2AN AA3 R44
DSI_D2AP 453_0402_1%
4 4
2
AG4 DSI_CSI_RUP
DSI_CSI_RUP
AJ3 DSI_CSI_RDN
DSI_CSI_RDN
1
AB4 R45
DSI_CSI_TEST_OUT
1
49.9_0402_1%
R1424
49.9_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 6 of 35
A B C D E
A B C D E
+VDD_1V8_SYS_TEGRA
+VDD_1V8_SENSOR
BT_RST# GPS_RESET# For PMU RTC CLOCK
Y1 4.7P_0402_50V8J
1 2 T30_XTAL_IN C36 1 2
(31) PMU_OSC32KIN PMU_OSC32KOUT (31)
1
@
R56 R75 R48 R49
32.768KHZ_12.5P_1TJF125DP1A000D
2
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
+VDD_1V8_UART_TEGRA R46 R47 Y10
2
R50 12MHZ_7PF_FL1200105
U1R 2.2K_0402_1% 2.2K_0402_1% CORE_PWR_REQ 2M_0402_5%
Open Drain CPU_PWR_REQ
1
14/22 UART
3
2
20mA
10K_0402_5%
4.7P_0402_50V8J
AA30 (1.8/3.3V)
AB25 Z T30_XTAL_OUT C37 1 2
1 VDD_1V8_GEN VDDIO_UART GEN1_I2C_SCL Z GEN1_I2C_SCL (19) 1
R1572
V29
GEN1_I2C_SDA GEN1_I2C_SDA (19)
0.1U_0402_10V6K
1 W25 PU
GPS_UART_TXD (24)
1
UART2_TXD PU
C38
AB28
UART2_RXD PU GPS_UART_RXD (24)
UART2_RTS*
AB26
PU GPS_UART_RTS# (24) For GPS AVDD_OSC
AA25
2 UART2_CTS* GPS_UART_CTS# (24)
U1B
AC27 PU VDD_1V8_GEN
UART3_TXD PU BT_UART_TXD (25) 2/22 OSC, PLL & SYS
W27 MPZ1005S300CT_2P
UART3_RXD PU BT_UART_RXD (25) L3
UART3_RTS*
AB29
PU BT_UART_RTS# (25) For BT
W29 1 2 AVDD_OSC10mA F30 (1.8V)
T30 T30_XTAL_IN
UART3_CTS* BT_UART_CTS# (25) AVDD_OSC XTAL_IN
AA28 Z
GPIO_PU0 Z BT_RST# (25)
V30 1
GPIO_PU1 Z
4.7U_0402_6.3V6M
AB30
GPIO_PU2 Z GPS_PWRON (24)
Deep Sleep : OFF
C39
AB27
GPIO_PU3 Z GPS_RESET# (24)
AC25 T29 T30_XTAL_OUT
GPIO_PU4 W30 Z DEBUG_UART1_RX_R 1@ R149 2 2 XTAL_OUT
GPIO_PU5 Z DEBUG_UART1_RX (18,7)
AA27 BT_PD# 0_0402_5%
GPIO_PU6 BT_PD# (25)
R372 2 1100K_0402_5%
AA29 PD
DAP4_DIN PD BT_PCM_IN (25)
W28
DAP4_DOUT PD BT_PCM_OUT (25) +AVDD_1V1_PLL_TEGRA
AA24
DAP4_FS PD BT_PCM_SYNC (25)
AA26
DAP4_SCLK BT_PCM_CLK (25)
54mA H13 (1.1V)
H12 PLL_S_PLL_LF
VDD_PMU_LDO7 AVDD_PLLA_P_C NC
0.1U_0402_10V6K
0
0.1U_0402_10V6K
Y27 1
CLK3_OUT Z CLK_12M_ES305 (16) (1.1V)
C42
W24 J12 1
CLK3_REQ AVDD_PLLX
C40
0.1U_0402_10V6K
2 J13 (1.1V)
AVDD_PLLM @ 2
T30L-P-A3-1.2G_FCBGA728
AA8 (1.1V) +VDD_1V8_SYS_TEGRA
AVDD_PLLU_D
2 1 2
(1.1V)
C41
AD7
AVDD_PLLU_D2
1
(1.05V)
2 AA22 1.8K_0402_5%
AVDD_PLLE 1.8K_0402_5%
2
R51 R52
R53
2
0_0402_5% M24 Z
+VDD_1V8_BB_TEGRA PWR_I2C_SCL N27 Z PWR_I2C_SCL (16,17,29,31,33,4,7)
1
PWR_I2C_SDA PWR_I2C_SDA (16,17,29,31,33,4,7)
U1S N28
SYS_RESET_N PMU_RESET_OUT_1V8# (31)
12/22 BB
VDD_1V8_GEN 20mA W1 R3 PU
VDDIO_BB ULPI_DATA0 DEBUG_UART1_TX (18)
V1 PU M22
ULPI_DATA1 DEBUG_UART1_RX (18,7) PWR_INT_N PMU_INT# (31)
(1.8/3.3V)
N1 PU +VDD_1V8_SYS_TEGRA
0.1U_0402_10V6K
ULPI_DATA2 T3 PU N25
1 ULPI_DATA3 WAKE_UP_ACIN (27) CORE_PWR_REQ CORE_PWR_REQ (31,6)
P4 PU
C43
R24
ULPI_DATA4 CPU_PWR_REQ CPU_PWR_REQ (31)
T4 PU VDD_1V8_GEN 20mA (1.8/3.3V)
0.1U_0402_10V6K
K29
ULPI_DATA5 T1 PU K30 VDDIO_SYS_1 T23 Z SYS_CLK_REQ
2 ULPI_DATA6 1 VDDIO_SYS_2 SYS_CLK_REQ PAD T2
T2 PU
C44
ULPI_DATA7 R22
CLK_32K_IN 0 PMU_CLK_32K (31)
M2 U27
ULPI_CLK AUDIO_UART4_TX (16) 2 CLK_32K_OUT CLK_32K_OUT (25)
M4 Z
ULPI_DIR AUDIO_UART4_RX (16)
N2 Z
ULPI_NXT EN_VDD_GPS (24)
N4 Z J30 PU
ULPI_STP EN_SENSOR_1V8# (23) KB_COL00 PU SC_LOCK# (22) +VDD_1V8_SYS_TEGRA
2
R77
1 +VDD_1V8_BB_TEGRA Deep Sleep : ON KB_COL01
N26
V25 PU VOL_UP# (22,4)
KB_COL02 PU VOL_DOWN# (22,4)
100K_0402_5% 100K_0402_5% R26
KB_COL03 EN_CAM_2V8 (20)
2
PU
10K_0402_5%
2 1 R379 W26
KB_COL04 BOARD_ID_WP (4)
N3 PD PU
A210@
R30
DAP3_DIN M3 PD KB_COL05 PU
R195
P27
DAP3_DOUT WF_RST# (25) KB_COL06
R4 PD N29 PU
DAP3_FS BT_WAKEUP (25) KB_COL07
R6 PD
EN_SENSOR_3V3_2 (23)
1
DAP3_SCLK
R164 2 1100K_0402_5% T26 PD
3 +VDD_1V8_BB_TEGRA KB_ROW00 WAKEUP_LED (27) 3
RB751V-40_SOD323-2 0_0402_5% M23 PD PCB_ID3
R1 Z ON_KEY# 2 1 2 R65 1 KB_ROW01 V27 PD
GPIO_PV0 ONKEY_R# (22) KB_ROW02 EN_CAM_1V8# (23)
R2 Z D20 M28 PD
GPIO_PV1 KB_ROW03
2
PD
10K_0402_5%
N24
KB_ROW04 PD
@
N30
KB_ROW05 UART_SW (18)
1
PD
R163
T24
@ R1560 KB_ROW06 T25 PD
KB_ROW07 PD @ PAD T10
100K_0402_5% R27
SHORT_DET (17)
1
KB_ROW08 M26 PD
+VDD_1V8_SYS_TEGRA KB_ROW09 R25 PD
WF_WAKE# (25)
2
KB_ROW10 M27 PD
KB_ROW11 PD @ PAD T14
@ JDBUG1 N23 1 @ 2
KB_ROW12 PD SD_DET# (21,4)
T30L-P-A3-1.2G_FCBGA728 0_0402_5% 1 V28 R405 0_0402_5%
1 KB_ROW13 PD G_ACC_INT (19)
JTAG_TRST#2 R1561 1 2 M25
JTAG_TDI 3 2 KB_ROW14 V26 PD
3 KB_ROW15 BT_IRQ# (25)
JTAG_TMS 4
JTAG_TCK 5 4
JTAG_RTCK 6 5
JTAG_TDO 7 6 T27 JTAG_TCK
7 JTAG_TCK @ PAD T4
8 R29 JTAG_TDI
(22) HOT_RST# 8 JTAG_TDI @ PAD T5
ONKEY_R# 9 T28 JTAG_TDO
9 JTAG_TDO @ PAD T6
10 R23 JTAG_TMS
10 JTAG_TMS @ PAD T7
11 T22 JTAG_TRST#
GND JTAG_TRST_N @ PAD T8
12 V24 JTAG_RTCK
GND JTAG_RTCK @ PAD T9
For JTAG ACES_87036-1001-CP
R57 @ M30 NV_THERM_DN
THERM_DN
0.1U_0402_10V6K
49.9_0402_1% N22
OWR
AC18
max current is 350uA 2 JTAG_TDI R155 1 2 HDMI_CEC
+3VS 10K_0402_5% R28 TEST_MODE_EN
VR1 =17mV JTAG_TMS R159 1 2 TEST_MODE_EN
10K_0402_5%
1
2
0_0402_5%
R59 JTAG_RTCK R160 1 2
1
R62
4 100_0402_1% R58 10K_0402_5% T30L-P-A3-1.2G_FCBGA728 4
NV_THERM_DP 1 2 THERMD_F_P R60 JTAG_TCK R161 2 1 100K_0402_5%
U4 100K_0402_5%
1
1000P_0402_50V7K 2 1 100K_0402_5% JTAG_TRST# R162 2 @ 1 100K_0402_5%
2
1
R61 3 D+ Vcc
2
100_0402_1% C46 D- 4
2 THERM# AP_OVERHEAT# (31)
NV_THERM_DN 1 2 THERMD_F_N 6
ALERT#/ THERM2# TEMP_ALERT# (4)
PWR_I2C_SCL 8
(16,17,29,31,33,4,7) PWR_I2C_SCL PWR_I2C_SDA 7 SCLK 5
(16,17,29,31,33,4,7) PWR_I2C_SDA SDATA GND
NCT72CMNR2G_DFN8_3x3
Security Classification Compal Secret Data Compal Electronics, Inc.
Thermal Issued Date 2012/05/20 Deciphered Date 2012/01/09 Title
T30L-UART/OSC/PLL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 7 of 35
A B C D E
A B C D E F G H
0.1U_0402_10V6K
AC23 GND_007 2
AC26 GND_008
AC29 GND_009
AC5 GND_010
AC8 GND_011 For placement question, limint by H=0.5mm
AF11 GND_012
AF14 GND_013 VDD_1V0_CPU_TEGRA VDD_1V0_GEN
AF17 GND_014 J1
AF2 GND_015
(0.9 ~ 1.0V)
H10 10A@ 1.2375V(max) 2 1
VDD_1V0_CPU_TEGRA
AF20 GND_016 VDD_CPU_01 J10 2 1
AF23 GND_017 VDD_CPU_02 J8 @ JUMP_43X118
AF26 GND_018 VDD_CPU_03 K8
GND_019 VDD_CPU_04 C25631 C25641 C25651 C25661 1 1 1 1 1 1 1 1
AF29 K9
AF5 GND_020 VDD_CPU_05 M7 C2599 C2598 C2567 C2568 C2569 C2570 C2571 C2572
GND_021 VDD_CPU_06 1 C2573 1 C2574 1 C2575 1 C2576 1 C2577 1 C2578 1 C2579 1 C2580
AF8 M8
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
GND_022 VDD_CPU_07 2 2 2 2 2 2 2 2 2 2 2 2
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
AJ1 M9
AJ11 GND_023 VDD_CPU_08 N8
AJ14 GND_024 VDD_CPU_09 N9 2 2 2 2 2 2 2 2
AJ17 GND_025 VDD_CPU_10 P14
AJ2 GND_026 VDD_CPU_11 P15
AJ20 GND_027 VDD_CPU_12 P16
AJ23 GND_028 VDD_CPU_13 P17
AJ26 GND_029 VDD_CPU_14 R14
2 AJ29 GND_030 VDD_CPU_15 R17 2
AJ30 GND_031 VDD_CPU_16 T14
AJ5 GND_032 VDD_CPU_17 T17
AJ8 GND_033 VDD_CPU_18 U14
AK2 GND_034 VDD_CPU_19 U15
AK29 GND_035 VDD_CPU_20 U16
B1 GND_036 VDD_CPU_21 U17
B11 GND_037 VDD_CPU_22
B14 GND_038
B17 GND_039
B2 GND_040
B20 GND_041
B23 GND_042
B26 GND_043 For placement question, limint by H=0.5mm
B29 GND_044
B30 GND_045
B5 GND_046 VDD_1V2_CORE_TEGRA VDD_1V2_SOC
B8 GND_047 VDD_1V2_CORE_TEGRA
E11 GND_048 R1392
E14 GND_049
(1.0 ~ 1.2V)
M13 3A@ 1.3V(max) 2 1
E17 GND_050 VDD_CORE_01 M15
E2 GND_051 VDD_CORE_02 M17 0_0805_5%
E20 GND_052 VDD_CORE_03 M19 1 C2590 1 C2591 1 C2592 1 C2593 1 C2594 1 C2595 1 C2596 1 C2597
E23 GND_053 VDD_CORE_04 N12
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
GND_054 VDD_CORE_05 C25811 C25821 C25831 1 1 1 1 1 1 1 1
E26 N14
E29 GND_055 VDD_CORE_06 N16 C2656 C2655 C2584 C2585 C2586 C2587 C2588 C2589
E5 GND_056 VDD_CORE_07 N18 2 2 2 2 2 2 2 2
0.1U_0402_10V6K
0.1U_0402_10V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
E8 N7
H11 GND_058 VDD_CORE_09 P13
H14 GND_059 VDD_CORE_10 P19
3 H17 GND_060 VDD_CORE_11 R12 3
H2 GND_061 VDD_CORE_12 R18
H20 GND_062 VDD_CORE_13 R7
H23 GND_063 VDD_CORE_14 R8
H26 GND_064 VDD_CORE_15 R9
H29 GND_065 VDD_CORE_16 T13
H5 GND_066 VDD_CORE_17 T19
H8 GND_067 VDD_CORE_18 T8
L2 GND_068 VDD_CORE_19 T9
L23 GND_069 VDD_CORE_20 U18
L26 GND_070 VDD_CORE_21 V13
L29 GND_071 VDD_CORE_22 V15
L5 GND_072 VDD_CORE_23 V17
L8 GND_073 VDD_CORE_24 V19
M12 GND_074 VDD_CORE_25 W14
M14 GND_075 VDD_CORE_26 W16
M16 GND_076 VDD_CORE_27 W18
M18 GND_077 VDD_CORE_28
N13 GND_078
N15 GND_079
N17 GND_080
N19 GND_081
P12 GND_082
GND_083 @ PAD T22
P18
P2 GND_084 Layout route as Diff. pair ( Z = 90 ohm )
GND_085 @ PAD T23
P23
P26 GND_086 AB12 90DIFF_NETCLASS1
VDD_CPU_SENSE_PAIR
GND_087 VDD_CPU_SENSE VDD_CPU_SENSE (33)
P29
P5 GND_088 AB15 90DIFF_NETCLASS1
VDD_CPU_SENSE_PAIR
GND_089 GND_CPU_SENSE GND_CPU_SENSE (33)
P8
4 R13 GND_090 4
R15 GND_091 Layout route as Diff. pair ( Z = 90 ohm )
R16 GND_092
R19 GND_093 AB16 VVDD_CPU_SENSE VVDD_CPU_SENSE_PAIR 90DIFF_NETCLASS1
GND_094 VVDD_CPU_SENSE @ PAD T24
T12
T15 GND_095 AA23 VGND_CORE_SENSE VVDD_CPU_SENSE_PAIR 90DIFF_NETCLASS1
GND_096 VGND_CORE_SENSE @ PAD T25
T16
T18 GND_097
U13 GND_098
GND_099 @ PAD T26
U19
U2 GND_100
GND_101 @ PAD T27 Layout route as Diff. pair ( Z = 90 ohm )
U23
U26 GND_102 W23 VDD_CORE_SENSE
GND_103 VDD_CORE_SENSE VDD_CORE_SENSE (33)
U29
U5 GND_104 W22 GND_CORE_SENSE
GND_105 GND_CORE_SENSE GND_CORE_SENSE (33)
U8
V12 GND_106
V14 GND_107 +VDD_3V3_FUSE_TEGRA
V16 GND_108
V18 GND_109
W12 GND_110
(3.3V) AB8 40mA@ 3.3V
W13 GND_111 VPP_FUSE
W15 GND_112 AA4 VPP_KFUSE
(3.3V)
W17 GND_113 VPP_KFUSE
GND_114 1
W19 C2600
GND_115
2
Y2
Y23 GND_116 R1395 R1396
0.1U_0402_10V6K
5 Y8 GND_120 5
GND_121
T30L-P-A3-1.2G_FCBGA728
AB18
AB19
(1.05V)
AVDD_PEXA_1 PEX_L0_TXN
AG18
AF18
T30 VI Interface
AVDD_PEXA_2 PEX_L0_TXP
POR State/ After Wake State/ Wake-Up Events
AJ19 PU: Pull Up
PEX_L0_RXN AH19 PD: Pull Down
PEX_L0_RXP
Z: High Impendance
R: Reset
D D
H: Hold
W: Wake-Up Event
AF19
PEX_L1_TXN AG19
PEX_L1_TXP
(1.05V) U1F
AD22 AK22
VDD_PEXA PEX_L1_RXN AK21 19/22 VI
PEX_L1_RXP
(1.2 / 1.8V)
AH30 AE26 PD/H
VDDIO_VI VI_MCLK
AF25 PD/H
T30 SPARE Pins
AJ18 VI_PCLK U1V
PEX_L2_TXN AH18 22/22 NC
PEX_L2_TXP AD27 PD/H
VI_HSYNC AG30 PD/H AB10
AK19 VI_VSYNC NC_37 AB5
PEX_L2_RXN AK18 NC_38 AC19
(3.3V)
AB21 PEX_L2_RXP NC_39 AC9
HVDD_PEX NC_40 C25
AF27 PD/H NC_41 E13
VI_D00 AD30 PD/H NC_42 H25
AK24 VI_D01 AH29 PD/H NC_43
PEX_L3_TXN AK25 VI_D02 AG28 PD/H/W
PEX_L3_TXP VI_D03 AE27 PD/H
VI_D04 AE25 PD/H
AJ21 VI_D05 AG29 PD/H
PEX_L3_RXN AH21 VI_D06 AD29 PD/H
PEX_L3_RXP VI_D07 AE29 PD/H
VI_D08 AD28 PD/H
VI_D09 AE30 PD/H
VI_D10 AE28 PD/H
VI_D11
(1.05V)
AC22 AG21
AVDD_PEXB PEX_L4_TXN AF21
PEX_L4_TXP T30L-P-A3-1.2G_FCBGA728
AB11
NC_1 AB14
C C
AJ24 NC_2 AB17
PEX_L4_RXN AH24 NC_3 AB20
PEX_L4_RXP NC_4 AB22
NC_5 AB9
NC_6 AE11
NC_7 AE14
AJ25 NC_8 AE17
PEX_L5_TXN AH25 NC_9 AE20
(1.05V)
AE23 PEX_L5_TXP NC_10 F11
VDD_PEXB NC_11 F14
AG22 NC_12 F17
PEX_L5_RXN AG23 NC_13 F20
PEX_L5_RXP NC_14 J11
NC_15 J14
NC_16 J17
NC_17 J20
NC_18 J22
NC_19 J9
NC_20 L22
NC_21 L25
NC_22 L6
NC_23 L9
NC_24 P22
NC_25 P25
NC_26 P6
NC_27 P9
NC_28 U22
NC_29 U25
NC_30 U6
NC_31 U9
NC_32 Y22
AE24
(1.05V)
AK28
T30 SATA Interface NC_33
NC_34
NC_35
Y25
Y6
Y9
AVDD_PEX_PLL PEX_CLK1N AK27 NC_36
PEX_CLK1P
U1U
B B
AB24 T30L-P-A3-1.2G_FCBGA728
PEX_CLK2N AB23 21/22 NC
PEX_CLK2P 75mA@ 1.05V AVDD_SATA AC15 (1.05V) AD16
AVDD_SATA SATA_L0_TXN AE16
AH27 18mA@ 1.05V VDD_SATA AF15 (1.05V)
SATA_L0_TXP
PEX_CLK3N AJ27 VDD_SATA
PEX_CLK3P 10mA@ 3.3V HVDD_SATA AC16 (3.3V) AE19
HVDD_SATA SATA_L0_RXN AD19
120mA@ 1.05V AVDD_SATA_PLL AG17 (1.05V)
SATA_L0_RXP
AVDD_SATA_PLL
AJ22
PEX_REFCLKN AH22
PEX_REFCLKP
AE21
SATA_TESTCLKN AD21
SATA_TESTCLKP
(3.3V) AD18
AF24 AG24 SATA_TERMP
VDDIO_PEX_CTL PEX_L0_CLKREQ* AD25
PEX_L0_PRSNT* AG26
PEX_L0_RST*
AD26 T30L-P-A3-1.2G_FCBGA728
PEX_L1_CLKREQ* AD24
PEX_L1_PRSNT* AG27
PEX_L1_RST*
AC21
PEX_L2_CLKREQ* AE22
PEX_L2_PRSNT* AG25
PEX_L2_RST*
AF22
PEX_WAKE*
AJ28
PEX_TESTCLKN AH28
A A
PEX_TESTCLKP
AG20
PEX_TERMP
T30L-P-A3-1.2G_FCBGA728
Title
T30L-PEX/SATA/VI
Size Document Number Rev
C 1.0
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 9 of 35
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
<Title>
DDR3/DDR3L (page 1/2): 4pcs, 2Gbx4 memory chips: RANK 0: LOW 16 BITS Note: Layout use the 82 ball biggest packages and co-Layout 78 ball
A210 use 78 ball H5TC2G83CFR-H9A
700mA@ 1.35V
VDD_1V35_DDR3_MEM VDD_1V35_DDR3_MEM
U150A U151A
F4 A3 DDR_RAS# F4 A3
(12,5) DDR_RAS# RAS* VDD[0] RAS* VDD[0]
G4 A10 DDR_CAS# G4 A10
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
(12,5) DDR_CAS#
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
H4 CAS* VDD[1] D8 DDR_WE# H4 CAS* VDD[1] D8
(12,5) DDR_WE# WE* VDD[2] 1 1 1 1 1 WE* VDD[2] 1 1 1 1 1
H3 G3 C2601 C2602 C2603 C2604 C2605 DDR_CS0# H3 G3 C2606
(12,5) DDR_CS0# CS* VDD[3] CS* VDD[3]
G9 G9 C2607 C2608 C2609 C2610
(12,5) DDR_A[14..0] VDD[4] VDD[4]
DDR_A0 K4 K2 DDR_A0 K4 K2
DDR_A1 L8 A[0] VDD[5] K10 2 2 2 2 2 DDR_A1 L8 A[0] VDD[5] K10 2 2 2 2 2
DDR_A2 L4 A[1] VDD[6] M2 DDR_A2 L4 A[1] VDD[6] M2
DDR_A3 K3 A[2] VDD[7] M10 DDR_A3 K3 A[2] VDD[7] M10
DDR_A4 L9 A[3] VDD[8] DDR_A4 L9 A[3] VDD[8]
DDR_A5 L3 A[4] B10 VDD_1V35_DDR3_MEM DDR_A5 L3 A[4] B10 VDD_1V35_DDR3_MEM
DDR_A6 M9 A[5] VDDQ[0] C2 DDR_A6 M9 A[5] VDDQ[0] C2
DDR_A7 M3 A[6] VDDQ[1] E3 DDR_A7 M3 A[6] VDDQ[1] E3
DDR_A8 N9 A[7] VDDQ[2] E10 DDR_A8 N9 A[7] VDDQ[2] E10
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
A[8] VDDQ[3] A[8] VDDQ[3]
0.1U_0402_10V6K
DDR_A9 M4 DDR_A9 M4
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
A[9] 1 1 1 A[9] 1 1 1
DDR_A10 H8 C2611 DDR_A10 H8 C2614
DDR_A11 M8 A[10]/AP DDR_A11 M8 A[10]/AP
C2612 C2613 C2615 C2616
DDR_A12 K8 A[11] DDR_A12 K8 A[11]
DDR_A13 N4 A[12]/BC* 2 2 2 DDR_A13 N4 A[12]/BC* 2 2 2
DDR_A14 N8 A[13] DDR_A14 N8 A[13]
A[14] B3 A[14] B3
J3 VSSQ[0] B9 DDR_BA0 J3 VSSQ[0] B9
(12,5) DDR_BA0 BA[0] VSSQ[1] BA[0] VSSQ[1]
2 K9 C10 DDR_BA1 K9 C10
(12,5) DDR_BA1 BA[1] VSSQ[2] BA[1] VSSQ[2]
J4 D2 DDR_BA2 J4 D2
(12,5) DDR_BA2 BA[2] VSSQ[3] BA[2] VSSQ[3]
D10 D10
G10 VSSQ[4] DDR_CKE0 G10 VSSQ[4]
(12,5) DDR_CKE0 CKE CKE
F8 A2 DDR_CLKP F8 A2
(12,5) DDR_CLKP CK VSS[0] CK VSS[0]
G8 A9 DDR_CLKN G8 A9
(12,5) DDR_CLKN CK* VSS[1] CK* VSS[1]
B2 B2
VSS[2] D9 VSS[2] D9
F2 VSS[3] F3 F2 VSS[3] F3
F10 NC_F2 VSS[4] F9 F10 NC_F2 VSS[4] F9
H2 NC_F10 VSS[5] J2 H2 NC_F10 VSS[5] J2
H10 NC_H2 VSS[6] J10 H10 NC_H2 VSS[6] J10
NC_H10 VSS[7] L2 NC_H10 VSS[7] L2
VSS[8] L10 VSS[8] L10
N3 VSS[9] N2 DDR_RESET# N3 VSS[9] N2
(12,5) DDR_RESET# RESET* VSS[10] RESET* VSS[10]
N10 N10
G2 VSS[11] DDR_ODT0 G2 VSS[11]
(12,5) DDR_ODT0 ODT ODT
1R1398 2 M1_ZQ H9 1 R1399 2 M4_ZQ H9
243_0402_1% A1 ZQ 243_0402_1% A1 ZQ
A11 NC_A1 A11 NC_A1
N1 NC_A11 VDD_0V675_DDR3_VREF N1 NC_A11 VDD_0V675_DDR3_VREF
N11 NC_N1 N11 NC_N1
A4 NC_N11 E2 A4 NC_N11 E2
DDR_A15 J8 NC_A4 VREFDQ J9 DDR_A15 J8 NC_A4 VREFDQ J9
(12,5) DDR_A15 NC_J8 VREFCA NC_J8 VREFCA
X76@ H5TC2G83BFR-PBA_FBGA82 X76@ H5TC4G83MFR-PBA _FBGA82
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1
3 2 2 2 2
1
R1400
1K_0402_1%
VDD_0V675_DDR3_VREF
2
1
R1401
1K_0402_1% NB DDR3 design
2
(12,5) DDR_DQ[31..0]
U150B
DDR_DQ4 B4 U151B
DDR_DQ7 C8 DQ[0] DDR_DQ23 B4
DDR_DQ0 C3 DQ[1] DDR_DQ18 C8 DQ[0]
DDR_DQ5 C9 DQ[2] DDR_DQ17 C3 DQ[1]
DDR_DQ2 E4 DQ[3] DDR_DQ22 C9 DQ[2]
DDR_DQ3 E9 DQ[4] DDR_DQ20 E4 DQ[3]
DDR_DQ1 D3 DQ[5] DDR_DQ19 E9 DQ[4]
DDR_DQ6 E8 DQ[6] DDR_DQ16 D3 DQ[5]
A8 DQ[7] DDR_DQ21 E8 DQ[6]
B8 NF/TDQS* A8 DQ[7]
(5) DDR_DM0 DM/TDQS NF/TDQS*
C4 B8
(5) DDR_DQS0P DQS (5) DDR_DM2 DM/TDQS
D4 C4
(5) DDR_DQS0N DQS* (5) DDR_DQS2P DQS
D4
4
(5) DDR_DQS2N DQS*
X76@ H5TC4G83MFR-PBA_FBGA82
X76@ HH5TC4G83MFR-PBA_FBGA82
A B C D E F G
DDR3/DDR3L(page 2/2): 4pcs, 2Gbx4 memory chips: RANK 0: HIGH 16 BITS
1 VDD_1V35_DDR3_MEM VDD_1V35_DDR3_MEM
U152A U153A
F4 A3 DDR_RAS# F4 A3
(11,5) DDR_RAS# RAS* VDD[0] RAS* VDD[0]
G4 A10 DDR_CAS# G4 A10
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
(11,5) DDR_CAS#
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
CAS* VDD[1] CAS* VDD[1]
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
H4 D8 1 1 1 1 1 DDR_WE# H4 D8 1 1 1 1 1
(11,5) DDR_WE# WE* VDD[2] WE* VDD[2]
H3 G3 C2621 DDR_CS0# H3 G3 C2626
(11,5) DDR_CS0# CS* VDD[3] CS* VDD[3]
G9 C2622 C2623 C2624 C2625 G9 C2627 C2628 C2629 C2630
(11,5) DDR_A[14..0] VDD[4] VDD[4]
DDR_A0 K4 K2 DDR_A0 K4 K2
DDR_A1 L8 A[0] VDD[5] K10 2 2 2 2 2 DDR_A1 L8 A[0] VDD[5] K10 2 2 2 2 2
DDR_A2 L4 A[1] VDD[6] M2 DDR_A2 L4 A[1] VDD[6] M2
DDR_A3 K3 A[2] VDD[7] M10 DDR_A3 K3 A[2] VDD[7] M10
DDR_A4 L9 A[3] VDD[8] DDR_A4 L9 A[3] VDD[8]
DDR_A5 L3 A[4] B10 VDD_1V35_DDR3_MEM DDR_A5 L3 A[4] B10 VDD_1V35_DDR3_MEM
DDR_A6 M9 A[5] VDDQ[0] C2 DDR_A6 M9 A[5] VDDQ[0] C2
DDR_A7 M3 A[6] VDDQ[1] E3 DDR_A7 M3 A[6] VDDQ[1] E3
DDR_A8 N9 A[7] VDDQ[2] E10 DDR_A8 N9 A[7] VDDQ[2] E10
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
DDR_A9 M4 A[8] VDDQ[3] DDR_A9 M4 A[8] VDDQ[3]
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
A[9] 1 1 1 A[9] 1 1 1
DDR_A10 H8 C2631 DDR_A10 H8 C2634
DDR_A11 M8 A[10]/AP DDR_A11 M8 A[10]/AP
C2632 C2633 C2635 C2636
DDR_A12 K8 A[11] DDR_A12 K8 A[11]
DDR_A13 N4 A[12]/BC* 2 2 2 DDR_A13 N4 A[12]/BC* 2 2 2
DDR_A14 N8 A[13] DDR_A14 N8 A[13]
A[14] B3 A[14] B3
J3 VSSQ[0] B9 DDR_BA0 J3 VSSQ[0] B9
(11,5) DDR_BA0 BA[0] VSSQ[1] BA[0] VSSQ[1]
K9 C10 DDR_BA1 K9 C10
(11,5) DDR_BA1 BA[1] VSSQ[2] BA[1] VSSQ[2]
J4 D2 DDR_BA2 J4 D2
(11,5) DDR_BA2 BA[2] VSSQ[3] BA[2] VSSQ[3]
D10 D10
G10 VSSQ[4] DDR_CKE0 G10 VSSQ[4]
(11,5) DDR_CKE0 CKE CKE
F8 A2 DDR_CLKP F8 A2
(11,5) DDR_CLKP CK VSS[0] CK VSS[0]
2 G8 A9 DDR_CLKN G8 A9
(11,5) DDR_CLKN CK* VSS[1] CK* VSS[1]
B2 B2
VSS[2] D9 VSS[2] D9
F2 VSS[3] F3 F2 VSS[3] F3
F10 NC_F2 VSS[4] F9 F10 NC_F2 VSS[4] F9
H2 NC_F10 VSS[5] J2 H2 NC_F10 VSS[5] J2
H10 NC_H2 VSS[6] J10 H10 NC_H2 VSS[6] J10
NC_H10 VSS[7] L2 NC_H10 VSS[7] L2
VSS[8] L10 VSS[8] L10
N3 VSS[9] N2 DDR_RESET# N3 VSS[9] N2
(11,5) DDR_RESET# RESET* VSS[10] RESET* VSS[10]
N10 N10
G2 VSS[11] DDR_ODT0 G2 VSS[11]
(11,5) DDR_ODT0 ODT ODT
1R1402 2 M3_ZQ H9 1R1403 2 M2_ZQ H9
243_0402_1% A1 ZQ 243_0402_1% A1 ZQ
A11 NC_A1 A11 NC_A1
N1 NC_A11 VDD_0V675_DDR3_VREF N1 NC_A11 VDD_0V675_DDR3_VREF
N11 NC_N1 N11 NC_N1
A4 NC_N11 E2 A4 NC_N11 E2
DDR_A15 J8 NC_A4 VREFDQ J9 DDR_A15 J8 NC_A4 VREFDQ J9
(11,5) DDR_A15 NC_J8 VREFCA NC_J8 VREFCA
X76@ H5TC4G83MFR-PBA _FBGA82 X76@ H5TC4G83MFR-PBA_FBGA82
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1
U153B
U152B DDR_DQ29 B4
(11,5) DDR_DQ[31..0] DQ[0]
DDR_DQ11 B4 DDR_DQ25 C8
DDR_DQ10 C8 DQ[0] DDR_DQ26 C3 DQ[1]
DDR_DQ12 C3 DQ[1] DDR_DQ27 C9 DQ[2]
DDR_DQ13 C9 DQ[2] DDR_DQ28 E4 DQ[3]
DDR_DQ9 E4 DQ[3] DDR_DQ24 E9 DQ[4]
DDR_DQ14 E9 DQ[4] DDR_DQ30 D3 DQ[5]
DDR_DQ8 D3 DQ[5] DDR_DQ31 E8 DQ[6]
DDR_DQ15 E8 DQ[6] A8 DQ[7]
A8 DQ[7] B8 NF/TDQS*
NF/TDQS* (5) DDR_DM3 DM/TDQS
B8 C4
(5) DDR_DM1 DM/TDQS (5) DDR_DQS3P DQS
C4 D4
(5) DDR_DQS1P DQS (5) DDR_DQS3N DQS*
D4
(5) DDR_DQS1N DQS* X76@ H5TC4G83MFR-PBA_FBGA82
X76@ H5TC4G83MFR-PBA_FBGA82
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC(Reserved)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 13 of 35
5 4 3 2 1
5 4 3 2 1
+VDD_2V85_EMMC +3VS
+VDD_2V85_EMMC
+VDDIO_1V8_EMMC U51
VDD_1V8_GEN R422 1 @ 2 200mA @ C148 C149 @ C150 C117 C118 1
+3VS VIN
0_0402_5% R437
1 5 1 2
10U_0402_6.3V6M
10U_0402_6.3V6M
VOUT
22U_0603_6.3V6M
2 33mA
10U_0402_6.3V6M
0.1U_0402_10V6K
R101 1 2 2 1 1 C385 2
GND
1
+VDDIO_1V8_EMMC 0_0402_5% 2.2U_0402_6.3V6M 0_0402_5%
2
+VDD_2V85_EMMC 0_0402_5% 4
C119 2 R440 1 2 3 NC C365
1 1 1
2
1 1 2 2 EN
1U_0402_10V4Z
1 @ 2 1
D (5) EN_3V3_EMMC D
2.2U_0402_6.3VM R439 G9001-300TO1U TSOT-23 5P LDO
2 2 2 (4) EN_3V3_EMMC1
0_0402_5%
SA00005II00
C120 C121
AA3
AA5
T10
W4
M6
N5
U9
0.1U_0402_10V6K 0.1U_0402_10V6K
K6
Y4
U13
A4
VCC
VCC
VCC
VCC
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
A6 NC +VDDIO_1V8_EMMC
A9 NC
A11 NC W5 EMMC_CMD_R 1 2
B2 NC CMD R102 33_0402_5% EMMC_CMD (4)
B13 NC
D1 NC
D14 NC
NC
2
H1
H2 NC R113 R114
NC
4.7K_0402_5%
4.7K_0402_5%
H6 W6 EMMC_CLK_R R103 1 2 0_0402_5%
H7 NC CLK 1 2 C122 EMMC_CLK (4)
H8 NC 12P_0402_50V4Z
close U13
1
H9 NC
H10 NC
H11 NC
H12 NC H3 EMMC_DAT0_R R104 1 2 33_0402_5%
H13 NC DAT0 H4 EMMC_DAT1_R R105 1 2 33_0402_5% EMMC_DA0 (4) EMMC_CMD_R
H14 NC DAT1 H5 EMMC_DAT2_R R106 1 2 33_0402_5% EMMC_DA1 (4)
J1 NC DAT2 J2 EMMC_DAT3_R R107 1 2 33_0402_5% EMMC_DA2 (4) MMC_RST#
J7 NC DAT3 J3 EMMC_DAT4_R R108 1 2 33_0402_5% EMMC_DA3 (4)
J8 NC DAT4 J4 EMMC_DAT5_R R109 1 2 33_0402_5% EMMC_DA4 (4)
J9 NC DAT5 J5 EMMC_DAT6_R R110 1 2 33_0402_5% EMMC_DA5 (4)
J10 NC DAT6 J6 EMMC_DAT7_R R111 1 2 33_0402_5% EMMC_DA6 (4)
J11 NC DAT7 EMMC_DA7 (4)
J12 NC
J13 NC K2 C123 1 2
J14 NC VDDi
K1 NC U1 0.1U_0402_10V6K
K3 NC NC U2
K5 NC NC U3
C C
K7 NC NC U5 MMC_RST# R112 1 2 0_0402_5%
K8 NC RSTN U6 EMMC_RST# (4)
K9 NC NC U7
K10 NC NC U10
K11 NC NC U12
K12 NC NC U13
K13 NC NC U14
K14 NC NC V1 U13
NC NC
L1
L2 NC NC
V2
V3
SS8GB@ KLM8G2FE3B-B001
L3 NC NC V12
L4 NC NC V13 SA00005KM10
L12 NC NC V14
L13 NC NC W1 U13
NC NC
L14
M1 NC NC
W2
W3
SD8GB@ SDIN5D1-8G-L
M2 NC NC W7
M3 NC NC W8 SA00005MV10
M5 NC NC W9
M8 NC NC W10
M9 NC NC W11
M10 NC NC W12
M12 NC NC W13
M13 NC NC W14
M14 NC NC Y1
N1 NC NC Y3
N2 NC NC Y6
N3 NC NC Y7
N10 NC NC Y8
N12 NC NC Y9
N13 NC NC Y10 U13
NC NC
N14
P1 NC NC
Y11
Y12
SS16GB@ KLMAG2GE4A-A001
P2 NC NC Y13 SA00005KG10
P3 NC NC Y14
P10 NC NC AA1
P12 NC NC AA2 U13
B NC NC B
P13
P14 NC NC
AA7
AA8
SD16GB@ SDIN5C1-16G-L
R1 NC NC AA9
R2 NC NC AA10 SA00004XA30
R3 NC NC AA11
R5 NC NC AA12
R12 NC NC AA13
R13 NC NC AA14
R14 NC NC AE1
T1 NC NC AE14
T2 NC NC AG2
T3 NC NC AG13
T5 NC NC AH4
T12 NC NC AH6
T13 NC NC AH9
T14 NC NC AH11
NC NC
13
14 NC 1
15 NC NC 2
16 NC NC 3
17 NC NC 4
18 NC NC 5
19 NC NC 6
20 NC NC 7
21 NC NC 8
22 NC NC 9
23 NC NC 10
24 NC NC 11
NC NC 12
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
AA6
AA4
Y5
Y2
K4
U8
R10
P5
M7
@
A SDIN5F1-64G_TFBGA169 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eMMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 14 of 35
5 4 3 2 1
5 4 3 2 1
0.01U_0402_25V7
0.01U_0402_25V7
@ R139
LVDS Bridge 1 1
0_0402_5%1 2 +LEDVDD
B+ FDC604P_NL_SSOT6
+LEDVDD
D
U10 2 2 6 1 R1375 2
S
LCD_D12 51 1 +VDD_BIO @ R140 4 5
(4) LCD_D12 D0 Vcc
2
LCD_D13 52 9 0_0402_5%1 2 2
(4) LCD_D13 D1 Vcc
LCD_D14 54 26 1 1 @ 1 C2652 1
(4) LCD_D14 D2 Vcc 4.7K_0402_5%
1
LCD_D15 55 44 R138 C2650 C2651 C2653
G
(4) LCD_D15 D3 LVDSVcc 1
LCD_D12 @ C1433 1 233P 50V J NPO 0201 LCD_D16 56 34 +VDD_LVDS 0_0402_5%1
0_0402_5% 2 R218 R519
(4) LCD_D16 +3VS
3
D4 PLLVcc
330P_0402_50V7K
10U_0805_25V6K
LCD_D13 @ C1434 1 233P 50V J NPO 0201 LCD_D17 3
0.1U_0402_25V4Z
100K_0402_5% C605
100P_0402_50V8J
(4) LCD_D17
2
LCD_D14 @ C1435 1 233P 50V J NPO 0201 50 D6 47 LVDS_A0 C191 C2657 C474 0.1U_0402_25V6 2 2 2
LCD_D15 @ C1436 1 233P 50V J NPO 0201 2 D27 Y0P 48 LVDS_A0# BSS138W-7-F_SOT323-3~D 2
1 1 1 D
2
D5 Y0M
1
0.01U_0402_25V7
LCD_D16 @ C1437 1 233P 50V J NPO 0201 Q55
D D
4.7U_0603_6.3V6K
LCD_D17 @ C1438 1 233P 50V J NPO 0201 LCD_D06 4 2 1 2 LEDVDD_GATE
(4) LCD_D06 D7
1U_0402_10V4Z
LCD_D06 @ C1439 1 233P 50V J NPO 0201 LCD_D07 6 45 LVDS_A1 G
(4) LCD_D07 D8 Y1P 2 2 2
LCD_D07 @ C1440 1 233P 50V J NPO 0201 LCD_D08 7 46 LVDS_A1# S R825
(4) LCD_D08
3
LCD_D08 @ C1441 1 233P 50V J NPO 0201 LCD_D09 11 D9 Y1M 120K_0402_5%
(4) LCD_D09 D12 D
1
LCD_D09 @ C1442 1 233P 50V J NPO 0201
(4) LCD_D10
LCD_D10 12
D13 for EMI
LCD_D10 @ C1443 1 233P 50V J NPO 0201 LCD_D11 14 41 LVDS_A2 EN_VDDLCD_T30S 2 Q57
(4) LCD_D11 D14 Y2P
LCD_D11 @ C1444 1 233P 50V J NPO 0201 8 42 LVDS_A2# G BSS138W-7-F_SOT323-3~D
LCD_D00 @ C1445 1 233P 50V J NPO 0201 10 D10 Y2M
S
1.8V level
3
LCD_D01 @ C1446 1 233P 50V J NPO 0201 D11
LCD_D02 @ C1447 1 233P 50V J NPO 0201
(4) LCD_D00
LCD_D00 15
D15 Y3P
37 Close to U10
LCD_D03 @ C1448 1 233P 50V J NPO 0201 LCD_D01 19 38
(4) LCD_D01 D18 Y3M
LCD_D04 @ C1449 1 233P 50V J NPO 0201 LCD_D02 20
(4) LCD_D02 D19
LCD_D05 @ C1450 1 233P 50V J NPO 0201 LCD_D03 22
(4) LCD_D03 D20
LCD_HSYNC @ C1451 1 233P 50V J NPO 0201 LCD_D04 23 39 LVDS_ACLK
(4) LCD_D04 D21 CLKOUTP
LCD_VSYNC @ C1452 1 233P 50V J NPO 0201 LCD_D05 24 40 LVDS_ACLK#
(4) LCD_D05 D22 CLKOUTM
LCD_DE @ C1453 1 233P 50V J NPO 0201 16
18 D16 5
D17 GND
for EMI GND
13
LCD_HSYNC 27 21
(4) LCD_HSYNC D24 GND
LCD_VSYNC 28 53
(4) LCD_VSYNC D25 GND 29
LVDS_SHTDN# 32 GND 33
(4) LVDS_SHTDN# SHTDN# PLLGND
LCD_DE 30 35
(4) LCD_DE D26 PLLGND
25 36 LVDS_SHTDN#
LCD_PCLK 31 D23 LVDSGND 43 LVDS_A00 C101 1 2 12P_0402_50V4Z
(4) LCD_PCLK CLKIN LVDSGND
+VDD_BIO 1 2 17 49
CLKSEL LVDSGND LVDS_A00# C102 1 2 12P_0402_50V4Z
1
R1409 10K_0402_5% R99
SN75LVDS83DGGRG4_TSSOP56 LVDS_A01 C103 1 2 12P_0402_50V4Z
1 : Rising edge 100K_0402_5%
0 : Falling edge LVDS_A01# C104 1 2 12P_0402_50V4Z
2
LVDS_A02 C105 1 2 12P_0402_50V4Z
for EMI
Close JLVDS3
JLVDS3
+LEDVDD 1
2 1
3 2
LVDS_A0 1 R1332 2 LVDS_A00 2 1 4 3
(4) IMG_EN 4
0_0402_5% 5
R1027 4.7K_0402_5% 6 5
7 6
LCD POWER CIRCUIT 1 2
+LCDVDD 8
9
7
8
1 2 R1344 1 20_0402_5% 10 9
WCM-2012HS-900T_0805 +3VS 10
AP_SMB_SCL 11
11
1
U97
8
FBMA-L11-201209-221LMA30T_0805
1
+LCDVDD_L 2 L6
280mA 4
4 3
3
EDID AP_SMB_SDA 12
13 12
GND OUT +LCDVDD @ L87 13
+3VS 2 7 14
3 IN OUT 6 C2654 LVDS_A0# 1 R1333 2 LVDS_A00# 15 14
IN OUT 15
0.1U_0402_10V7K
4.7U_0603_6.3V6K
S LVDS_ACLK0# 21
3
21
2
R1410 1 2 @ C1232 22
100K_0402_5% 1 2 R1417 LVDS_A02 23 22
39P 50V J NPO 0402 23
WCM-2012HS-900T_0805 1 LVDS_A02# 24
100K_0402_5% 24
4 3 25 31
1
4 3 LVDS_A01 26 25 GND1 32
1
@ L88 LVDS_A01# 27 26 GND2 33
B
28 27 GND3 34 B
LVDS_A1# 1 R1335 2 LVDS_A01# LVDS_A00 29 28 GND4 35
0_0402_5% LVDS_A00# 30 29 GND5 36
30 GND6
LVDS_A2 1 R1336 2 LVDS_A02 SP010011S00
0_0402_5% STARC_107K30-000001-G2
1
1 2
2 Focaltech Request
WCM-2012HS-900T_0805 2 1
+3VS
4 3 R1030 0_0402_5%
4 3
@ L89 2 @ 1 +TS_LDO
+5VS
R1029 0_0402_5%
LVDS_A2# 1 R1337 2 LVDS_A02# Atmel Request 1 1
For LCD 0_0402_5%
(15,4) GEN2_I2C_SCL 2 1 AP_SMB_SCL
R1425 0_0402_5% LVDS_ACLK 1 R1338 2 LVDS_ACLK0 C1474 C1475
(15,4) GEN2_I2C_SDA 2 1 AP_SMB_SDA 0_0402_5% 1U_0402_10V4Z 2 2 0.1U_0402_10V7K
R1426 0_0402_5%
JP58
C1501
1 2 22P_0402_50V8J 1
1 2 1@ 2 TS_I2C_SCL 2 1
WCM-2012HS-900T_0805 33_0402_5% TS_I2C_SDA 3 2
4 3 1 2 R1388 4 3
4 3 (4) TS_INT# 4
5
@ L90 6 5
(4) TS_RST# 6
7
LVDS_ACLK# 1 R1339 2 LVDS_ACLK0# 1 2 8 7
(4) TS_PWR_EN 8
0_0402_5% @ R1031 33_0402_5%
2
2 9
@ R1308 10 GND
@ C1502 GND
100K_0402_5%
22P_0402_50V8J ACES_50208-00801-003
1
1
A A
(15,4) GEN2_I2C_SCL
2 1 TS_I2C_SCL For TP
R1389 0_0402_5%
2 1 TS_I2C_SDA
(15,4) GEN2_I2C_SDA
R1390 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD PANEL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 15 of 35
5 4 3 2 1
5 4 3 2 1
+VDD_1V8_AUDIO
R168
1 2 VDD_IO_305
0_0402_5% 1 1
C193 C194
1U_0402_10V4Z 0.1U_0402_10V6K
2 2
D D
VDD_DAL_305 +VDD_1V8_AUDIO
1 1
C196 C197
1
1U_0402_10V4Z 0.1U_0402_10V6K
2 2 R167 @
10K_0402_5%
2
R169 U23 +VDD_1V8_AUDIO
1 2 AUDIO_SEL_R 1 10 CODEC_IN
(6) AUDIO_SEL IN1 COM1
0_0402_5% AUDIO_DOUT2 2 9
VDD_P_305 3 NO1 NC1 8
AUDIO_DIN2 4 GND V+ 7
1 1 NO2 NC2 1
2
C198 C199 IN NC to COM NO to COM 5 6 CODEC_OUT C195
COM to NC COM to NO R170 IN2 COM2
1U_0402_10V4Z 0.1U_0402_10V6K 470K_0402_5% TS5A23157RSER_QFN10_2X1P5 0.1U_0402_10V6K
2 2 2
L ON OFF ES305
SA000039100
1
H OFF ON CODEC
R177
AUDIO_DOUT2_R 1 2
AUDIO_DOUT2 (6)
0_0402_5%
R178
AUDIO_DIN2_R 1 2
+VDD_1V8_AUDIO AUDIO_DIN2 (6)
0_0402_5%
R171
1 2
(17) AUDIO_SCLK2_VOICE AUDIO_SCLK2 (6)
0_0402_5%
1
C380 R174
C 0.01U_0402_25V7 1 2 C
(17) AUDIO_FS2_VOICE AUDIO_FS2 (6)
1
1
0_0402_5%
R187 2
@ R184 0_0402_5%
10K_0402_5%
Modify for Acer request
2
2
AUDIO_FS2_VOICE connect to portA and CODEC,
X5
(6) EN_ES305_OSC
R182 1 2 0_0402_5% 1
OE VDD
4 AUDIO_FS2 connect to portB, portC and CPU.
2
GND OUTPUT
3 ES305_CLK_12M AUDIO_SCLK2_VOICE connect to portA and CODEC
2
H OSC out
OPEN OSC out
L High Z Active --> 17 mA
Sleep --> 35 uA 20110823 Modify for Acer request
U24
VDD_IO_305 D6 A2
VDD_IO PORTA_DI CODEC_OUT (17)
VDD_DAL_305 C6 B2 CODEC_IN (17)
VDD_DAL PORTA_DO
B6 A1 AUDIO_SCLK2_VOICE
VDD_DPD PORTA_CLK
VDD_P_305 A6 B1 AUDIO_FS2_VOICE
VDD_P PORTA_FS
R185 1 @ 2 0_0402_5%
(7) CLK_12M_ES305
SW ES305_CLK_12M R186 1
R172 1
2 0_0402_5%
2 0_0402_5%
ES305_CLK_IN
UART_SIN
A4
A3
CLK_IN 12M ~ 16M PORTB_DI
F3 AUDIO_DOUT2_R
F4 R173 2 1 100K_0402_5%
(7) AUDIO_UART4_TX UART_SIN PORTB_DO
B T28PAD @ B
R175 1 2 0_0402_5% UART_SOUT B4 E4 AUDIO_SCLK2
(7) AUDIO_UART4_RX UART_SOUT PORTB_CLK
R176 1 2 0_0402_5% ES305_INT B3 E3 AUDIO_FS2
(6) ES305_INT_R GPIO_A PORTB_FS
T29PAD @
R226 1 2 0_0402_5% ES305_I2C_SDA B5
(17,29,31,33,4,7) PWR_I2C_SDA I2C_DATA
T30PAD @
R246 1 2 0_0402_5% ES305_I2C_SCL C5 F2 AUDIO_DOUT2_R
(17,29,31,33,4,7) PWR_I2C_SCL I2C_CLK PORTC_DI
AUDIO_DIN2 CODEC_OUT
DAP2_DIN C_DO A_DI ADC (6) AUDIO_RST#
R179 1 2 0_0402_5% AUDIO_RST#_R D5
RESET_ low active PORTC_DO
E2 AUDIO_DIN2_R
F5 E1 AUDIO_SCLK2
TEST PORTC_CLK
AUDIO_DOUT2 CODEC_IN
DAP2_DOUT C_DI A_DO DAC +VDD_1V8_AUDIO PORTC_FS
F1 AUDIO_FS2
AUDIO_SCLK2 AUDIO_SCLK2_VOICE
1
DAP2_SCLK C_CLK A_CLK CLK For 24M or 26M
A5
GND_P PORTD_DI
D1
R180 @ E5 C1
10K_0402_5% GND PORTD_DO
GND PORTD_CLK
2
AUDIO_FS2 AUDIO_FS2_VOICE UART_SOUT F6
GND PORTD_FS
D2
1
2
B_CLK D_CLK
A A
B_FS D_FS Support for input clock frequencies of 24 MHz and 26 MHz
requires a 10k pull-up resistor on the UART_SOUT pin.
Audio Block Diagram Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/20 Deciphered Date 2012/01/09 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ES305
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 16 of 35
5 4 3 2 1
5 4 3 2 1
AUDIO_CLK_R AUDIO_SCLK2_VOICE
+VDD_1V8_AUDIO
EN_SPEK +CPVDD +AVDD_CDC
1
R190 @ R191 @
1
0_0402_5% 0_0402_5% 1 1 1 1
300K_0402_1%
C213 C214 C212 C216 Close to U25
1U_0402_10V4Z 1U_0402_10V4Z 1U_0402_10V4Z 1U_0402_10V4Z
2
R457
Close U113.40 2 2 Close U113.39 2 2
C217 R194
2 2 Close U113.10 1 2 2 1
2
1
Close U113.24
C236 C218 C219 0.1U_0402_10V6K 20_0402_5%
33P 50V J NPO 0402 68P_0402_50V8J 68P_0402_50V8J
2
1 1 VDD_1V8_GEN
@ @
C220 R196
1 2 2 1 R157 1 2 200mA
+VDD_1V8_AUDIO
0_0402_5%
0.1U_0402_10V6K 20_0402_5%
D +VDD_1V8_AUDIO D
+VDD_1V8_AUDIO
U25
Audio Codec
39 16 CDC_HP_R CDC_HP_R (18)
L41 40 DCVDD HPOUTR 18 CDC_HP_L
DBVDD HPOUTL CDC_HP_L (18)
L17 1 2 +CPVDD 10 17 R443 10_0402_5%2 @
1 2 FBMA-10-100505-121T_0402 +AVDD_CDC 24 CPVDD HPGND
FBMA-10-100505-121T_0402 AVDD R446 10_0402_5%2
HPGND (18)
R322 1 2 0_0402_5% 37 19 TP38
(16,29,31,33,4,7) PWR_I2C_SCL SCLK LINEOUTR
R256 1 2 0_0402_5% 36 21 TP39
(16,29,31,33,4,7) PWR_I2C_SDA 5 SDIN LINEOUTL 20 R447 10_0402_5%2
(6) CDC_IRQ# INTERRUPT LINEGND
2
(6) AUDIO_CLK_R MCLK
6 22 CDC_LEFT_P
(16) AUDIO_SCLK2_VOICE 8 BCLK LOP 23 CDC_LEFT_N
(16) AUDIO_FS2_VOICE LRC LON 28 CDC_RIGHT_P
7 ROP 27 CDC_RIGHT_N
(16) CODEC_IN DACDAT RON
9
(16) CODEC_OUT ADCDAT 11 CFB1 C223 1 2 2.2U_0402_6.3VM
EN_SPEK 38 CFB1 13 CFB2
GPIO3/ADDR CFB2 +VDD_1V8_AUDIO
(7) SHORT_DET
R430 1 2 0_0402_5% SHORT_DETECT 3
DMIC_DAT/GPIO2 Close to U25
+VDD_1V8_AUDIO_EN 4 29 +MIC_BIAS
DMIC_LR/GPIO1 MICBIAS
COM_MIC R3921 2 1K_0402_5% CDC_COM_MIC C230 1 2 1U_0402_10V6K 32 25 +VMID_CDC
(18) COM_MIC IN1R VMID
1
C231 1 2 1U_0402_10V6K 35 14 +MIC_BIAS +VMID_CDC +VPOS_CDC +VNEG_CDC
IN1L VPOS +VPOS_CDC
2 15 +VNEG_CDC R9
C209 C224 1 2 0.1U_0402_10V6K 31 VNEG 100K_0402_5%
0_0402_5% 2.2K_0402_1% IN2R
AMIC_LEFT+ C225 1 2 1U_0402_10V6K 34 12 C226 1 C227 1 1 1
IN2L CPGND
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
+MIC_BIAS 2 1 1 2 100P_0402_50V8J 26 C228 C229
2
1 C269 1 2 0.1U_0402_10V6K 30 AGND 41
IN3R GNDPAD
2.2U_0402_6.3VM
2.2U_0402_6.3VM
R197 R198 AMIC_LEFT- C258 1 2 1U_0402_10V6K 33 1 HP_IN R28 1 2 HP_DET# (6)
IN3L DGND 2 2 2 2 (18) HP_IN
1K_0402_5%
WM8903LGEFK-RV_QFN40_5X5
4.7U_0402_6.3V6M SA00003MP00 1 C9
0.1U_0402_10V7K
1 2
C
2 C
C202
+VDD_1V8_AUDIO
R151 1 2 0_0402_5%
+VDD_1V8_MIC
NONLDO@
+VDD_1V8_AUDIO_LDO
R165 1 2 0_0402_5%
LDO@ Main MIC
2
C237 R243
620_0402_5%
LDO@
SD028000080
1
C270 1 2
R265 C399 2.2U_0402_6.3VM
0_0402_5% MIC_GND 2 1 1 2 S SUPPRE_ KC FBMA-11-100505-680T 0402
S SUPPRE_ KC FBMA-11-100505-680T 0402
D
1
4.7U_0402_6.3V6M
C2551
C2561
3
2
Vth (Max) = 1.5
C2531 47P_0402_50V8J
C2541 47P_0402_50V8J
C237
C206
R260 R221 1 1 2 2 1 3
G1
3
2 4
620_0402_5% 620_0402_5% 1 1 G2
C207 33P 50V J NPO 0402
47P_0402_50V8J
47P_0402_50V8J
33P 50V J NPO 0402 E&T_3800-E02N-00R
1
2 2 1
AMIC_LEFT+
2 2
D8 SP02000S010
TVNST52302AB0_SOT523-3
AMIC_LEFT-
1
referece to Acer
B
Int. Speaker Conn. SPK1 B
SPKR_LEFT# L20 2 1 FBMA-101_0402 SPK_L# 1
SPKR_LEFT L21 2 1 FBMA-101_0402 SPK_L 2 1
SPKR_RIGHT# L22 2 1 FBMA-101_0402 SPK_R# 3 2 5
SPKR_RIGHT L23 2 1 FBMA-101_0402 SPK_R 4 3 G1 6 2 1 EAR_JACK_GND
4 G2 EAR_JACK_GND (18)
TVNST52302AB0_SOT523-3
R200 0_0402_5%
C240 C241 C242 C243 ACES_88266-04001 @
2 2 2 2 ME@ close to 8903 for psudo differential
2
SP02000SC00
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
D6 D7
TVNST52302AB0_SOT523-3
1 1 1 1
1
+AMP_VDD
0_0603_5% +3VS
+3VS @1 R445
@ 2
1 2
0_0603_5% LDO@ LDO@
+AMP_VDD
U8 LDO@
2 1 +VDD_1V8_AUDIO_EN R449 1 2 0_0402_5% 1 5
C238 10U_0402_6.3V6M @ 2 CE VDD
3 NC 4
GND VOUT +VDD_1V8_AUDIO_LDO
2 1 1 2
C261 10U_0402_6.3V6M C239 1U_0402_10V4Z RP114Q182D-TR-FE_SC-88A5 1 2
LDO@ LDO@
C145 C144
1U_0402_10V4Z 0.1U_0402_10V6K
2 1
B1
B2
B1
B2
1U_0402_10V4Z U2 U5
C250 100K_0402_1% C248 1U_0402_10V4Z 100K_0402_1%
VDD
PVDD
VDD
PVDD
GND
GND
A2
B3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Codec / AMP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 17 of 35
5 4 3 2 1
5 4 3 2 1
Audio Jack
JLINE1 ME@
R1320
7 COM_MIC_JACK_R 2 1 COM_MIC_JACK
5 R1427 0_0402_5% EAR JACK GND_R 1 2 EAR_JACK_GND
EAR_JACK_GND (17)
4 HP_LEFT @
3 HP_IN
D HP_IN (17) 0_0402_5% D
1 HP_RIGHT
2 COM_MIC_JACK
1
6 COM_MIC 1 R1428 2 0_0402_5% R1430
0_0402_5%
@
2
10K_0402_5%
10K_0402_5%
0_0402_5%
COM_MIC (17)
SINGA_2SJ3005-008211 R1429 R1431 2 1 R436
2
2
3
D2 HP_LEFT
1
TVNST52302AB0 SOT523
HP_RIGHT
SCA00001W00
1
2
D1
TVNST52302AB0 SOT523
CLOSE TO JLINE1
SCA00001W00
1
0_0402_5%
2 1 R426
HPGND (17)
R429
@ 0_0402_5% 0_0402_5%
HP_LEFT 2 1 R409 HP_L 2 1
CDC_HP_L (17)
@ 0_0402_5%
HP_RIGHT 2 1 R423 HP_R 2 1
CDC_HP_R (17)
R431
0_0402_5%
C210 C211
100P_0402_50V8J
2 2 C2641 2 C2642 2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
@ @ @ @
C
1 1 1 1 C
L(4) GND(5)
R(1) MIC(7)
+VDD_3V3_GMI_TEGRA
1
+VDD_1V8_BB_TEGRA
B B
R438 @ 1 C1484
0_0402_5% 0.1U_0402_10V7K
1
R1365
2
D29 U146
RB751V-40_SOD323-2 A2 A1
V+ NO2 DEBUG_UART1_TX (7)
DEBUG_UART1_RX 2 1 A3 B1 HP_RIGHT
(7) DEBUG_UART1_RX NO1 COM2
HP_LEFT B3 C1 HP_R
HP_L C3 COM1 NC2 D1
D3 NC1 IN2 D2
(7) UART_SW IN1 GND
TS5A22362YZPR_DSBGA10
IN NC to COM NO to COM
COM to NC COM to NO
SA00005AE00
1
L ON OFF HP
@ R1366
H OFF ON Debug 100K_0402_5%
2
HP Switch
A A
Title
<Title>
GYRO_CLKIN GYRO_FSYNC
V_logic must be <= VDD at all time
1
R253 @ R255 @
10K_0402_5% 10K_0402_5% +VDD_3V3_SENSOR
2
D D
GYRO
U29 H12 H9 H8
HOLEA HOLEA HOLEA H1 H2 H3 H4 H5 H11
GYRO_CLKIN 1 13 C253 1 2 0.1U_0402_10V6K HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
IME_DA 6 CLKIN VDD
IME_CL 7 IME_DA 10 C254 1 2 0.1U_0402_10V6K
1
8 IME_CL REGOUT 11 GYRO_FSYNC R220
+VDD_1V8_SENSOR
1
AD0 9 VLOGIC FSYNC 12 GYRO_INT 1 2
AD0 INT GYRO_INT_R (6)
20 1 2 0_0402_5%
CPOUT 22 C255 2200P_0402_25V7K
1 CLKOUT
1
C256 R224 2
3 NC 23
0.1U_0402_10V6K NC SCL GEN1_I2C_SCL (19,7)
2
10K_0402_5%
4 24 GEN1_I2C_SDA (19,7) H6 H7 FD1 FD2 FD3 FD4
5 NC SDA HOLEA HOLEA 1 1 1 1
2
14 NC 18
15 NC GND
16 NC 19
1
17 NC RESV 21
NC RESV
MPU-3050_QFN24_4X4
+VDD_1V8_SENSOR
350 A
ECOM@ R222
1 ECOM@ 2 C3 C4 2 1
(6) COMPASS_DRDY
1
DRDY VID
350 A
R1404 0_0402_5% B1 2 1
R1414 1ECOM@ 2 0_0402_5% A3 VDD ECOM@ R223
(19,7) GEN1_I2C_SCL SCL/SK 1
1 2 D4 A1 0_0402_5% 1
(19,7) GEN1_I2C_SDA R1412 ECOM@ 0_0402_5% SDA/SI TST1 C2 C2643 CLIP13 CLIP14 CLIP15 CLIP16 CLIP17 CLIP18
B4 TST2 B3 0.1U_0402_10V7K C2644 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
SO TST6 ECOM@ 2 0.1U_0402_10V7K
A2 D1 2 ECOM@
+VDD_ECP CSB# CAD0 D2
1
A4 CAD1
RSV C1
VSS
AK8975C_BGA14 CLIP19 CLIP25
EMIST_SUL-12A2M_1P CLIP21 CLIP22 CLIP23 CLIP24 EMIST_SUL-12A2M_1P
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
B note: IC power trace B
Ecompass
1
1
1
CLIP26 CLIP27 CLIP29 CLIP30 CLIP31 CLIP32
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
1
CLIP33 CLIP34 CLIP35
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GYRO/G-Sen/E-Compass/Clip
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 19 of 35
5 4 3 2 1
5 4 3 2 1
D D
@ Q73
1 3
S
G
2
@ R1573
2 1
+VDD_CAM_1V8
1 Recever
C C2685 @ C
U141 +2.8V_AVDD +2.8V_2M_AVDD_R 10K_0402_5% 0.1U_0402_10V6K
1 2
+3VS VIN
5 2 1
2 VOUT R143
GND
1
0_0402_5% 1
1
C1389 4
2.2U_0603_10V6K 3 NC C1413 C1401
(7) EN_CAM_2V8
2
EN 0.1U_0402_25V6
2
1
4.7U_0402_6.3V6M
2
100K_0402_5%
1
R1369
0_0402_5%
1 2+VDD_CAMIO_1V8
+VDD_CAM_1V8
ACES_88194-2041
2
C1494
1 R1340 2 CSI_CLKB_NN 10P_0402_25V8K 21
(6) 2M_CAM_CLK#_R 22 GND
@ 0_0402_5%
1 GND
1
B 4 3 2 1 B
4 3 3 2
WCM-2012HS-900T_0805 4 3
L91 1 +VDD_CAM_1V8 4
2 1 2 1.3M_AGND 5
1 2 0_0402_5% 6 5
+2.8V_2M_AVDD_R 6
R1152 7
2M_CAM_RST# 8 7
1 R1342 2 (6) 2M_CAM_RST# 9 8
CSI_CLKB_PP CAM_I2C_SDA
(6) 2M_CAM_CLK_R (6) CAM_I2C_SDA 10 9
@ 0_0402_5% 2M_CAM_PWDN
(6) 2M_CAM_PWDN 11 10
CAM_I2C_SCL
1 R1343 2 (6) CAM_I2C_SCL 12 11
CSI_D1B_NN
(6) 2M_CAM_DA1#_R 12
@ 0_0402_5% CAM_MCLK 1 R1341 2 13
(6) CAM_MCLK 13
0_0402_5% 14
CSI_CLKB_NN 15 14
4 3 CSI_CLKB_PP 16 15
4 3 2 16
@ C1476 17
WCM-2012HS-900T_0805 10P_0402_25V8K CSI_D1B_NN 18 17
L92 1 2 CSI_D1B_PP 19 18
1 2 1 20 19
20
JP14
(6) 2M_CAM_DA1_R
1 R1416 2 CSI_D1B_PP SP01001CB10
@ 0_0402_5% 2M connector
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2M CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 20 of 35
5 4 3 2 1
5 4 3 2 1
TVNST52302AB0_SOT523-3
+USB_VOUT_F 2
1
+USB_CLIENT 3
@ D35
R1037 0_0402_5%
1 2 USB1_DN_COMM
@
D16
1 2 2 JP70
(6) USB1_DN 1 2
L24 1 +USB_CLIENT 1
WCM-2012HS-900T_0805 3 VBUS 9
4 3 USB1_DN_COMM 2 GND4 8
(6) USB1_DP 4 3 D- GND3
1
@ R1295 7
100K_0402_5% USB1_DP_COMM 3 CND2 6
PJDLC05C_SOT23-3 D+ GND1
C R1038 1 1 C
1 2 0_0402_5% USB1_DP_COMM C1233 C1234
(6) USB1_ID 4
@ @ ID
2
TP37 0.1U_0402_25V4Z 0.1U_0402_25V4Z 5
2 2 GND
ACON_MUC4A-557700
1
@ R1300
100K_0402_5%
2
USB Port
Micro SD
+VDD_3V_SD
2
0.1U_0402_25V4Z @ R1413 1 2 0_0402_5%
IN OUT 1 1
2
2 1 4 5 C431 C311
R1559 EN# OC# 0.01U_0402_25V7 C312
APL3510DXI-TRG MSOP 8P 1U_0402_10V4Z
1
100K_0402_5% 2 2
D
1
SDMMC_CLK_R
SDMMC_DAT0_R
SDMMC_DAT1_R
SDMMC_DAT2_R
A SDMMC_DAT3_R A
SDMMC_CMD_R
1 1 1 1 1 1
C367 C368 C369 C370 C371 C310
10P_0402_25V8K 10P_0402_25V8K 10P_0402_25V8K 10P_0402_25V8K 10P_0402_25V8K 10P_0402_25V8K
2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB / Micro SD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 21 of 35
5 4 3 2 1
5 4 3 2 1
+5VS
1
R1435
100K_0402_5%
2
SW1
Bottom Side RB751V-40_SOD323-2
2
G
R13 10K_0402_5% 1
Power Button @ 0_0402_5%
2 1R1566 3 1 1
D21
2
(7) HOT_RST#
HOT_RST# 1 2 HOT_RST#_R 2
3
ONKEY# (22,31)
1U_0402_10V4Z
S
D
SW2 TAFG1-12WQR_3P
1
4
NTC325-AA1J-A160C_3P Q72 2N7002KW_SOT323-3
D D
TVNST52302AB0 SOT523
1 C47
2 ONKEY_R#
ONKEY_R# (7) 2
3
2
Ground
1 D11
4
5
6
7
8
3
C2645
0.1U_0402_10V6K D30
2 TVNST52302AB0 SOT523
1
1
VDD_1V8_PMU_VRTC VDD_1V8_PMU_VRTC
1/17 M
1
VDD_5V0_SBY
1
R432 56K_0402_5%
100K_0402_5% R433
2
1
1
power button delay 1 sec circuit HDRST (31)
2
R1562 R1434
D
1
100K_0402_5% @
100K_0402_5% HOT_RST# 2 Q4
2 G BSS138W-7-F_SOT323-3
2
U157 To PMU S
3
1 6
2 MRDLY VCC 5
GND RESET ONKEY# (22,31)
3 4 ONKEY_R#
CD MR
1 1 @ 1 G677L308A31U_ADFN6_1P5x1P5
C2679 C2683
C2680
0.022U_0402_25V7 0.01U_0402_25V7 100P_0402_50V8J
2 2 2
C
Lock SW3
C
2
SS-B70-BK-S100_3P
D31
TVNST52302AB0 SOT523
1
Power LED LED1
White
(27) W_LED_CTL
W_LED_CTL 1 R1405 2 W_LED_CTL_R 5mA 2
R1563
470_0402_1%
1 2 1
(27) O_LED_CTL
O_LED_CTL 1 2 O_LED_CTL_R 5mA 3
VDD_5V0_SBY
R1406
1K_0402_1% 0_0402_5%
Amber
HT-210UD5-BP5_AMBER-WHITE
+3VS_VB
1 1
R316
@ C2646 @ C2647
+3VS_VB
B 1000P_0402_50V7K 1000P_0402_50V7K B
2 1 +3VS
2 2
2 0_0402_5%
C303
VIBRATOR 0.1U_0402_10V6K
1
1
VB1
VCC
KHN4NZ3RB_3P
volume button up / down +3VALW
GND
GND
+3VALW
SW4
2
3
TC303-CA1G-D180T-B SPST H3.5 C2681 +3VALW +3VALW
R317
1
2
0.1U_0402_10V6K
2 1 1 2 VOL_UP#_R 2 1 R1565
VOL_UP# (4,7)
1
R1407 1K_0402_1% 1 R1564 100K_0402_5%
1
0_0402_5%
0_0402_5% R1569 R1570 R1571
3
4
2
1
100K_0402_5% 100K_0402_5% @ 1K_0402_1%
U158
2
10P_0402_25V8K
1 1 6 Q71
2
MRDLY VCC
C2648
2 5 5 4
GND RESET G1 S1 R318
3 4 1 2 +3VALW 3 @
CD MR D1 6 2 1
0.47U_0402_6.3V6K
R1567
2 D2
C2684
2 1
0.47U_0402_6.3V6K
BSS138W-7-F_SOT323-3
100K_0402_5% G2 S2
C2682
1 1 Q20
0_0402_5% D
1
DMN2004DWK-7_SOT363-6
2 2 1
VIB_EN_T30S (4)
G
1
2 2 S R320 0_0402_5%
3
SW5 R321
NTC303-CA1G-D180T-B SPST H3.5 100K_0402_5%
1 2 VOL_DOWN#_R 2 1
VOL_DOWN# (4,7)
2
A R1408 1K_0402_1% A
3
4
2
10P_0402_25V8K
1 D32
C2649
TVNST52302AB0 SOT523
2
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power LED/Lock LED/Ecompass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 22 of 35
5 4 3 2 1
5 4 3 2 1
VDD_1V8_GEN
VDD_PMU_LDO5
2 1 +VDD_1V8_SDMMC4_TEGRA
R390 0_0402_5% +3VS +3VS 1 2
R444 0_0402_5%
1 2 +VDD_1V8_SDMMC3_TEGRA
R395 0_0402_5% 2 1 +VDD_3V3_LCD_TEGRA 1 2 +VDD_3V3_SDMMC1_TEGRA
R418 @ 0_0402_5% @ R442 0_0402_5%
2 1 +VDD_1V8_AUDIO_TEGRA
R397 0_0402_5% 2 1 VDD_PMU_LDO8
+VDD_3V3_GMI_TEGRA
R393 0_0402_5%
1 2 +VDD_1V0_DDR_HS_TEGRA
1 2 +VDD_3V3_DDR_RX_TEGRA R412 0_0402_5%
R419 0_0402_5% VDD_1V35_DDR3_MEM
1 2 +VDD_1V8_CAM_TEGRA J2
R401 0_0402_5% 1 2 +AVDD_3V3_USB_TEGRA 2 1 +VDD_1V35_MEM_TEGRA
R396 0_0402_5% 2 1
1 2 +VDD_1V8_UART_TEGRA JUMP_43X79
D VDD_PMU_LDO6 D
R402 0_0402_5%
1 2 +VDD_1V8_SYS_TEGRA 2 1 +AVDD_1V2_DSI_CSI_TEGRA
R406 0_0402_5% R410 0_0402_5%
1 2 VDD_PMU_LDO7
+VDD_1V8_BB_TEGRA
R404 0_0402_5%
1 2 +AVDD_1V1_PLL_TEGRA
2 1 +VDD_3V3_LCD_TEGRA R411 0_0402_5%
R450 0_0402_5% VDD_PMU_LDO4
2 1 VDD_1V2_RTC_TEGRA
R407 0_0402_5%
VDD_1V8_GEN +VDD_CAM_1V8
Q26
ME2301A-G_SOT23-3
S
3 1
D
1
2
1
SB00000JL00 C33 +3VS +VDD_3V3_FUSE_TEGRA
1U_0402_10V4Z Q33
ME2301A-G_SOT23-3
2 R19
2.2K_0402_1% +3VALW TO +3VS
S
3 1
D
2
D
1
+3VALW +3VS
G
C 1 C
2
2
Q46 VDD_5V0_SBY SB00000JL00 C159 JUMP_43X118
G 1U_0402_10V4Z
S TR DMN3150LW-7 1N SOT-323-3 J3
S @
3
2 1 2
1 2
1
R300
2 1 R326
(7) EN_CAM_1V8#
200K_0402_1%
100K_0402_5% U21 AO4409L_SO8
1
R325 1 8
2
C384 2 1 2 7
0.1U_0402_10V6K 3 6
2
2
10U_0805_10V4Z
C460
10U_0805_10V4Z
C459
100K_0402_5% 1 1 1 5 1 1
10U_0805_10V4Z
C461
1U_0603_10V6K
C458
R380
C389 470_0603_5%
4
Q25B 0.1U_0402_10V6K
5 DMN2004DWK-7_SOT363-6 2 2 2 2 2
(4) EN_T30S_FUSE_3V3
1
3.3V
6
R385
10mil
20mil 2 1 3VS_GATE
VDD_5V0_SBY
510K_0402_5% 2 3VS_GATE
1
3
Q70A
1
C463 DMN66D0LDW-7_SOT363-6
VDD_1V8_GEN +VDD_1V8_SENSOR 0.01U_0603_50V7K
Q35 EN_3V3_SW 5 2
(31) EN_3V3_SW
ME2301A-G_SOT23-3
Q70B
4
S
3 1 DMN66D0LDW-7_SOT363-6
D
R05. Change
G
1
2
SB00000JL00 C160
1U_0402_10V4Z
2 +3VS +VDD_3V3_SENSOR
B B
Q38
ME2301A-G_SOT23-3
S
3 1
D
R330
2 1
(7) EN_SENSOR_1V8#
G
1
2
1
VDD_5V0_SBY SB00000JL00 C163
47K_0402_1% C390 @ 1U_0402_10V4Z
0.1U_0402_10V6K 2
1
2
R414
200K_0402_1%
R415
2
2 1
100K_0402_5% 1
6
C391
Q25A 0.1U_0402_10V6K
@ R427 1 2 0_0402_5% 2 DMN2004DWK-7_SOT363-6 2
(4) EN_SENSOR_3V3
3.3V
1
R424 1 2 0_0402_5%
(7) EN_SENSOR_3V3_2
1.8V
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC interface/Power Button
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 23 of 35
5 4 3 2 1
5 4 3 2 1
+2V8_GPS 1 2
L95
C2662
0.1U_0402_10V7K
BLM15AG601SN1D_2P 1 1
C2663
Antenna 39P 50V J NPO 0402
C313
1/11 M 2 2
GPS@
L35 1 2 BLM15AG601SN1D_2P 1 2
2.2U_0402_6.3V6M
L8 GPS@ 470P_0402_50V7K L96 L9 GPS@ GPS@
SAFFB1G58KB0F0A U154 GPS@ SAFFB1G58KA0F0AR14_5P
H10
C2664
J10
GPSANT 6.8NH_LQG15HN6N8J02D_5% IC BGU7005 L98 U47
K7
K6
1 1 2 1 4 1 2 1 2 3 6 1 4
Vcc
ANT Input Output RFIN RFOUT Input Output 7.5NH +-0.1NH LQP15MN7N5B02D
GPS_VDDIF
VDD1P2_GRF
GPS_VDDPL
GPS_VDDLNA
C315 1 5 GPS_PWRON_R GPS_IN3 1 2GPS_ANT4 K9
SHDN GPS_RFIP
2.7P_0402_50V8C
2 C2668 2 22P_0402_50V8J 1 C2665 2
GND
GND
GND
GND
GND
GND
GND
2.2P_0402_50V8
3 @C2669
@C2669 C2670 1 1 2
GND
GND
D GND D
2.7P_0402_50V8C
0.1U_0402_10V7K
0.1U_0402_10V7K
@ @ C2671
ACES_20262-0001 2 C2666 C2677 @
2
3
5
2
3
5
1 2 1 1P_0402_50V NPO
@ TP40
2
2 2 1
RF
1/31 M Footprint
BCM4751IFBG_FBGA_100P-NH
+GPS_AUX_OUT +1V8_GPS A4
GPS_CAL CLK IF
GPS_CLK_26M_R G10
TCXO B7
1 CAL_REQ
1 C316 GPS_CLK_32K_R K2
0.1U_0402_10V6K 0.01U_0402_25V7 LPO_IN H9
C379 GPS@ F10 NC F9
2 NC NC
GPS@ 2 26MHZ_10PF_TX6214 F8
GPS@ NC
6
4
X2 X3 G9
4 GPS_CLK_26M_R GPS@ NC
VCC
VDD
OUTPUT
1
OE Clock Output
3 GPS_CLK_32K R351 1 GPS@ 2 0_0402_5% GPS_CLK_32K_R SYS IF AUX_HI
K4
C318
2 2 H6 +GPS_AUX_OUT 2 1
ENABLE/DISABLE VDD_AUX_O
5 C139 @ H7 +3V3_GPS
1 NC 1P_0402_50V NPO VDD_AUX_IN 0.22U_0402_6.3V4Z
GND
GND
NC 1 A6
A8 HOST_REQ
GPS_SYNC/PPS_OUT B6
3
2
32.768KHZ_15PF_KK3270032 A7 LNA_EN
IFVALID
C C
R383 1 2 0_0402_5% GPS_RESET#_R A5 A3
(7) GPS_RESET# RST_N C_GPIO_6 B5
R416 1 2 0_0402_5% GPS_PWRON_R J4 C_GPIO_7
(7) GPS_PWRON REGPU A2
H2 D_GPIO_5 H1
TM1 D_GPIO_6 C317
K1
GPS_PWRON_R B3 TM2 J6 GPS_REF_CAP 1 2
TM3 REF_CAP
UART/I2C IF 0.01U_0402_25V7
1
R348 GPS@ D2 GPS@
C1 C_GPIO_2
100K_0402_5% C_GPIO_3 E1 R417 1 2 0_0402_5%
SCL2/UART_TX GPS_UART_RXD (7)
SB00000SM00 D1 R421 1 2 0_0402_5%
GPS_UART_TXD (7)
2
+1V8_GPS SDA2/UART_RX B2 R434 1 2 0_0402_5%
VDD_1V8_GEN UART_nRTS GPS_UART_CTS# (7)
Q28 Acer request UART_nCTS
A1 R435 1 2 0_0402_5%
GPS_UART_RTS# (7)
4 3
MEMORY
2 F2 E5
NC NC
1
5 1 2 1 F7 B1
NC NC
1
C323 H3 E6
GPS@ R303 6 C332 C326 C353 C324 H4 NC NC D4
2
J1 NC NC E7
GPS@ NC NC
G6 C2
G4 NC NC D10 +1V8_GPS
(7) EN_VDD_GPS Vth = 1.5 G1 NC NC B4
NC NC
1
F1 A9
1.8V G5 NC NC A10
NC NC
1
R304 C10 B9
1M_0402_1% C8 NC NC C9 R346
GPS@ D5 NC NC B10 GPS@
2
B NC NC 100K_0402_5% B
2
GPS@ D6 NC NC E4
D9 NC NC E2 GPS_UART_RXD
NC NC
+3V3_GPS J5
VDD_BAT
R428 1 GPS@ 2 VDD_PRE H5 E8
VDD_PRE NC
0_0402_5%
PWR
2.2U_0402_6.3V6M
@ C319 GPS_VDDC E9 J3
G2 VDDIFP AVSS K3
1 1 VDDC AVSS
2.2U_0402_6.3V6M
GPS@ C7
C320 C3 VDDC
VDDC
2 2 K5 G3
VDD1P2_CORE VSSC F4
C6 VSSC B8
VDDIO VSSC
SB00000SM00 +3V3_GPS
D7
VDDIO VSSC
C5
+1V8_GPS F3 D3
+3VS Q29 VDDIO VSSC
4 3 BCM47511IFBG_FBGA100
+3V3_GPS
1/17 Add
5
2 GPS@
SA00004YJ00 U50
1
1 2 1
VIN
1
C330 R305 6
1U_0402_10V4Z 1M_0402_1% 1 C331 C333 C347 1 5 +2V8_GPS
2
+3VS
SB00000SM00 +3VS_WIFI
Q31
4 3
dual-Band wifi RF matching , Reserve " 2 Pi " filter
2
SHI0000FQ00
1
5 1 1 2
1
C337 C342 R375 ACES_20262-0001
1U_0402_10V4Z R308 6 C339 C341 C340
2.4RF_IN_L 1 2 2.4RF_IN_R R387 1 WIFI@2 0_0402_5% 2.4RF_IN 1
2
WIFI@ 1M_0402_1% 1 1U_0402_10V4Z 4.7U_0402_6.3V6M 0.1U_0402_10V6K 68P_0402_50V8J ANT
2
WIFI@ WIFI@ 2 WIFI@ 2 WIFI@ 1
WIFI@ 2 2 2
FDG6331L_SC70-6 1.5P_0402_50V NPO 2
2
WIFI@ C136 @ WIFI@ C137 @ C138 @ 3 GND
1P_0402_50V NPO 1P_0402_50V NPO 1P_0402_50V NPO GND
1 1 1 WIFANT
D D
(25,4) EN_WIFI_VDD Vth = 1.5
1
R307
1M_0402_5%
@
2
SB00000SM00 AH662 use 1U, AH663 use 0.1U
VDD_1V8_GEN +1.8VS_WIFI
Q32
+SR_PA_OUT +VDD_WL_PA Compal ESD request.
4 3 2.4RF_IN
2
2
1
5 C356 C359
2
1
1
1 1 2
1
1U_0402_10V4Z R319 6 NH660@ WIFI@ C2672 @
2
2
FDG6331L_SC70-6 WIFI@ 2 WIFI@ 2 WIFI@ 1
WIFI@
close to H2 close to G9
2
EN_WIFI_VDD
1
C R361 1 @ 2 0_0402_5% C
R93 R94
100K_0402_5% 1K_0402_1% +VDD_CORE
WIFI@ WIFI@ +5VS
2
2
Q47 WIFI@ +VDD1P4_WIFI
Q37
5 4 1
G1 S1 3 VDD
D1 6 5
2 VOUT
EN_WIFI_VDD 2 D2 1 1 1 GND
G2 S2 +1.8VS_WIFI 4
VFB
2
C343 C350 3 1 1
DMN2004DWK-7_SOT363-6 4.7U_0402_6.3V6M 0.1U_0402_10V6K CE R356
2 WIFI@ 2 WIFI@ 2 RP111N331D-TR-FE_SOT23-5
+3VS_WIFI 1P_0402_50V NPO 0_0402_5% C378 C346
WIFI@ WIFI@
C2675 WIFI@ WIFI@ 2 2 WIFI@
C360 0.1U_0402_10V6K
1
1 0.1U_0402_10V6K
2 WIFI@ 1 4.7U_0402_6.3V6M
+CBUCK_OUT
1
+VDD_WL_PA
+VDD_WL_PA
WIFI@ R388 2
C2678
33K_0402_5%
1P_0402_50V NPO
+VDD_LN
C2676 WIFI@
1 2 1P_0402_50V NPO
1
1
FM power
2
(25,4) EN_WIFI_VDD R456 @
1
15K_0402_5%
R389
G9
2
H9
H2
C1
C2
D1
H1
A2
A3
B9
B1
B4
B3
E2
J3
U53 1M_0402_1%
+1.8VS_WIFI WIFI@
SR_PA_OUT
VDDIO_RF
CBUCK_OUT
VDD_LN_OUT
VBAT_IN
VOUT_2P5_OUT
VDD1P2_CLDO_OUT
VOUT_2P5_IN
VDD_LN_IN
VDD_WL_PA_A_MODE
VDD_BT_PA
VDD_WL_PA
VDD_CORE
VIN_LDO
VDDIO
2
A8
WFMMC_CMD_R R367 1 @ 2 100K_0402_5% FM_AUDIO_L A7
FM_AUDIO_R
F1,F2,F3,G2,G3 internal weak pull up resister to VDDIO
WIFI@ R272 A6
1 2 WFMMC_CLK_R G1 ANT_FM_TX A5
(5) WFMMC_CLK SDIO_CLK_SPI_CLK ANT_FM_RX
R373 1 WIFI@ 2 0_0402_5% WFMMC_CMD_R G3
B (5) WFMMC_CMD SDIO_CMD_SPI_DI B
1 0_0402_5% R374 1 WIFI@ 2 0_0402_5% WFMMC_DAT0_R F2 J7 2.4RF_IN_L
(5) WFMMC_DAT0 SDIO_DATA0_SPI_DO ANT_2G4_5G
1
2 SDIO_DATA3_SPI_CS ANT_AUX_EN
D7
BT_I2S_DI D5
BT_I2S_DO
1
08/09 Add C387,C388,R272 for WFMMC_CLK E6 C7 +3VS_WIFI
WL_GPIO_1 BT_I2S_WS
C387&C388 from mount to unmount E4
WL_GPIO_2 BT_I2S_CLK
B6 @ R366
100K_0402_5%
D6
C6 WL_GPIO_5 G4
BT_PCM_SYNC (7)
2
WL_GPIO_6 BT_PCM_SYNC F5
BT_PCM_CLK BT_PCM_CLK (7)
1
R382 1 WIFI@ 2 0_0402_5% WF_RST#_R D2 F4 BT_UART_RXD
(7) WF_RST# WL_SHUTDOWN#_RST# BT_PCM_IN BT_PCM_OUT (7)
TP36 F6 G5 @ R386
(7) WF_WAKE# WL_HOST_WAKE BT_PCM_OUT BT_PCM_IN (7)
100K_0402_5%
TP34 E3
TP35 G7 WL_UART_TX C8
@ PAD T11 BT_WAKEUP (7)
2
WL_UART_RX BT_DEVICE_WAKE B7
C345 WIFI@ 0.01U_0402_25V7 BT_HOST_WAKE @ PAD T12 BT_IRQ# (7)
1 2 C3
+SR_PA_OUT BT_SHUTDOWN# @ PAD T13 BT_PD# (7)
H3 C4 R381 1 WIFI@ 2 0_0402_5%
HSIC_DATA BT_RST# BT_RST# (7)
C344 WIFI@ 4.7U_0402_6.3V6M J2
HSIC_STROBE
1 2
E7 R365 1 WIFI@ 2 0_0402_5%
BT_UART_RTS# BT_UART_CTS# (7)
F7 R370 1 WIFI@ 2 0_0402_5%
BT_UART_CTS# BT_UART_RTS# (7)
R384 1 WIFI@ 2 0_0402_5% RTC_32K_WIFI D3
(7) CLK_32K_OUT RTC_CLK F8 R371 1 WIFI@ 2 0_0402_5%
BT_UART_TXD BT_UART_RXD (7)
E8 R369 1 WIFI@ 2 0_0402_5%
BT_UART_TXD (7)
H8 BT_UART_RXD 8/22 Change BOM structure
D9 NC
C355 WIFI@ NC
+VDD_LN 1 2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U53
4.7U_0402_6.3V6M
8/22 Change BOM structure NH660@
A1
A4
A9
B2
B5
B8
C5
C9
D4
D8
E1
E5
E9
F9
G6
G8
H5
H7
J1
J4
J5
J6
J8
J9
A10
C10
E10
G10
J10
+VDD_CORE 1 2
L40 WIFI@
PK29S003200
+VDD1P4_WIFI
1 2
+CBUCK_OUT
Footprint use AH662 co-lay
C357 WIFI@ 4.7U_0402_6.3V6M
1 2 C336 WIFI@ 2.2UH_VLS252012T-2R2M1R3_1.8A_20%
2 1
10U_0402_6.3V6M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WIFI/BT AH662
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 25 of 35
5 4 3 2 1
5 4 3 2 1
D D
Charger IC
VIN BQ24171
AC=12V
+5VS
RT8243AZQW
B+ SYSTEM
Boost-Buck IC
+3VALW
Battery
2S1P
G920AT24U
C Charge PUMP +5V0_SBY C
Boost IC
TPS51212DSCR
DDR3L PWR RAIL VDD_1V35_DDR3_MEM
TPS6591104A2ZRCR T30L
T30L PWR RAIL CHIP
PMU IC
B B
TPS62361YZHR
T30L PWR RAIL
Boost-Buck IC
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR BLOCK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V0JET(A210)-LA8981P
Date: Wednesday, June 13, 2012 Sheet 26 of 35
5 4 3 2 1
5 4 3 2 1
OVPUVPRangesetting:
##OVPSETvoltageisbetween0.497~1.6V## CHARGER BQ24171 AC Insert or remove --> Wake up T30S
USB Insert or remove --> Wake up T30S
SW to check if Acer USB --> Change charge current to 1A
VDD_1V8_GEN
1
1.6V*(768+100)/100=13.888V
100K_0402_5%
0.497V*(768+100)/100=4.314V PR3
PD2
Setting"OVP13.888V"&"UVP4.314V" VIN PR5
2
2 1 1 2
WAKE_UP_ACIN (7)
Max Rds(on) 16.5mohm 42.2K_0402_1% RB751V-40_SOD323-2
10K_0402_5%
1
PQ3 P3 PQ4
PR6
SI7716ADN-T1-GE3_POWERPAK8-5 SI7716ADN-T1-GE3_POWERPAK8-5 PC11 PC12
P2 1 1 0.01UF_0402_25V7K 0.01UF_0402_25V7K
PR8
2
PD1 SBR3U40P1-7_POWERDI123-2 2 2
1
VIN 2 1 5 3 3 5 1 4 Charge_in
D D
2 3
IF=3A VF=0.5V VR=40V
4
1
0.05_1206_1%
3.3_1206_5% PD4
@
PR11 PC15
1 2 CHARGER_LED#
1 2
2
RB751V-40_SOD323-2
SB000005N00
1
PC18 0.1U_0402_25V6
PC20
1
0.01U_0603_50V7K PC19
D
1
PC16 0.1U_0402_25V6 1 2
2
0.1U_0402_25V6 2
SSM3K7002FU_SC70-3
D
2
6
PQ5A G
2 1@ PR15 2 2.2U_0603_16V6K
BTB_OFF S
BQ24171_ACN
3
2
G
PQ27
499K_0402_1%
S SI1034CX-T1-GE3_SC89-6 PR20
10U_0805_25V6K
0.01UF_0402_25V7K
1
PU2 1M_0201_1%
1
PC22
PC23
PC24
1
1 2 5 2
2
ACN PVCC
0.047U_0402_25V7K 3
PVCC
B+
BQ24171_ACP 6
ACP
19 BATDRV#
BATDRV#
PR22 4.02K_0402_1% PD5
2
1 2 7 2 1
CMSRC PC25 PC26
PR23 4.02K_0402_1% SBR3U40P1-7_POWERDI123-2 0.01UF_0402_25V7K 10U_0603_10V6M
VDD_3V3_BQ24171_VREF
1
1 2 BATT+
PR26 PJ1
8 1 PL3 @
ACDRV SW BQ24171_SW 1 2 1 4 charger_out 1 2
24 2.2UH_PCME051E-2R2MS_3.3A_20% 1 2
SW
BQ24171 internal regulator BQ24171_SRP 2 3 BQ24171_SRN
10U_0603_10V6M
JUMP_43X118
1
267K_0402_1%
1
C 1 2 12 21 BQ24171_BTSTPR30 PC28 C
VREF BTST 0.02_1206_1%
1
PR29
PR28 1 2 1 2
PC27 2.2_0603_5%
PC31
16
PC29
1U_0402_6.3V6K 0.047U_0402_25V7K BQ24171_SRP
2
2
100K_0402_1% 2 SRP 1 2
BQ24171_ISET 13
PR40 49.9K_0402_1% ISET 15 BQ24171_SRN
2 1 BQ24171_ACSET 17 SRN 0.1U_0402_16V4Z
ACSET VDD_3V3_BQ24171_VREF
1
PC34
1U_0603_25V6K PC32 PC33
PR58 2 PR35 1 2 PC35 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D BATT+
2
3
1
68K_0402_1%
1 2 5 1 1 2 2.43K_0402_1% PR37
G PQ10B PR33 P2 1U_0402_16V6K 82K_0402_0.1%
(5) CP_GPIO S 73.2K_0402_1% 3 PD6 BQ24171_AVCC 4 PR39
4
2
10 BQ24171_TS 1 2
TS
1
1
PR42 PR43
0_0402_5%
PR41
768K_0402_1% 0_0402_5%
14 BQ24171_FB 1 2
FB BATT_TEMP (29)
BQ24171_OVPSET 18
2
OVPSET
Charging 0-58C
2
22
VDD_3V3_BQ24171_VREF PGND LNJT103F011-20
BQ24171_ISET
BQ24171_TTC 11
ChargeCurrentsetting: D TTC
3
PQ5B 23
PGND
2
1 2 5 PR45
ICHG=VISET/(20*PR26) (6) BATT_LEARN G 100K_0402_1% @ PR47
PR50 0_0201_5% S SI1034CX-T1-GE3_SC89-6 10K_0201_1% CHARGER_LED# 9 25
<<ACadaptorcharge>>
499_0402_1%
STAT THERMALPAD
2
Vbat=2.1*(1+R27/R37)
2
1
VISET=VREF*[PR34/(PR29+PR34)]
1
PR44
BQ24171RGYR_VQFN24_3P5X5P5 PR48
27.4K_0402_0.1%
=3.3*[29.4/(267+29.4)]=0.327V @ PR49
1 2
VDD_3V3_BQ24171_VREF
1
1
ICHG=0.327/(20*0.01)=1.635A 10K_0402_5%
2
1
@ PR52 0_0201_5%
2 1 PR31
PC36 30K_0402_1%
2
2
1
PR54
TTC_PRECH 2 51K_0402_1%
B Idpm=Vacset/(20*PR8) G 2 PR55 1 White LED B
@ PQ14 S
VDD_3V3_BQ24171_VREF
<<systemoff&standby>>
3
1
O_LED_CTL (22) PQ36A
Vacset=3.3*PR33/(PR28+PR33)=1.395V (4) CHARGER_STAT
IDECT 2 PR53 @
D
6
G
Iin=Vacset/(20*PR8)=1.395A 2
PR57
1
Orange LED 2
0_0402_5%
100K_0201_1% G P2 VDD_3V3_BQ24171_VREF
<<Systemon>> D PQ11A D
S
2
3
1
PR210
1
Vacset=3.3*(PR33//PR40)/(PR28+(PR33//PR40))=0.755V 5 2 PQ13A PQ15 1 2
1
G G 5 1 2 1M_0402_1%
Iin=Vacset/(20*PR8)=0.755A DMN66D0LDW-7_SOT363-6 G PQ13B PR201
CHARGER_LED#
S SDMN66D0LDW-7_SOT363-6 S SI1034CX-T1-GE3_SC89-6 2N7002KW_SOT323-3 226K_0402_1% 1 2
4
4
PC45 1M_0402_1% 100K_0402_1%
8
0.1U_0402_25V6 PU11A PR209
D
3
3
TTCsetting:
P
PD7 + 1 VDECT 5
D O
1
2 1
VDD_3V3_BQ24171_VREF2 2 G
High:Disablechargetimer,allowtermination. -
G
1
2 PR205 LM393DMR2G_MICRO8
1
1
0.022U_0402_25V7K
4
1
PC37
2
1
3 S 0.1U_0402_25V6
Connectcapacitor:Setfastchargetimer.
1M_0402_5%
2.2U_0402_6.3V6M
4.7U_0402_6.3V6M
2
6
PR59
PR60
PC40 @
2
2 (7) WAKEUP_LED
##NVDCmustkeepTTClow## WAKEUP_LED 2 0.1U_0402_25V6
2
BAT54CW_SOT323-3
1
G
PC126
PC127
Terminationcurrentis10%offastcharge. SI1034CX-T1-GE3_SC89-6 S
1
2
PQ10A VDD_5V0_SBY
2
BATT+ BATT+
P2
191K_0402_1%
2
2
806K_0402_1%
Battery OVP protect
PR13
2
100K_0402_1%
1
1
PR21 @ 1
PR27 PD10 @ IDECT BTB_OFF 2 VDD
PR14
LEDstatus: 200K_0402_1%
0.1U_0402_16V4Z
1
RESET/RESET
2
PR214 SBR3U40P1-7_POWERDI123-2 3
150K_0402_1%
100_0402_1% 100_0402_1% GND
2
2 1
PR17
47K_0402_1%
Nocharge:LEDoff
2
8
1
806K_0402_1%
PC21
PQ35A D
2
A 5 PR16 A
Fullycharged:StaticWhiteLED BattOVP:
P
+ 7 1 2 1 2 2 RT9818A-36PV_SOT23-3
1
O
1
G
Charging:StaticOrangeLED
6 20120515 Batt+over8.8V
1
-
G
0.01U_0402_50V7K
DMN66D0LDW-7_SOT363-6
D
Boot:StaticWhiteLED
3
PQ35B
5 2 PR56 1
Wakeup:StaticWhiteLED5sec G
P2 Security Classification Compal Secret Data Compal Electronics, Inc.
1
100K_0402_1% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
L: charge in progress A2 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Picasso M R02
2
H : charge is complete or in sleep mode MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/4/21 Date: Wednesday, June 13, 2012 Sheet 27 of 35
Blink (0.5Hz): fault occur (charge suspend, input over-voltage, timer fault and battery absent)
5 4 3 2 1
5 4 3 2 1
D D
+3VL
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
1
PC55
4.7U_0805_10V6K
2
Typ: 175mA
PR76 PR77
13.7K_0402_1% 30K_0402_1%
1 2 2 1
PR79
TPS51225_B+
PR78 20K_0402_1%
TPS51225_B+ 20K_0402_1% 1 2
2 1
0.1U_0603_25V7K
1 2
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
JUMP_43X118 36K_0402_1%
PC47
1
PC39
PQ19
1
1
PC41
PC42
PC44
PC46
SIS412DN-T1-GE3_POWERPAK8-5 @ PR89 0_0402_5%
5
1 2
+3VL
2
2
5
1
EN_3_5V
PQ20
PU4
CS2
VFB2
VREG3
VFB1
CS1
(28,31,33) EN_3V_5V_SYS PAD
21
4 2 1 6
C EN2 20 EN_3_5V 4 C
PR1400_0402_5% EN1
SPOK 7
PGOOD 19
1
2
3
VCLK SIS412DN-T1-GE3_POWERPAK8-5
3
2
1
LX_3V 8 TPS51225CRUKR_QFN20_3X3
PL4 SW2 18 LX_5V
2.2UH_MMD-06AH-2R2M-X2A_6A_20% PC48 PR83 SW1 PR84 PC49 PL5
2 1 2 12 1BST_3V 9 0_0603_5% 0.1U_0603_25V7K 2.2UH_MMD-06AH-2R2M-X2A_6A_20% +5VS
+3VALW 0_0603_5% VBST2 17 1
BST_5V 2 1 2 1 2
VBST1
5
0.1U_0603_25V7K
1
1
4.7_1206_5%
4.7_1206_5%
UG_3V 10
DRVH2
5
PR85
PR86
16 UG_5V
VREG5
DRVL2
DRVL1
DRVH1
VO1
VIN
PQ21
1 4 1 PC53
2
2
PC50 SI7716ADN-T1-GE3_POWERPAK8-5
11
12
13
14
15
150U_B2_6.3VM_R45M + 4 +
1
1
680P_0402_50V7K
680P_0402_50V7K
PC51
150U_B2_6.3VM_R45M
Rds(on)=13.5-16.5m ohm
PC52
PQ22
1
2
3
2 SI7716ADN-T1-GE3_POWERPAK8-5 2
2
2
3
2
1
LG_3V LG_5V
+5VS
TPS51225_B+ Rds(on)=13.5-16.5m ohm
Typ: 225mA
VL
B PC56 B
(28,31,33) EN_3V_5V_SYS 1 2
1M_0402_1%
1
PR66
4.7U_0805_10V6K
1
0_0402_5% PQ18
PR63 5
0_0402_5% PR65
3 2 1 VIN1
2
2 6
<1>5V=300KHz 3V=355KHz
SI1555DL-T1-GE3 SOT363-6
1
<1> +3.3VALWP Ipeak=1.206A ; Imax=0.8442A F=355K Hz <1> +5VS Ipeak=3.0A ; Imax=2.1A F=300K Hz
0.1U_0402_16V4Z
0_0402_5%
1
20120515
PC38
VIN1
Iocp=Vtrip/(Rds(on)*1.2)+(1/(2*L*f)*(Vin-Vout)*Vout/Vin) Iocp=Vtrip/(Rds(on)*1.2)+(1/(2*L*f)*(Vin-Vout)*Vout/Vin)
Iocp_min= Iocp_min=
VDD_5V0_SBY 3.363m/(16.5m*1.2)+(1/(2*2.2u*355K)*(8.4-3.3)*3.3/8.4) 41.5m/(16.5m*1.2)+(1/(2*2.2u*300K)*(8.4-5)*5/8.4)
=0.170+1.283=1.453A =2.096+1.533=3.629A
Iocp_max= Iocp_max=
1
2
3.363m/(13.5m*1.2)+(1/(2*2.2u*355K)*(8.4-3.3)*3.3/8.4) 41.5m/(13.5m*1.2)+(1/(2*2.2u*300K)*(8.4-5)*5/8.4)
0_0402_5%
0_0402_5%
A A
PR68
@
PR32
@ PR67
EN_3V_5V_SYS#
D
3
D
6
PQ37B
2 5 EN_3V_5V_SYS#
Security Classification Compal Secret Data Compal Electronics, Inc.
G G Issued Date 2011/06/13 2012/06/13 Title
Deciphered Date
(28,31,33) EN_3V_5V_SYS
S S
DMN66D0LDW-7_SOT363-6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DMN66D0LDW-7_SOT363-6 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Thor 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 13, 2012 Sheet 28 of 35
5 4 3 2 1
5 4 3 2 1
SP02000I600 BATT+
PL1
D D
@PJP2
@PJP2 FBMA-L11-160808-301LMA20T
1 1 2
1 2
2 3
3 4
4
1000P_0402_50V7K
33P_0402_50V8J
5 PR2 0_0402_5%
5
2200P_0402_50V7K
0.033U_0402_16V7K
8 6 2 1
0.01UF_0402_25V7K
G1 6 PWR_I2C_SDA (16,17,31,33,4,7)
1
9 7
G2 7
1
PC1
PC2
PC3
PR1 0_0402_5%
PC4
PC5
ACES_88231-07001 1 2
PWR_I2C_SCL (16,17,31,33,4,7)
2
BATT_TEMP (27)
VIN
SPARK_79X118
DC_IN
@PJP3
@PJP3 PSG1 @
C 1 1 PL2 C
1 2 HCB2012KF-121T50_0805
2 3 1 2
3 4
4 5
GND 6
GND
1000P_0603_50V7K
1000P_0603_50V7K
1000P_0603_50V7K
1000P_0603_50V7K
1
ACES_88266-04001 PC6
1
2
PC7
PC8
PC9
PC10
0.01U_0603_50V7K
2
2 1
VIN
PD9
LL4148_LL34-2
G922T11U_SOT23-5
2 1 1 2 1 PD14
BATT+ IN 5 2 1
OUT VDD_5V0_SBY
PD8 PR212 2
GND
1
0.01U_0402_50V7K
LL4148_LL34-2 200_0805_5% 4 RB751V-40_SOD323-2
ADJ
1
3
EN 887K_0402_1%
PC14
PR4 PR7
PU9
2
1
1 2
2
1
1
PC211
1U_0805_25V6K PC13 PC212
2
2
1
B B
267K_0402_1%
PR9
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC IN/BATT IN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Thor
Date: Wednesday, June 13, 2012 Sheet 29 of 35
5 4 3 2 1
5 4 3 2 1
+3VALW
1
PR93
10K_0402_5% PJ3
+1.35VSP_B+ 1 2
1 2 B+
2
PR94 JUMP_43X79
0_0402_5%
5
2 1 PQ24
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PGOOD_1.5V SIS412DN-T1-GE3_POWERPAK8-5
2200P_0402_50V7K
0.1U_0402_25V6
D D
1
PC59
PC60
PC61
PC62
4
2
PR95 PC63
3
2
1
PU5 0_0603_5% 0.1U_0603_25V7K
PR96 1 10 BST_+1.35VSP 1 2 1 2
30K_0402_1% PGOOD VBST
PR97 2 1 TRIP_+1.35VSP 2 9 UG_+1.35VSP PL6
0_0402_5% TRIP DRVH 2.2UH_MMD-06AH-2R2M-X2A_6A_20% VDD_1V35_DDR3_MEM
1 2 EN_+1.35VSP 3 8 SW_+1.35VSP 1 2
(31) EN_DDR_BUCK EN SW
+5VS
5
FB_+1.35VSP 4 7
@ PC64 VFB V5IN
1
0.1U_0402_16V7K RF_+1.35VSP 5 6 LG_+1.35VSP 1
2
TST DRVL
1
11 PR98 + PC66
TP PC65 4 4.7_1206_5% 220U_B2_2.5VM_R35
PR99 TPS51212DSCR_SON10_3X3 1U_0402_10V6K
2
470K_0402_1% PQ25 2
SI7716ADN-T1-GE3_POWERPAK8-5
1
PC67
3
2
1
680P_0402_50V7K
Rds=13.5m(Typ)
2
C 16.5m(Max) C
PR100
VFB=0.7V 9.31K_0402_1%
2 1
1
VFB= 0.704V
PR101
10K_0402_1% Vo=VFB*(1+PR100/PR101)= 1.35V
Freq= 266~314KHz , 290KHz(typ)
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR Regualtor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Thor 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 13, 2012 Sheet 30 of 35
5 4 3 2 1
5 4 3 2 1
PMU-TPS65911 1/3 b.
c.
d.
e.
GP2:
GP6:
GP7:
GP8:
EN_SOC
EN_3V3_SYS
EN_DDR (Optional on Cardhu S since we are using VDD2 for memory)
EN_5V0
22P_0402_50V8J
22P_0402_50V8J
F8 PMU_OSC32KIN
OSC32KIN
100K_0402_1%
100K_0402_1%
100K_0402_1%
100K_0402_1%
100K_0402_1%
PR103 1 2 0_0402_5% M5
(16,17,29,33,4,7) PWR_I2C_SDA SDA
1
PC68
PC69
D D
2
PR106 1 2 0_0402_5% M7
(7) CPU_PWR_REQ
2
EN1
PR136 1 2 10K_0402_5% M6 L5
VDD_1V8_GEN EN2 GPIO0 EN_3V_5V_SYS (28,33)
VDD_1V8_GEN L4
GPIO7 EN_DDR_BUCK (30)
K5
GPIO8 EN_5V0_SYS
1
PR107
10K_0402_5% PR108 1 2 0_0402_5% F1
(6,7) CORE_PWR_REQ SLEEP L2
GPIO2 EN_VDD_SOC (33)
G3
EN_3V3_SW (23)
2
GPIO6
L3
(7) PMU_INT# INT1
F6
@ GPIO1
PR213
B7
1 2 POWERHOLD N1 GPIO3 TP3
VDD_1V8_GEN PWRHOLD PAD
PR111 33_0402_1%
0_0402_5% PR112 0_0402_5% F4 1 2
CLK32KOUT PMU_CLK_32K (7)
1 2 N2
(7) AP_OVERHEAT# PWRDN
TP4 PAD
HDRST L6 PR113 0_0402_5%
(22) HDRST HDRST H4 1 2
NRESPWRON PMU_RESET_OUT_1V8# (7)
C7
NRESPWRON2 TP5 PAD 1 2 VDD_1V8_GEN
C C
@ PR114 100K_0402_5%
D7 PMU_VBACKUP
VBACKUP
1
PC70
1U_0402_6.3V6K
VDD_1V8_GEN
2
PR137 0_0402_5%
1 2 H7
GPIO4
PR138 0_0402_5%
1 2 G6 N7
GPIO5 VDDIO
VDD_5V0_SBY
1
PC71 VDD_5V0_SBY
4.7U_0402_6.3V6M
2
B6
VCC7
1
VDD_1V8_PMU_VRTC
PR116
(22) ONKEY#
PR115 1 2 0_0402_5% PMU_ONKEY# E4
PWRON
PC72
4.7U_0402_6.3V6M
Always on
2
2 1 1.8V
0_0402_5% 0.05A
1
10MIL
1
B5
@ PR117 PC73 VDD_1V8_PMU_VRTC VRTC
1
0_0402_5% 1U_0402_6.3V6K PMU_VCCS E8
VDD_0V85_PMU_VREF
2
VCCS PC74
2
2.2U_0402_6.3V6M
2
2
0 = Hardcode 0.85V
PR118
B B
0_0402_5% 1 = EEPROM G8
10MIL 0.05A
VREF
1
PMU_BOOT1 J5
BOOT1
1
PC75
2
0.1U_0402_25V6
2
@ PR139
0_0402_5% G7
REFGND
1
B8
TESTV
B+ D6
E6 AGND1
E5 AGND2
F5 AGND3
412K_0402_1% G4 AGND4
2
AGND5
2
@ H6
PR134 J3 AGND6
PR146 AGND7
100K_0402_1% @ J4
J6 AGND8
K3 AGND9
1
AGND10
1
H5
PMU_VCCS AGND11
M8
D AGND21
1
PQ12 N8
AGND22
2
G @ A1
B1 DGND1
2N7002KW_SOT323-3 DGND2
S B2
DGND3
3
TPS6591104A2ZRCR_BGA98
2
PR141 @
A 442K_0402_1% A
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PMU part1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Thor
Date: Wednesday, June 13, 2012 Sheet 31 of 35
5 4 3 2 1
5 4 3 2 1
Note: LDO1 & LDO2 need 4.7uF cap according to TI on July 6th
PMU-TPS65911 2/3
Compal P/N: SA000056800 S IC TPS6591104A2ZRCR BGA 98P PMU
D D
1.05V 1.2V
PU6B
0.5A 0.2A
VDD_PMU_LDO1 VDD_PMU_LDO2
N5 N6 VDD_PMU_LDO1
VDD_1V8_GEN VCC6 LDO1
N4 VDD_PMU_LDO2
30MIL
LDO2
1
PC76
4.7U_0402_6.3V6M
1
PC77 PC78
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
2
1.2V 1.2V
0.2A 0.1A
30MIL VDD_PMU_LDO3 VDD_PMU_LDO4
D8 E7 VDD_PMU_LDO3
+3VALW VCC5 LDO3
C8 VDD_PMU_LDO4
20MIL
LDO4
1
PC79
4.7U_0402_6.3V6M
1
PC80 PC81
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
C C
3.3V
30MIL PR119 0.2A
0_0402_5%
L1 20MIL VDD_PMU_LDO5
+5VS VCC4 K1 1 2
LDO5
5V
1
0.2A
1
PC82
4.7U_0402_6.3V6M PC83
2
2.2U_0402_6.3V6M
2
1.2V 1.2V 1.0V
0.1A 0.05A 0.02A
10MIL VDD_PMU_LDO6 VDD_PMU_LDO7 VDD_PMU_LDO8
N3 M2 VDD_PMU_LDO6
B VDD_1V8_GEN VCC3 LDO6 B
M3 VDD_PMU_LDO7
10MIL
LDO7
1
PC84
4.7U_0402_6.3V6M M1 VDD_PMU_LDO8
2
LDO8
1
PC85 PC86 PC87
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
TPS6591104A2ZRCR_BGA98
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PMU part2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Thor
Date: Wednesday, June 13, 2012 Sheet 32 of 35
5 4 3 2 1
5 4 3 2 1
+3VALW
FOR VDD_1V2_CORE_TEGRA
1
(28,31,33) EN_3V_5V_SYS
PC89
0.1U_0402_25V6 VDD_1V2_SOC
VDD_1V8_GEN
2
1
1
2 PU7
PL7
@ PR135 @ PR121
100K_0402_5% A4 B3 1
TPS62361_SW 2
VIN SW
0.1U_0402_25V6
100K_0402_5% A1 B4 2.2UH_PCMB041B-2R2MS_2.75A_20%
AVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
B2
(31) EN_VDD_SOC EN
PC90
PC91
PC92
PC94
VDD_CORE_SENSE (8)
PC93
PU6C D1 B1
VDD_1V8_GEN
2
D +3VALW PC95 PR122 0_0402_5% VDD SENSE+ 2 D
20MIL PWR_I2C_SDA (16,17,29,31,4,7)
1
E1 D2 1 2 D2 C1 GND_CORE_SENSE (8)
VCCA1 SWA1 D1 0.1U_0402_25V6 1 2 D3 SDA SENSE -
SWA2 SCL
10U_0603_6.3V6M
0.1U_0402_25V6
F2 E2
PWR_I2C_SCL (16,17,29,31,4,7)
2
VCCA2 SWA3 PR123 0_0402_5% C2
VSEL0 Close to CPU
1
1
PC96
PC99
F3 2 1 A3 D4
VCCA3 +3VALW VSEL1 PGND C3
PR120 A2 PGND C4
2
AGND PGND
C2
100K_0402_5%
2 1
Ipeak =2.5A( 6us)
TPS62361YZHR_XBGA16
GNDSWA1
GNDSWA2
C1
(28,31,33) EN_3V_5V_SYS
Imax = 1.8A(60us) sustained
D3 @ PR131
GNDSWA3 100K_0402_5%
D4
VFB1
TPS62361B
TPS62361YZHR_XBGA16
+3VALW @ 2.2UH_VLS252012T-2R2M1R3_1.8A_20%
50MIL PL8 50MIL
30MIL G2 H2 1 2
VCCBB1 SWB1 VDD_1V2_MEM
1.2V 2A
10U_0603_6.3V6M
0.1U_0402_25V6
G1 H1 1.2V
VCCB2 SWB2
1
1
PC97
PC98
2A
10U_0603_6.3V6M
0.1U_0402_25V6
1
1
2
@ PC100
@ PC101
@ PR124
0_0402_5%
J2
2
GNDSWB1 2
2
J1 50OHM_NETCLASS1
GNDSWB2
C K2 PMU_VFB2 C
VFB2
VL
PC102
A5
V5IN A2 PMU_VBST 1 2 B+
VBST
1U_0402_16V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
1 0.1U_0402_25V6
1
1
PC103
PC104
PC105
PC106
1
PC107
PR125
2
2
2
A3 PMU_DRVH 1 2 PMU_DRVH_R 2
DRVH PMU_DRVH_R
0_0402_5% Tj<90 degree ==>6.1A
Tj<70 degree ==>5.1A
1
1V
D1
D1
D1
G1
PL9 8A
2.2UH_MMD-06AH-2R2M-X2A_6A_20% 200MIL
A4 PMU_SW 10 9 PMU_SW 1 2
SW D1 D2/S1 VDD_1V0_GEN
Change C_B3 footprint
1000P_0603_50V7
G2
S2
S2
S2
1
330U_B2_2VM_R15M
PC115
0.1U_0402_25V6
FDMC7200_POWER33-8-10 1
8
PQ26 1
2
PC108
PC109
@
A6 PMU_DRVL
DRVL
1
1
PMU_DRVL
0.1U_0402_25V6
1
@ PR132 @ PR126 2 2
1_0603_5% 0_0402_5% PC216
2
2
2
B B
B4 PMU_VOUT
VOUT
PC110
PR129 100_0402_1%
C5 1 2 1 2 VDD_CPU_SENSE (8)
VFB
@ PR130 0_0402_5%
330P_0402_50V7K 50OHM_NETCLASS1 1 2 GND_CPU_SENSE (8)
+3VALW
2.2UH_VLS252012T-2R2M1R3_1.8A_20%
L8 PL10 50MIL
VCCIO1 K8 PMU_SWIO 1 2
SWIO1 VDD_1V8_GEN
10U_0603_6.3V6M
0.1U_0402_25V6
L7
VCCIO2 K7
1 SWIO2 1.8V
1
PC111
PC112
10U_0603_6.3V6M
0.1U_0402_25V6
2A
1
1
2
2
PC113
PC114
PR128
A J7 0_0402_5% A
GNDIO1
2
J8 2
2
GNDIO2
50OHM_NETCLASS1
H8
VFBIO