U

nR
eg
is
te
re
6-1 d
 ADC Module
u Sensors normally generate analog voltages
between 0-3 V; proportional to signal strength
strength..
D * (V REF + - V REF - )

d
Vin = + V REF -

re
(2 - 1)
n

te
u Where,

is
VREF+ & VREF REF-- = Reference voltage to limit analog
voltage range
range;;

eg
Vin=Input Voltage
Voltage;;
nR
D= corresponding Digital voltage
voltage;;
N= no
no.. of bits in D
D..
U

u Any input voltage beyond reference voltages

will deliver a saturated number
number..
6-2
 2812 ADC Module
u With 2812 core, VREF+ = 3.0V; and VREF REF-- = 0V,
Thus;;
Thus
D * 3.0V
Vin =

d
4095

re
u 2812 is equipped with 16 dedicated input pins

te
to measure analog voltage
voltage..

is
u These 16 channels are multiplexed internally

eg
implying sequential processing
processing;;
u It is obligatory that during the process of
nR
conversion input should remain constant constant;;
forcing the use of S/H circuits
circuits..
U

u Two S/H circuits can be used in parallel, hence

02 inputs can be converted simultaneously
simultaneously..
u For 12 bit ADC of 2812 the analog resolution is
0.732
732mV
mV per bit
bit.. 6-3
 2812 ADC Module
u We have two s&h units, they can be used in
parallel (simultaneous sampling).
u Each sample and hold is connected to 8

d
multiplexed input lines.

re
u The auto sequencer is a programmable state

te
machine and is able to automatically convert up

is
to 16 input signals.

eg
u Each state of the auto sequencer puts a
measurement into its own result register.
nR
u The fastest conversion time is 80ns per sample in
U

a sequence and 160ns for the very first sample.

u Assuming an input voltage range from 0...+3V
we get a voltage resolution of
3.0V/4095 = 0.732mV per bit. 6-4
 2812 ADC Module
u 12-bit resolution ADC core
u 16 analog inputs (range of 0 to 3V)
u 02 analog input multiplexers

d
re
w Up to 8 analog input channels each

te
u 02 sample/hold units (for each input mux)

is
u Sequential and simultaneous sampling modes

eg
u Auto sequencing capability - up to 16 auto conversions
w 02 independent 8-state sequencers
nR
w Dual-sequencer mode
U

w Cascaded mode
u 16 individually addressable result registers
u Multiple trigger sources for start-of-conversion
w External trigger, S/W, and Event Manager events 6-5
 ADC Module Block Diagram (Cascaded Mode)
Analog MUX
ADCINA0
ADCINA1 Result MUX
MUX S/H
RESULT0
...
A A

d
ADCINA7 RESULT1
S/H 12-bit A/D
12-

re
RESULT2
MUX Converter

...
ADCINB0
ADCINB1 MUX Result

te
S/H
SOC EOC
...

B B Select RESULT15

is
ADCINB7 Auto sequencer

eg
MAX_CONV1
CHSEL00 (state 0)
nR
CHSEL01 (state 1)
CHSEL02 (state 2)
Software CHSEL03 (state 3)
EVA
U

...
EVB
Ext Pin (ADCSOC) CHSEL15 (state 15)
Start Sequence
Trigger

6-6
 Word About Cascaded Mode
u One Auto sequencer
w controls flow of conversion
conversion..

d
u Before SOC, one has to specify
specify::

re
te
w No. of Conversions (Max_Conv
No. (Max_Conv11)

is
w Which I/p line is to be connected in which
stage
w
eg
Results to be buffered in individual state
nR
register..
register
u There are 02 options
options::
U

w Simultaneous;
w Sequential 6-7
 Word About Cascaded Mode

u Simultaneous: Both S/H are used in parallel (02

input lines with same input code e.g. ADCINA
ADCINA33 and
ADCINB33 are converted at the same time by state
ADCINB

d
re
CHSEL00
CHSEL 00)).

te
u Sequential: Input lines can be connected to any of
the states of auto sequencer
sequencer..

is
eg
u Triggering Conversion Sequence:
w By S/W start
start;; by setting a particular bit
bit;;
nR
w By an external pin ADCSOC
ADCSOC;;
U

w By EVA or EVB
u An ADC Interrupt can be used after the end of sequence
to read out result register block.
6-8
 ADC Module Block Diagram (Dual
(Dual--Sequencer mode)
Analog MUX
Result MUX
ADCINA0
ADCINA1 S/H RESULT0
MUX
...
A A RESULT1
12-bit A/D
12-

...
ADCINA7

d
S/H Result
Converter
MUX Select

re
ADCINB0 RESULT7
Sequencer
ADCINB1 MUX S/H Arbiter

te
...

B B SOC1/ SOC2/
RESULT8
EOC1 EOC2 RESULT9
ADCINB7

is

...
SEQ1 SEQ2 Result

eg
Auto sequencer Auto sequencer Select RESULT15
MAX_CONV1 MAX_CONV2
nR
CHSEL00 (state 0) CHSEL08 (state 8)
CHSEL01 (state 1) CHSEL09 (state 9)
U

CHSEL02 (state 2) CHSEL10 (state 10)

Software

...
...

Software
EVA
EVB
Ext Pin CHSEL07 (state 7) CHSEL15 (state 15)
(ADCSOC) Start Sequence Start Sequence
Trigger Trigger
6-9
 Word About Dual Sequencer Mode
u Two sequencers
w Splits into 02 independent machines (SEQ
(SEQ11 & SEQ
SEQ22).

d
w Uses EVA as H/W trigger for SEQ SEQ11;

re
w Uses EVB as H/W trigger for SEQ SEQ22;

te
w To code I/P channels for individual states of 02
sequencers;; user is free to use any of 16 inputs for
sequencers

is
any of 2x8 states
states..

eg
w Result00 to Result
Result Result77 gives O/P for SEQ
SEQ11;
nR
w Result88 to Result
Result Result1515 gives O/P for SEQ
SEQ22
u The reason for this split mode to have 02
U

independent ADCs triggered by their own

hardware timer events
events::
w GP TIMER 1&2 for SEQ
SEQ11;
w GP TIMER 3&4 for SEQ
SEQ22; 6 - 10
Word About Dual Sequencer Mode

Sequence Arbiters
In case of simultaneous start of

d
re
SEQ1 and SEQ2, the SEQ1 has

te
higher priority and the start of

is
SEQ2 will be delayed after the
eg
end of SEQ1.
nR
U

6 - 11
 F2812 ADC Clocking Example
CLKIN PLLCR SYSCLKOUT HISPCP HSPCLK
(30 MHz) DIV (150 MHz) HSPCLK (150 MHz)
bits To CPU
bits

d
1010b 000b

re
PCLKCR.ADCENCLK = 1

te
ADCTRL3 ADCTRL1

is
FCLK ADCCLK
ADCCLKPS (25 MHz)

eg
(25 MHz) To ADC
CPS bit pipeline
bits
ADCTRL1
nR
0011b 0b sampling
ACQ_PS window
FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK =
U

FCLK/(CPS+1) bits
0111b
sampling window = (ACQ_PS + 1)*(1/ADCCLK)

Important: ADCCLK can be a maximum of 25 MHz!

6 - 12
 About ADC Clock
u There are 03 limitations for the set-up of the
ADC conversion time:
(i) the basic clock source for the ADC is the internal

d
clock HSPCLK (derived from the external

re
oscillator, multiplied by PLLCR and divided by
HISPCP).

te
(ii) The ADC clock known as FCLK is limited to

is
25MHz. (To adjust this clock we have to initialise the bit

eg
field ADCCLKPS accordingly. Bit CPS gives the option
for another divider by 2. The clock ADCCLK is the time
base for the internal processing pipeline of the ADC).
nR
(iii) The sampling window ACQ_PS. This group of
bits defines the length of the window that is used
U

between the multiplexer switch and the time when

we sample (or freeze) the input voltage. This
time depends on the line impedance of the input
signal.
6 - 13
 Analog--to
Analog to--Digital Converter Registers
Register Address Description
ADCTRL1 0x007100 ADC Control Register 1
ADCTRL2 0x007101 ADC Control Register 2
ADCMAXCONV 0x007102 ADC Maximum Conversion Channels Register

d
ADCCHSELSEQ1 0x007103 ADC Channel Select Sequencing Control Register 1

re
ADCCHSELSEQ2 0x007104 ADC Channel Select Sequencing Control Register 2

te
ADCCHSELSEQ3 0x007105 ADC Channel Select Sequencing Control Register 3

is
ADCCHSELSEQ4 0x007106 ADC Channel Select Sequencing Control Register 4
ADCASEQSR 0x007107 ADC Auto sequence Status Register

eg
ADCRESULT0 0x007108 ADC Conversion Result Buffer Register 0
nR
ADCRESULT1 0x007109 ADC Conversion Result Buffer Register 1
ADCRESULT2 0x00710A ADC Conversion Result Buffer Register 2
: : : : : : : : :
U

ADCRESULT14 0x007116 ADC Conversion Result Buffer Register 14

ADCRESULT15 0x007117 ADC Conversion Result Buffer Register 15
ADCTRL3 0x007118 ADC Control Register 3
ADCST 0x007119 ADC Status and Flag Register 6 - 14
 ADC Control Register 1 - Upper Byte
ADCTRL1 @ 0x007100

ADC Module Reset Acquisition Time Prescale (S/H)

d
0 = no effect Value = (binary+1)

re
1 = reset (set back to 0 * Time dependent on the Conversion
by ADC logic) Clock Prescale bit (Bit 7 CPS)

te
is
15 14 13 12 11 10 9 8

eg
reserved RESET SUSMOD1 SUSMOD0 ACQ_PS3 ACQ_PS2 ACQ_PS1 ACQ_PS0
nR
Emulation Suspend Mode
00 = [Mode 0] free run (do not stop)
01 = [Mode 1] stop after current sequence
U

10 = [Mode 2] stop after current conversion

11 = [Mode 3] stop immediately

6 - 15
 ADC Control Register 1 - Lower Byte
ADCTRL1 @ 0x007100

Continuous Run Sequencer Mode

0 = stops after reaching 0 = dual mode

d
end of sequence 1 = cascaded mode

re
1 = continuous (starts all over
again from initial state)

te
is
7 6 5 4 3 2 1 0

eg
CPS CONT_RUN nR SEQ1_OVRD SEQ_CASC reserved reserved reserved reserved

Conversion Prescale Sequencer Override

0 = CLK / 1 (continuous run mode)
U

1 = CLK / 2 0 = sequencer pointer resets to initial state

at end of MAX_CONVn
1 = sequencer pointer resets to initial state
after end state

6 - 16
 ADC Control Register 2 - Upper Byte
ADCTRL2 @ 0x007101

EVB SOC EVA SOC

(cascaded mode only) SEQ1 Mask Bit
0 = no action 0 = cannot be started

d
1 = start by EVB by EVA trigger
signal Start Conversion (SEQ1)

re
1 = can be started
0 = clear pending SOC trigger
by EVA trigger
1 = software trigger-
trigger-start SEQ1

te
is
15 14 13 12 11 10 9 8

eg
EVB_SOC INT_ENA_ INT_MOD EVA_SOC_
RST_SEQ1 SOC_SEQ1 reserved reserved SEQ1
_SEQ SEQ1 _SEQ1
nR
Interrupt Enable (SEQ1)
U

Reset SEQ1
0 = no action
1 = immediate reset
SEQ1 to initial state
0 = interrupt disable
1 = interrupt enable Interrupt Mode (SEQ1)
0 = interrupt every EOS
1 = interrupt every other EOS
6 - 17
 ADC Control Register 2 - Lower Byte
ADCTRL2 @ 0x007101
External SOC (SEQ1) EVB SOC
0 = no action SEQ2 Mask bit
1 = start by signal 0 = cannot be started

d
from ADCSOC pin by EVB trigger

re
Start Conversion (SEQ2) 1 = can be started
(dual--sequencer mode only)
(dual by EVB trigger

te
0 = clear pending SOC trigger
1 = software trigger-
trigger-start SEQ2

is
7 6 5 4 3 2 1 0

eg
EXT_SOC INT_ENA_ INT_MOD EVB_SOC_
RST_SEQ2 SOC_SEQ2 reserved reserved
_SEQ1 SEQ2 _SEQ2 SEQ2
nR
Reset SEQ2 Interrupt Enable (SEQ2)
U

0 = no action 0 = interrupt disable

1 = immediate reset 1 = interrupt enable Interrupt Mode (SEQ2)
SEQ2 to initial state 0 = interrupt every EOS
1 = interrupt every other EOS
6 - 18
 Word about ADCCTRL2
u The upper half of register ADCTRL2 is
responsible to control the operating mode
of sequencer 1.

d
re
u The lower byte of ADCTRL2 is similar to

te
its upper half: it controls sequencer SEQ2.

is
u Bit 7 flags the event that the external pin

eg
ADCSOC has caused the conversion.
nR
u The rest of lower half is identical to the
upper half.
U

u ADC clock prescalar is mainly defined in

ADCCTRL3 register.
6 - 19
 ADC Control Register 3
ADCTRL3 @ 0x007118

ADC Reference ADC Bandgap ADC Power Down

Power Down Power Down (except Bandgap & Ref.)

d
0 = powered down 0 = powered down 0 = powered down

re
1 = powered up 1 = powered up 1 = powered up

te
15 - 8 7 6 5

is
reserved ADCRFDN ADCBGND ADCPWDN

4
eg
3 2 1 0
nR
ADCCLKPS3 ADCCLKPS2 ADCCLKPS1 ADCCLKPS0 SMODE_SEL
U

ADC Clock Prescale Sampling Mode Select

0 = sequential sampling mode
1 = simultaneous sampling mode
6 - 20
 Maximum Conversion Channels Register
ADCMAXCONV @ 0x007102

Bit fields define the maximum number of auto conversions (binary+1)

Cascaded Mode

d
re
MAX_ MAX_ MAX_ MAX_ MAX_ MAX_ MAX_
reserved

te
CONV 2_2 CONV 2_1 CONV 2_0 CONV 1_3 CONV 1_2 CONV 1_1 CONV 1_0

is
eg
SEQ2 SEQ1
Dual Mode
nR
Auto conversion session always starts with the initial state
and continues sequentially until the end state, if allowed
U

SEQ1 SEQ2 Cascaded

Initial state CONV00 CONV08 CONV00
End state CONV07 CONV15 CONV15

6 - 21
 ADC Input Channel Select Sequencing
Control Register

d
Bits 15-
15-12 Bits 11-
11-8 Bits 7-
7- 4 Bits 3-
3-0

re
0x007103 CONV03 CONV02 CONV01 CONV00 ADCCHSELSEQ1

te
0x007104 CONV07 CONV06 CONV05 CONV04 ADCCHSELSEQ2

is
0x007105 CONV11 CONV10 CONV09 CONV08 ADCCHSELSEQ3

eg
0x007106 CONV15 CONV14 CONV13 CONV12 ADCCHSELSEQ4
nR
U

6 - 22
Example - Sequencer Start/Stop Operation

EVA
Timer 1

d
re
EVA
PWM

te
is
I1 , I2 , I3 V1, V2, V3 I1 , I2 , I3 V1, V2, V3

eg
nR
System Requirements:
Three auto conversions (I1, I2, I3) off trigger 1 (Timer underflow)
Three auto conversions (V1, V2, V3) off trigger 2 (Timer period)
U

Event Manager A (EVA) and SEQ1 are used for this example
with sequential sampling mode

6 - 23
Example - Sequencer Start/Stop Operation
(Continued)

MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to:
Bits 15
15--12 11-
11-8 7-
7-4 3-
3-0
0x007103 V1 I3 I2 I1 ADCCHSELSEQ1

d
0x007104 x x V3 V2 ADCCHSELSEQ2

re
Once reset and initialized, SEQ1 waits for a trigger

te
First trigger three conversions performed: CONV00 (I1), CONV01 (I2), CONV02 (I3)
MAX_CONV1 value is reset to 2 (unless changed by software)

is
SEQ1 waits for second trigger

eg
Second trigger three conversions performed: CONV03 (V1), CONV04 (V2), CONV05 (V3)
End of second auto conversion session, ADC Results registers have the following values:
nR
RESULT0 I1 RESULT3 V1
RESULT1 I2 RESULT4 V2
U

RESULT2 I3 RESULT5 V3

User can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 session
SEQ1 keeps waiting at current state for another trigger

6 - 24
 ADC Conversion Result Buffer Register
ADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117
(Total of 16 Registers)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

d
MSB LSB

re
te
With analog input 0V to 3V, we have:

is
analog volts converted value RESULTx
3.0
eg FFFh 1111|1111|1111|0000
nR
1.5 7FFh 0111|1111|1111|0000
0.00073 1h 0000|0000|0001|0000
U

0 0h 0000|0000|0000|0000

6 - 25
 How do we Read the Result?
Integer format
x x x x x x x x x x x x 0 0 0 0 RESULTx

15 bit shift right 0

d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x xx x ACC

re
0 0 0 0 x x x x x x x x x x x x Data Mem

te
is
eg
Example: read RESULT0 register
#include "DSP281x_Device.h"
nR
void main(void)
{
U

Uint16 value; // unsigned

value = AdcRegs.ADCRESULT0 >> 4;

}
6 - 26