Lab Experiment #1

Design of Combinational Logic Circuits

1.1 Objective: To learn the design of combinational logic circuits in Verilog then simulating
and synthesizing using EDA tools

1.2 Software tools Requirement

Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE
Simulation tool: ModelSim Simulator

1.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)
1.List the types of design methodologies for digital design with an example?
2. Give the difference between module and module instance.
3. What are built in gate primitivies?
4. Give the use of net, reg and wire data types.
5. Declare the following variables in Verilog:
a. An 8-bit vector net called a_in.
b. An integer called count.
c. An array called delays. Array contains 20 elements of the type integer.
d. A parameter cache_size equal to 512.

1.4.1 Problem 1: Write a Verilog code to implement Ripple Carry Adder.

The following points should be taken care of:
1. Use assign statement to design sub module half adder
2. Use gate primitives to design full adder using half adder
3. Construct the top module ripple carry adder using 1-bit full adder

1.4.2 Problem 2: Write a Verilog code to implement Multiplexer.

The following points should be taken care of:

1. Use ternary operator to design 2x1 Mux

2. Use initial and always statement to design 4x1 Mux
3. Use Gate Level Model to design 8x1 Mux using two 4x1 Mux and one 2x1 Mux

1.4.3 Problem 3: Write a Verilog code to implement Decoder

The following points should be taken care of:

1. Use dataflow model and behavioral model to design 3x8 decoder

2. Use 3x8 decoder to design 4x16 decoder
3. Use Generate Statement to design 4x16 decoder using 2x4 decoder.

1.5 Post lab

Write a verilog HDL code to design a 4-bit adder cum Subtractor using structural model.
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1.6 Result: Thus the design of combinational logic circuits was simulated in Verilog and
synthesized using EDA tools.

Lab Experiment #2
Design of Sequential Circuits
2.1 Objective: To learn the design of sequential circuits in Verilog then simulating and
synthesizing using EDA tools
2.2 Software tools Requirement
Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator
2.3 Prelab Questions
(write pre lab Q & A in an A4 sheet)
1. Write the difference between initial and always block.
2. List the Reduction and Logical Operators.
3. Give the use of Blocking and Nonblocking statments.
4. Differentiate case, casex and casez statements.
2.4.1 Problem 1: Write a Verilog code to implement Flip flops.
The following points should be taken care of:
1. Use If statement to design positive edge triggered SR flip
2. Use case statement to design negative edge triggered JK and T flip flop
3. Use Blocking and Non-Blocking statement to design negative edge triggered D flip
flop with asynchronous clear input.

2.4.2 Problem 2: Write a Verilog code to implement Counters.

The following points should be taken care of:

1. Use behavioral model to design mod n Counter with active high synchronous reset
input.
2. Use behavioral model to design Up-Down Counter. When mode =1 do up counting
and for mode=0 do down counting.
3. Use T flip flop as a sub module to design Decade Counter active low asynchronous
reset input.
2.4.2 Problem 3: Write a Verilog code to implement Shift Registers.

1. Use behavioral model to design a n-bit SISO shift register using active high
synchronous reset input
2. Use behavioral model to design a n-bit SIPO shift register using active high
asynchronous reset input.
3. Use D flip flop with negative edge clock and asynchronous clear input to design n bit
PIPO shift register.

2.5 Post Lab :

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 Write a Verilog HDL Code to design a Ring Counter
2.6 Result:
Lab Experiment #3
Design of VLSI multipliers
3.1 Objective: To learn the design of VLSI multipliers in Verilog then simulating and
synthesizing using EDA tools.

3.2 Software tools Requirement

Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator

3.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)
1. Give the difference between Task and function
2. Design a 2-bit multiplier using functions.
3. Differentiate Primitive and Parameter.
4. Design an NAND gate using Switch Level Model in Verilog\

3.4 Problem 1: Write a Verilog code to implement Braun Array multiplier

The following points should be taken care of:

1. Use structural model to design 4-bit Braun array multiplier

3.6 Postlab question

Write a Verilog HDL to design 4-bit Baugh wooley multiplier

3.7 Result:

Lab Experiment #4
Design of MAC Unit

4.1 Objective: To learn the design of Multiply-Accumulate circuits in Verilog then simulating
and synthesizing using EDA tools

4.2 Software tools Requirement

Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk

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 Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator

4.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)
1. What is a MAC unit?
2. Design a 4-bit unsigned accumulator using Behaioural Verilog
3. Write a Verilog code to swap contents of two registers with and without a temporary
register.
4. Design a priority encoder in verilog.

4.4 Problem 1: Write a Verilog code to implement unsigned MAC Unit using data flow
model
4.5 Post Lab Question: Write a Verilog code to implement Last in First out Stack.
4.6 Result:

Lab Experiment #5
Design of Digital Filter

5.1 Objective: To learn the design of Digital Filter in Verilog then simulating and synthesizing
using EDA tools.

5.2 Software tools Requirement

Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator

5.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)
1. What is the basic algorithm for implementing the FIR filter?
2. List the advantage FIR filter over IIR filter.
3. Design a frequency divder using Verilog HDL.

5.4 Problem 1: Write a Verilog code to implement N order FIR filter. Use parameter
statement to define the filter coefficients

5.4 Post Lab

Write a Verilog HDL Code to implement an IIR Filter.

5.5 Result

Lab Experiment #6
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 Design of FSM

6.1 Objective: To learn the design of FSM for any application in Verilog then simulating and
synthesizing using EDA tools

6.2 Software tools Requirement

Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator
6.3 Prelab Questions
(write pre lab Q & A in an A4 sheet)
1. Draw the simple model of FSM.
2. What is the basic algorithm for sequence detector.
3. List the difference between Mealy and Moore Model.

6.4 Problem 1: Implement Sequence Recognizer for detecting three successive 1s using
Verilog code
6.5 Post Lab Question: Write a Verilog code to implement an FSM. (For any application)

6.6 Result:.

Lab Experiment #7
Design of Microprocessor Parts
7.1 Objective: To learn the design of Microprocessor parts in Verilog then simulating and
synthesizing using EDA tools

7.2 Software tools Requirement

Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator

7.3 Problem 1: Write a Verilog code to implement General Purpose Register block that has 8
eight-bit register which are used for data manipulation.

The following points should be taken care of:

1. The register block has three 3-bit address inputs which are used to index the
registers.

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 2. The input_select input determines which register receives a value from the data bus
if read_data is high; output_select determines which register is written when
write_data is high.
3. The alu_output_value bus goes directly to the ALU and is always active. The
alu_output_select address determines which register is sent directly to the ALU on
this bus.
4. The register pairing is not due to any hardware feature within the register block - the
registers are
implemented simply as an 8-element array of 8-bit registers. The pairing is
performed by the control signals module
Logic Diagram Problem 1

Fig General Purpose Register Block Diagram

7.4 Problem 2: Write a Verilog code to implement ALU block that all of the arithmetic
operations.

The following points should be taken care of:

1. Operation performed in ALU are addition, subtraction, multiplication, logical AND

and OR, left and right logical shifts, left and right arithmetic shifts, bitwise
complement, and negation.
2. The output is only 8 bits, except for the multiply, which is 16 bits. The zero flag is
defined for every operation: if the result is all zeros, the flag is set. Likewise, the
negative flag is set whenever the highest bit of the result is a 1, which indicates a
negative number in the two's complement system. The behavior and meaning of the
carry flag is dependent on the operation. For add and subtract, it indicates a carry
out or borrow in; for shifts, it indicates the bit that was shifted out.
Logic Diagram Problem 2

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 Fig : ALU Block diagram

7.5 Problem 3: Implement 64-bit x 8-bit single-port RAM design with common read and
write addresses.
Logic Diagram Problem 3

Verilog Code - Problem 3

7.6 Post Lab :Design the program counter that holds the address of the next instruction byte
and is used to index ROM when fetching instructions. It increases the output count by on the
rising edge of the clock when the increment signal is high. When the set signal is asserted, it
loads the value from the jump register through the input newCount.

7.7 Result: