3RD BERKELEY SYMPOSIUM ON

ENERGY EFFICIENT ELECTRONIC SYSTEMS

Device Design Considerations for

Ultra-Thin Body Non-Hysteretic
Negative Capacitance FETs

Chun Wing Yeung, Asif Khan

Sayeef Salahuddin, Chenming Hu
EECS, UC Berkeley

1
 Outline
Introduction
Background of Negative Capacitance
FET (NCFET)
Design considerations
Simulation of UTB NCFET
Conclusion

2
Vdd scaling is slowing down
Node 250 180 130 90 65 32 14
(nm)

Vdd 2.5 1.8 1.3 1.2 1.1 0.9 0.8

(V)

IC Vdd scaling history and ITRS projection

Source: C. Hu, IEDM 2010

Boltzmann statistics lead to 60mV/decade limit.

3
 Sub-60mV/dec Swing FETs

STRUCTURE SWITCHING MECHANISM

Lg
VG
Band-To-Band
Gate
Tunneling
Tunnel FET P+ i-Si
Gate
BOX
N+ VD>0V

Reverse-biased
P-I-N
Feedback +
Gate
+
Internal Feedback
FET
N+ i-Si P+ VD > 0
Forward-biased
Gate
A Padilla, IEDM 2008 P-I-N
Negative
Negative Capacitance
Capacitance FET Amplification
S. Salahuddin,
Nano lett. 2008
4
 The Negative Capacitor

Landau Theory of
Khan et al. APL 99, (2011)
Ferroelectric

5
The Negative Capacitance
Region
Q (C/cm^2)

|CFE|

V (v)

6
 Capacitance Model for
Negative Capacitance FET
Schematic of NCFET Capacitance Model of NCFET
VG

CFE
VMOS
Cox
Underlying
MOSFET s CMOS
Cdep
 Capacitive Divider
VG = ? ?

=
+
CFE
VMOS Since CFE can be negative:

CMOS | |
=

Condition 1: A = =
For large amplification,
|CFE| should be close to CMOS
8
 Use Negative Capacitance to Reduce the
Subthreshold Swing
Schematic of
Negative Capacitance FET VG

CFE

Underlying Cox
MOSFET

s CMOS
Cdep

= / +

 Subthreshold Swing of NCFET

= / +
| |

Condition 2: VG
For swing < 60mV/dec
|CFE| < Cox CFE
(sets the maximun value for |CFE|)
Cox
Cox

||
Cox = Cdep

 Condition for no hysteresis

= / +
| |
For stable operation (no hysteresis):

must be larger than -1
| |
Condition 3:
For no hysteresis, |CFE| must be
> -1
| | larger than CMOS
(sets the minimum value for |CFE|)
< +
| |
|CFE| > CMOS
A =

 The window of CFE
COX Condition 2:
8 If swing < 60mV/dec
Capacitance (au)

=> |CFE| < Cox

4 CMOS
Condition 3:
For no hysteresis, |CFE|
must be larger than CMOS
0
-2 -1 0 1 2 Condition 1:
VG (V) For small swing, CFE should
be ~ CMOS
12
Choosing the |CFE| value

Capacitance (au)

CMOS
4

0
-2 -1 0 1 2
VG (V)
13
 The Capacitance Mismatch
VG
CFE
8

Capacitance (au)

CMOS
CMOS
4

20
Av=
15 0
V 10

5
-2 -1 0 1 2
0
0.0 0.2 0.4 0.6
CMOS /CFE
0.8 1.0 VG (V)
14
 What do we need?
We need a underlying MOSFET with
a larger depletion capacitance.
8
CMOS (au)

0
-2 -1 0 1 2
VG (V)

15
 Device Optimization:
UTB with Extremely Thin BOX
VG
VG
Ferro- VD
electric CFE
Metal
High-K Oxide
N+ i- Semiconductor N+
Buried Oxide
Cox
p+ Si

CMOS Cs
Cdep
CBOX
By using a thin body and a thin
BOX, Cdep can be increased

16
 Simulation of Negative
Capacitance FET Structure
Coupled 2D Electrostatics-1D Landau
Simulation
VG
Ferroelectric: 1-D Landau Simulation.
PbZr0.5Ti0.5O3. Anisotropy Constants
Ferro- VD
from Haun et al., Ferroelectrics 99, 63
electric
Metal
(1989)
High-K Oxide
N+ i- Semiconductor N+
Buried Oxide Intrinsic MOSFET (2D): TCAD
Sentaurus Simulation.
p+ Si

Interlayer Metallic Electrode: To screen

out non-uniformity in potential profile
as well due to domain formation.
 Effect of varying TS
VG

3
CFE 10

0
10
Cox

IDS (A/m)
Cs
10
-3
Ts=0.5nm
CMOS Ts=1nm
Ts=2nm
Cdep 10
-6
CBOX 0.0 0.1 0.2 0.3 0.4 0.5
VGS (V)

18
 Simulated Id-Vg of
UTB NCFET
3
10

WIth FE
Vds=0.05
IDS (A/m)

0
10 Vds=0.5

~22mV/dec
~235mV/dec
-3
10 ~18mV/dec
WIthout FE
Vds=0.05
Vds=0.5
-6
10
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

Lg=32nm, Ts=0.7nm, Tox=3nm, Tbox=1nm

19
 Summary

25
400
Avg.SS (mV/dec)

ION (A/m)
300
20

LG=32nm
tS=0.7nm
200
tBOX=1nm
tOX=3nm

15 100
200 300 400 500
VDD (mV)

20
 Conclusion
NCFET can operate hysteresis free.
For sub-60mV/dec and no hysteresis,
there is a maximum and minimum
constraint for CFE.
UTB design can reduce the issue of
capacitance mismatch.
Simulation shows NCFET can achieve
swing of sub-30mV/dec from pA/m to
A/m with estimated ION of 0.250mA/m
at 0.3V VDD
21
 Acknowledgements

This work was partially supported by Office of Naval

Research, the FCRP MSD center, Qualcomm, and
NSF E3S Center at Berkeley.

22
 Thank you!

23
 Backup Slide

= =
+

=
+
+

60
SS=

60
= (1 + )
| |

24
 Ec ~ 30k to 300kV/cm
~ 0.003 to 0.03V/nm

25
 Material Exploration for Ferroelectric
Negative Capacitance
Three Different Ferroelectric Ba0.8Sr0.2TiO3-LaAlO3 superlattice
Negative Capacitance Model (layer thickness <10nm)
Systems has been identified so far.

1. Pb(Zr0.2Ti0.8)O3, > 225 0C

2. PbTiO3, > 110 0C
3. (Ba0.8Sr0.2)TiO3 > 110 0C
Negative Capacitance in sub-10nm Films:
Ba0.8Sr0.2TiO3-LaAlO3 superlattice

Au Unpublished
BSTO
...

LAO

With three different negative

BSTO
LAO
BSTO

SrRuO3
LAO capacitance material system identified,
substrate the stage is set for making the first
crystalline NCFET.
26
 MOSFET Scaling: The Negative
Capacitance Approach
Moores Law Negative Capacitance FET

Salahuddin et al., Nanoletters 8, 405 (2008).

Negative capacitance can give S < 60 mV/decade

Fabrication of Negative Capacitance FET for simultaneous High

Performance-Ultra Low Power Operation for Mobile Computing
27
 Ferroelectric Negative
Capacitance
Ferroelectric
Capacitor Positive Capacitance Negative Capacitance

V C

Landau-Devonshire Theory of Ferroelectrics tells that

Ferroelectric capacitors can give rise to negative capacitance
under certain conditions.
28
 Epitaxial Growth of
Nanoscale Ferroelectric
Material
Heterostructure
Type a-axis
param Au
eter
Pb(Zr0.2Ti0.8) Ferroelec 3.953 Ferro PZT
O3 A Dielectric STO
SrTiO3 Dielectric 3.905
A SRO
Pulsed Laser
SrRuO3 Metal
Deposition
3.92 A
STO substrate

Interface
roughness less
than 2-3 unit cell.

TEM Courtesy:
Prof. X. Pan,
UMich

Excellent Epitaxial Quality, Interface Roughness 2-3

29
 Material Exploration for
Ferroelectric Negative
Capacitance
Three Different Ferroelectric Ba Sr TiO -LaAlO
0.8 0.2 3 3 superlattic
Negative Capacitance Model (layer thickness <10nm)
Systems has been identified so far.

1. Pb(Zr0.2Ti0.8)O3, > 225 0C

2. PbTiO3, > 110 0C
3. (Ba0.8Sr0.2)TiO3 > 110 0C
Negative Capacitance in sub-10nm
Films: Ba0.8Sr0.2TiO3-LaAlO3 superlattice

Au Unpublished
BSTO
...

LAO

With three different negative

BSTO
LAO
BSTO

SrRuO3
LAO capacitance material system identified,
substrate the stage is set for making the first
crystalline NCFET.
30
31