Academic plan for 5th Semester

Lesson Plan Digital System Design ETEC-309

S. No. Topic Lectures (44)
UNIT 1
1 Introduction to VHDL, design units, data objects, 2
2 signal drivers, inertial and transport delays, delta delay, 2
3 VHDL data types, concurrent and sequential statements. 2
4 Subprograms Functions, Procedures, attributes, generio, generate, 2
package,
5 IEEE standard logic library, file I/O, 2
6 Test bench, component declaration, instantiation, configuration. 2
UNIT 2
7 Combinational logic circuit design and VHDL implementation of 2
following circuits first adder, Subtractor,
8 decoder, encoder, 2
9 multiplexer, 1
10 Arithmetic Logic Unit, 1
11 barrel shifter, 1
12 4X4 key board encoder, 1
13 multiplier, 1
14 divider, 1
15 Hamming code encoder and correction circuits. 2
UNIT 3
16 Synchronous sequential circuits design finite state machines, 2
Mealy and Moore,
17 state assignments, 2
18 design and VHDL implementation of FSMs, 3
19 Linear feedback shift register (Pseudorandom and CRC). 3
UNIT 4
20 Asynchronous sequential circuit design primitive flow table, 2
concept of race, critical race and hazards,
21 design issues like metastability, synchronizers, clock skew and 2
timing considerations
22 Introduction to place & route process, 2
23 Introduction to ROM, PLA, PAL, Architecture of CPLD 2
(Xilinx/Altera).
24 Architecture of CPLD (Xilinx/Altera). 2
Text Books:

[T1] Douglas Perry ,VHDL 4th Edition, TMH

[T2] Stephen Brown, Zvonko Vranesic, Fundamentals of Digital Logic with VHDL design,
TMH.

Reference Books:

[R1] Charles. H.Roth ,Digital System Design using VHDL, PWS (1998)

[R2] John F. Wakerley ,Digital Design Principles And Practices ,Pearson Education

[R3] Navabi Z , VHDL-Analysis & Modelling of Digital Systems,McGraw Hill.

[R4] William I. Fletcher, An Engineering Approach To Digital Design, Prentice Hall

[R5] Bhasker, A VHDL Primmer, Prentice Hall 1995.