School of Engineering

Department of Computer and Communications Engineering

Spring 2013-2014

CENG350 - Digital Logic Systems

Final exam
Instructors: Dr. Zaher Merhi Dr. Ali Bazzi Dr. Ali Ghouwayel
Dr Zouhair El-Bazzal Mr. Samih Abdul-Nabi

Date: June 11, 2014

Duration: 2 hours

Student Name: _________________________ ID: ________________________ Section: __________

Instructions:
Closed book/notes
Calculators allowed
Answer all questions
Total pages: 17 including cover
(12 Question sheets + 3 PIC Instruction set sheets+ 2 INTCON and T0CON description)

Question Mark Weight

1 25
2 25
3 25
4 25
Total 100

Page 1 of 17
Question 1 multiple choices (25 points)

Select the one correct answer according to your best knowledge. Each correct answer earns 2
or 3 points.

1) On a 10Mhz microcontroller, what value should be loaded in timer0 to produce a delay of

1.2ms when setting T0CON to 0x02 (4 points)
a) 375
b) 0x177
c) 0xFE89
d) 0xFE88

2) What is the number of instruction cycles taken by btfss if WREG = 0x22 (2 points)
loop btfss WREG,1
goto loop
a) 1
b) 2
c) 3
d) 4

3) What is the equivalent of this code (2 points)

movlw 0x38
movwf FSR0L
clrf FSR0H
a) LFSR 1, 0x038
b) LFSR 0, 0x38
c) LFSR 0, 0x380
d) None of the above

4) If the address of FSR0L is 0xFE9 and the address of FSR0H is 0XFEA. What will be the value of
INDF0 after these lines of code (3 points)
movlw 0xEA
movwf FSR0L
movlw 0x0F
movwf FSR0H
a) 0xFE9
b) 0xFE
c) 0x0F
d) Cannot tell

5) What does this program do? (2 points)

again movf PORTB, W
movwf PORTC
goto again
a) Copy port C to port B
b) Copy port B to port C
c) Copy port B to working register then read port C
d) Exchange port B and port C contents

Page 2 of 17
6) Consider the following code:
LFSR 2, 0x0FF
INCF FSR2L, F
The contents of FSR2L and FSR2H are: (3 points)
a) FSR2L = 00000000 FSR2H = 00000001
b) FSR2L = 00000001 FSR2H = 00000000
c) FSR2L = 11111111 FSR2H = 00000000
d) FSR2L = 00000000 FSR2H = 00000000

7) Consider the following program:

ORG 0x0E
MOVLW 0x0E
MOVWF TBLPTRL
CLRF TBLPTRH
CLRF TBLPTRU
TBLRD*

What is the content of TABLAT after executing this part of code? (3 points)
a) We cannot tell since we do not know the contents of the memory
b) 0x0E
c) 0x00
d) 0xFF

8) Consider a PIC18F with a speed of 10Mhz. How long will it take timer 0 to time out if TMR0L
and TMR0L are set to 0 and T0CON set to use 16 bits with the highest pres-scaling? (3 points)
a) 4.7 seconds
b) 5.7 seconds
c) 6.7 seconds
d) 7.7 seconds

9) What are the directions of RB0 and RB2 if TRISB is set to 0x55? (1 point)
a) Both are input
b) Both are output
c) RB0 input and RB2 output
d) RB0 output and RB2 input

10) Which statement is wrong? (2 points)

a) When enabling GIE all interrupts are enabled
b) TABLAT is for TBLPTR as INDF0 is for FSR0
c) With 8 bit mode, timer 0 times out when TMR0L overflow
d) PIC18F is an 8 bit microcontroller

Page 3 of 17
Question 2: Hardware (25 points)

Part1: Crystal and reset button (10 points)

Consider the following PIC18F4550.

Redraw the microcontroller and connect the following:

1- A reset button.
2- The Crystal.
3- A push button on pin RB0 that goes low when pressed.
4- A push button on pin RB1 that goes high when pressed.
5- An LED connected to RB2.

Page 4 of 17
Part2: control the LED (10 points)

Write a program that continuously turns ON the LED of part 1 when the button on RB0 is pushed and
OFF when the button on RB1 is pushed. Make the assumption that the two buttons cannot be pressed at
the same time.

Page 5 of 17
Part3: LOGICS (5 points)

Consider the following interrupt logic for the pic18f4550.

a) What should be enabled to use Timer 1 interrupt?

b) What will trigger the interrupt?

Page 6 of 17
Question 3: timers and Interrupts (25 points)

Part1: Timers (12 points)

Consider a 20 MHz PIC18F microcontroller. We wrote the following delay routine to produce a delay of
1.5ms.
Delay clrf T0CON
movlw x
movwf TMR0H
movlw y
movwf TMR0L
bsf T0CON, 7
again btfss INTCON, TMPR0IF
goto again
bcf T0CON, 7
bcf INTCON, TMR0IF
nop
return

a) How many clock cycles are needed to create a delay of 1.5 ms? (2 points)

b) What value should be loaded into timer 0? (3 points)

c) In this case what is x and what is y? (1 point)

d) To get a more accurate delay time, compute the number of instruction cycles considered as
overhead caused by the instructions of the delay routine. (3 points)

e) Taking into consideration the pre-scaling if any, what value should be loaded into timer 0 in
order to have an exact 1.5 ms? (3 points)

Page 7 of 17
Part2: Interrupts (13 points)

Consider the PIC18F microcontroller in the figure below.

a) Write the code that sets the directions of the pins (2 points)

b) Write the code needed to activate INT0 (Interrupt on RB0). (2 points)

c) Write the interrupt service routine INT0_ISR that toggles the LEDs connected to RB6 and
RB7 each time an interrupt occurs on RB0 (4 points)

Page 8 of 17
d) Write the complete program that toggles the LEDs when the button is pressed.
Make sure you use ORG properly. (5 points)

Page 9 of 17
Question 4: Small programs and indirect memory (25 points)

Part1: Indirect addressing (8 points)

Write a program that copies the contents of bank 1 to bank 2 and the contents of bank 2 to
bank 3.

Page 10 of 17
Part2: Serialization (9 points)
Write a function called Serialize that sends out on RC0 the content of register 0x222 one bit at a time
MSb first ( Most significant bit first). Before sending out the content of 0x222 you need to send a zero.
After the sending out the content of the 0x222 you need to send a zero bit as well. (9 Points)

Page 11 of 17
Part3: Accessing ROM (8 points)

Assume that ROM space starting at 0x500 contains the message Great course for great students.
Write a program to bring this message byte by byte and place in RAM locations starting at 0x40.

Page 12 of 17
PIC18F2455/2550/4455/4550
TABLE 26-2: PIC18FXXXX INSTRUCTION SET
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
Borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
Borrow
SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input and is
driven low by an external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

DS39632E-page 316 2009 Microchip Technology Inc.

 PIC18F2455/2550/4455/4550
TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP No Operation 1 0000 0000 0000 0000 None
NOP No Operation 1 1111 xxxx xxxx xxxx None 4
POP Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None
PUSH Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software Device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input and is
driven low by an external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

2009 Microchip Technology Inc. DS39632E-page 317

PIC18F2455/2550/4455/4550
TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

LITERAL OPERATIONS
ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None
TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None
TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input and is
driven low by an external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

DS39632E-page 318 2009 Microchip Technology Inc.

12/10
13/10