Академический Документы
Профессиональный Документы
Культура Документы
-- Company:
-- Engineer:
--
-- Design Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity vending is
sel1 : in STD_LOGIC;
sel2 : in STD_LOGIC;
sel3 : in STD_LOGIC;
sel4 : in STD_LOGIC;
R10 : in STD_LOGIC;
R20 : in STD_LOGIC;
cancel : in STD_LOGIC;
reset : in STD_LOGIC;
end vending;
type estados is (inicio, espera, snack, coffee, cold, candy, service, change);
begin
process(clk,reset)
begin
if reset='1' then
T:=T+1;
if ( T<=1) then
else
T:=0;
end if;
end if;
end process;
process(clk_1Hz_s,reset,R10,R20,ep,sel1,sel2,sel3,sel4,s1,s2,s3,s4)
begin
if ep=inicio then
mo<=0;
else
ep<=inicio;
end if;
ep <= inicio;
case ep is
t<=t+1;
if(R10='1' ) then
mo<=mo+10;
end if;
if(R20='1' ) then
mo<=mo+20;
end if;
ep<=snack;mo<=mo-30;s1<=s1-1;t<=0;
ep<=coffee;mo<=mo-40;s2<=s2-1;t<=0;
ep<=cold;mo<=mo-40;s3<=s3-1;t<=0;
ep<=candy;mo<=mo-30;s4<=s4-1;t<=0;
ep<=change;t<=0;
else
ep<=espera;
end if;
t<=t+1;
if(t=4) then
ep<=change;t<=0;
else
ep<=snack;
end if;
t<=t+1;
if(t=4) then
ep<=change;t<=0;
else
ep<=coffee;
end if;
t<=t+1;
if(t=4) then
ep<=change;t<=0;
else
ep<=cold;
end if;
t<=t+1;
if(t=4) then
ep<=change;t<=0;
else
ep<=candy;
end if;
t<=t+1;
if(t=4) then
mo<=0;ep<=inicio;t<=0;
else
ep<=change;
end if;
t<=t+1;
if(t=24) then
ep<=inicio;t<=0;s1<=10;s2<=10;s3<=10;s4<=10;
else
ep<=service;
end if;
ep<=inicio;
end case;
end if;
end process;
process(ep)
begin
case ep is
end case;
end process;
end Behavioral;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Target Device:
-- Tool versions:
-- Description:
--
--
-- Dependencies:
--
-- Revision:
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY simu IS
END simu;
COMPONENT vending
PORT(
clk : IN std_logic;
sel1 : IN std_logic;
sel2 : IN std_logic;
sel3 : IN std_logic;
sel4 : IN std_logic;
R10 : IN std_logic;
R20 : IN std_logic;
cancel : IN std_logic;
reset : IN std_logic;
);
END COMPONENT;
--Inputs
--Outputs
BEGIN
);
clk_process :process
begin
clk <= '1';
end process;
sel4_process :process
begin
end process;
-- Stimulus process
stim_proc: process
begin
end process;
END;