ACS715

ACS715
Automotive Grade, Fully Integrated, Hall Effect-Based Linear Current Sensor IC

with 2.1 kVRMS Voltage Isolation and a Low-Resistance Current Conductor
Not for New Design

These parts are in production but have been determined to be
NOT FOR NEW DESIGN. This classification indicates that sale of
this device is currently restricted to existing customer applications.
The device should not be purchased for new design applications
because obsolescence in the near future is probable. Samples are no
longer available.
Date of status change: June 5, 2017
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, use ACS724.
NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
ACS715
with 2.1 kVRMS Voltage Isolation and a Low-Resistance Current Conductor
FEATURES AND BENEFITS DESRIPTION

Low-noise analog signal path The Allegro ACS715 provides economical and precise
Device bandwidth is set via the FILTER pin solutions for DC current sensing in automotive systems. The
5 s output rise time in response to step input current device package allows for easy implementation by the customer.
80 kHz bandwidth Typical applications include motor control, load detection and
Total output error 1.5% typical at TA= 25C management, switch-mode power supplies, and overcurrent
Small footprint, low-profile SOIC8 package fault protection.
1.2 m internal conductor resistance
The device consists of a precise, low-offset, linear Hall circuit
2.1 kVRMS minimum isolation voltage from pins 1-4 to
with a copper conduction path located near the surface of the
pins 5-8
die. Applied current flowing through this copper conduction
5.0 V, single supply operation
path generates a magnetic field which the Hall IC converts into a
133 to 185 mV/A output sensitivity
proportional voltage. Device accuracy is optimized through the
Output voltage proportional to DC currents
close proximity of the magnetic signal to the Hall transducer.
Factory-trimmed for accuracy
A precise, proportional voltage is provided by the low-offset,
Extremely stable output offset voltage
chopper-stabilized BiCMOS Hall IC, which is programmed
Nearly zero magnetic hysteresis
for accuracy after packaging.
Ratiometric output from supply voltage
Operating temperature range, 40C to 150C The output of the device has a positive slope (>VIOUT(Q))
when an increasing current flows through the primary copper
TV America
Certificate Number: conduction path (from pins 1 and 2, to pins 3 and 4), which is
U8V 06 05 54214 010
the path used for current sampling. The internal resistance of
this conductive path is 1.2m typical, providing low power
Package: 8-Pin SOIC (suffix LC)
loss. The thickness of the copper conductor allows survival of
the device at up to 5 overcurrent conditions. The terminals
of the conductive path are electrically isolated from the signal
Continued on the next page
Approximate Scale 1:1
+5 V
8
1 VCC
IP+
7 VOUT
2 CBYP
IP+ VIOUT
0.1 F
IP ACS715
3 6
IP FILTER
4 CF
IP 5
GND
Typical Application 1.
The ACS715 outputs an analog signal, VOUT. that varies linearly with
the unidirectional DC primary sampled current, IP, within the range
specified. CF is recommended for noise management, with values that
depend on the application.
ACS715-DS, Rev. 11 June 5, 2017

ACS715 with 2.1 kVRMS Voltage Isolation and a Low-Resistance Current Conductor
DESCRIPTION (CONTINUED)
leads (pins 5 through 8). This allows the ACS715 to be used in The leadframe is plated with 100% matte tin, which is compatible
applications requiring electrical isolation without the use of opto- with standard lead (Pb) free printed circuit board assembly processes.
isolators or other costly isolation techniques. Internally, the device is Pb-free, except for flip-chip high-temperature
The ACS715 is provided in a small, surface mount SOIC8 package. Pbbased solder balls, currently exempt from RoHS. The device is
fully calibrated prior to shipment from the factory.
Selection Guide
Optimized Range, IP Sensitivity, Sens TA
Part Number Packing*
(A) (Typ) (mV/A) (C)
ACS715ELCTR-20A-T 0 to 20 185
40 to 85
ACS715ELCTR-30A-T 0 to 30 133
Tape and reel, 3000 pieces/reel
ACS715LLCTR-20A-T 0 to 20 185
40 to 150
ACS715LLCTR-30A-T 0 to 30 133
*Contact Allegro for additional packing options.
TV America Parameter Specification

Certificate Number:
CAN/CSA-C22.2 No. 60950-1-03
U8V 06 05 54214 010
Fire and Electric Shock UL 60950-1:2003
EN 60950-1:2001
Allegro MicroSystems, LLC 2

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
SPECIFICATIONS
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Supply Voltage VCC 8 V
Reverse Supply Voltage VRCC 0.1 V
Output Voltage VIOUT 8 V
Reverse Output Voltage VRIOUT 0.1 V
Output Current Source IOUT(Source) 3 mA
Output Current Sink IOUT(Sink) 10 mA
Overcurrent Transient Tolerance IP 1 pulse, 100 ms 100 A
Range E 40 to 85 C
Nominal Operating Ambient Temperature TA
Range L 40 to 150 C
Maximum Junction Temperature TJ(max) 165 C
Storage Temperature Tstg 65 to 170 C
Isolation Characteristics
Characteristic Symbol Notes Rating Unit
Agency type-tested for 60 seconds per
Dielectric Strength Test Voltage* VISO 2100 VAC
UL standard 60950-1, 1st Edition
For basic (single) isolation per UL standard 60950-1, 1st
Working Voltage for Basic Isolation VWFSI 354 VDC or Vpk
Edition
For reinforced (double) isolation per UL standard 60950-
Working Voltage for Reinforced Isolation VWFRI 184 VDC or Vpk
1, 1st Edition
* Allegro does not conduct 60-second testing. It is done only during the UL certification process.

+5 V
VCC
(Pin 8)
Hall Current
Drive
IP+ Sense Temperature

(Pin 1)
Coefficient Trim
IP+
(Pin 2)
Dynamic Offset
Cancellation
Signal VIOUT
Recovery (Pin 7)
IP
(Pin 3)
Sense
Trim
IP
(Pin 4) 0 Ampere
Offset Adjust
GND FILTER
(Pin 5) (Pin 6)
Functional Block Diagram
IP+ 1 8 VCC
IP+ 2 7 VIOUT
IP 3 6 FILTER
IP 4 5 GND
Package LC, 8-Pin SOIC Pin-out Diagram
Terminal List Table

Number Name Description
1 and 2 IP+ Input terminals for current being sampled; fused internally
3 and 4 IP Output terminals for current being sampled; fused internally
5 GND Signal ground terminal
6 FILTER Terminal for external capacitor that sets bandwidth
7 VIOUT Analog output signal
8 VCC Device power supply terminal

COMMON OPERATING CHARACTERISTICS1 over full range of TA, and VCC = 5 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Current ICC VCC = 5.0 V, output open 10 13 mA
Output Capacitance Load CLOAD VIOUT to GND 10 nF
Output Resistive Load RLOAD VIOUT to GND 4.7 k
Primary Conductor Resistance RPRIMARY TA = 25C 1.2 m
Rise Time tr IP = IP(max), TA = 25C, COUT=10 nF 3.5 s
Frequency Bandwidth f 3 dB, TA = 25C; IP is 10 A peak-to-peak 80 kHz
Nonlinearity ELIN Over full range of IP, IP applied for 5 ms 1.5 %
VCC
Zero Current Output Voltage VIOUT(Q) Unidirectional; IP = 0 A, TA = 25C V
0.1
Output reaches 90% of steady-state level, no capacitor on
Power-On Time tPO 35 s
FILTER pin; TJ=25; 20 A present on leadframe
Magnetic Coupling2 12 G/A
Internal Filter Resistance3 RF(INT) 1.7 k
1Device may be operated at higher primary current levels, IP, and ambient, TA, and internal leadframe temperatures, TA, provided that the Maximum Junction Tem-
perature, TJ(max), is not exceeded.
21G = 0.1 mT.
3R
F(INT) forms an RC circuit via the FILTER pin.
COMMON THERMAL CHARACTERISTICS1

Min. Typ. Max. Units
E range 40 85 C
Operating Internal Leadframe Temperature TA
L range 40 150 C
Value Units
Junction-to-Lead Thermal Resistance2 RJL Mounted on the Allegro ASEK 715 evaluation board 5 C/W
Mounted on the Allegro 85-0322 evaluation board, includes the power
Junction-to-Ambient Thermal Resistance2,3 RJA 23 C/W
consumed by the board
1Additional thermal information is available on the Allegro website.
2The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias connecting the layers. Per-
formance values include the power consumed by the PCB. Further details on the board are available from the Frequently Asked Questions document on our website.
Further information about board design and thermal performance also can be found in the Applications Information section of this datasheet.
3R
JA values shown in this table are typical values, measured on the Allegro evaluation board. The actual thermal performance depends on the actual application board
design, the airflow in the application, and thermal interactions between the device and surrounding components through the PCB and the ambient air. To improve
thermal performance, see our applications material on the Allegro website.

x20A PERFORMANCE CHARACTERISTICS over Range E: TA = 40C to 85C1, CF = 1 nF, and VCC = 5 V, unless otherwise speci-
fied
Optimized Accuracy Range IP 0 20 A
Sensitivity Sens Over full range of IP, IP applied for 5 ms; TA = 25C 178 185 190 mV/A
Peak-to-peak, TA = 25C, 2 kHz external filter, 185 mV/A
Noise VNOISE(PP) programmed Sensitivity, CF = 47 nF, COUT = 10 nF, 2 kHz 21 mV
bandwidth
TA = 40C to 25C 0.08 mV/C
Zero Current Output Slope VOUT(Q)
TA = 25C to 150C 0.16 mV/C
TA = 40C to 25C 0.035 mV/A/C
Sensitivity Slope Sens
TA = 25C to 150C 0.019 mV/A/C
Electrical Output Voltage VOE IP = 0 A 40 40 mV
Total Output Error2 ETOT IP = 20 A, IP applied for 5 ms; TA = 25C 1.5 %
1Device may be operated at higher primary current levels, IP, and ambient temperatures, TA, provided that the Maximum Junction Temperature, TJ(max), is not
exceeded.
2Percentage of I , with I = 20 A. Output filtered.
P P
x20A PERFORMANCE CHARACTERISTICS over Range L: TA = 40C to 150C1, CF = 1 nF, and VCC = 5 V, unless otherwise
specified
Over full range of IP, IP applied for 5 ms; TA = 25C 185 mV/A
Sensitivity Sens
Over full range of IP, TA = 40C to 150C 161 194 mV/A
bandwidth
TA = 40C to 25C 0.08 mV/C
TA = 25C to 150C 0.16 mV/C
TA = 40C to 25C 0.035 mV/A/C
TA = 25C to 150C 0.019 mV/A/C
IP = 20 A, IP applied for 5 ms; TA = 25C 1.5 %
Total Output Error2 ETOT
IP = 20 A, IP applied for 5 ms; TA = 40C to 150C 6 6 %
1Device may be operated at higher primary current levels, I , and ambient temperatures, T , provided that the Maximum Junction Temperature, T (max), is not
P A J
exceeded.
P P

x30A PERFORMANCE CHARACTERISTICS over Range E: TA = 40C to 85C1, CF = 1 nF, and VCC = 5 V, unless otherwise speci-
fied
Sensitivity Sens Over full range of IP, IP applied for 5 ms; TA = 25C 129 133 137 mV/A
bandwidth
TA = 40C to 25C 0.06 mV/C
TA = 25C to 150C 0.1 mV/C
TA = 40C to 25C 0.007 mV/A/C
TA = 25C to 150C 0.025 mV/A/C
Total Output Error2 ETOT IP = 30 A, IP applied for 5 ms; TA = 25C 1.5 %
1Device may be operated at higher primary current levels, IP, and ambient temperatures, TA, provided that the Maximum Junction Temperature, TJ(max), is not
exceeded.
P P
x30A PERFORMANCE CHARACTERISTICS over Range L: TA = 40C to 150C1, CF = 1 nF, and VCC = 5 V, unless otherwise
specified
Over full range of IP, IP applied for 5 ms; TA = 25C 133 mV/A
Sensitivity Sens
Over full range of IP, TA = 40C to 150C 125 137 mV/A
bandwidth
TA = 40C to 25C 0.06 mV/C
TA = 25C to 150C 0.1 mV/C
TA = 40C to 25C 0.007 mV/A/C
TA = 25C to 150C 0.025 mV/A/C
IP = 0 A, TA = 25C 40 40 mV
Electrical Output Voltage VOE
IP = 0 A, TA = 40C to 150C 60 60 mV
IP = 30 A, IP applied for 5 ms; TA = 25C 1.5 %
Total Output Error2 ETOT
IP = 30 A, IP applied for 5 ms; TA = 40C to 150C 5 5 %
1Device may be operated at higher primary current levels, I , and ambient temperatures, T , provided that the Maximum Junction Temperature, T (max), is not
P A J
exceeded.
P P

CHARACTERISTIC PERFORMANCE
IP = 20 A, unless otherwise specified
Mean Supply Current versus Ambient Temperature Supply Current versus Supply Voltage
10.5 11.2
10.4 11.0
10.3 10.8
10.2 VCC = 5 V
10.6
Mean ICC (mA)
ICC (mA)
10.1
10.4
10.0
10.2
9.9
9.8 10.0
9.7 9.8
9.6 9.6
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (C) VCC (V)
Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

0 0.35
0.5
0.30
1.0
1.5 0.25
2.0
ELIN (%)
0.20
IOM (mA)
2.5 VCC = 5 V; IP = 0 A,
After excursion to 20 A 0.15
3.0
3.5 0.10
4.0
0.05
4.5
5.0 0
-50 -25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150
TA (C) TA (C)
Mean Total Output Error versus Ambient Temperature Sensitivity versus Ambient Temperature
10 188
8
187
6
4 186
Sens (mV/A)
ETOT (%)
2
185
0
2 184
4
183
6
8 182
50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150
TA (C) TA (C)
Output Voltage versus Sensed Current Sensitivity versus Sensed Current
5.0 200.00
4.5 198.00
196.00
4.0 194.00
3.5 VCC = 5 V 192.00
190.00
Sens (mV/A)
3.0
VIOUT (V)
TA (C) 188.00
2.5 186.00
40
2.0 184.00 TA (C)
20
1.5 182.00 40
25
180.00 25
1.0 85
178.00 85
0.5 125
176.00 150
0 174.00
0 5 10 15 20 25 0 5 10 15 20 25
Ip (A)
IP (A)
0 A Output Voltage versus Ambient Temperature 0 A Output Voltage Current versus Ambient Temperature
525 0.140
0.120
520
0.100
515 IP = 0 A IP = 0 A
0.080
VIOUT(Q) (mV)
IOUT(Q) (A)
510 0.060
505 0.040
0.020
500
0
495
-0.020
490 -0.040
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (C) TA (C)

CHARACTERISTIC PERFORMANCE
IP = 30 A, unless otherwise specified
Mean Supply Current versus Ambient Temperature Supply Current versus Supply Voltage
10.1 10.8
10.0 10.6
9.9 10.4
ICC (mA)
Mean ICC (mA)
90.8 VCC = 5 V 10.2
9.7 10.0
9.6 9.8
9.5 9.6
9.4 9.4
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (C) VCC (V)
Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

0 0.35
0.5
0.30
1.0
1.5 0.25
IOM (mA)
2.0 0.20 VCC = 5 V
ELIN (%)
2.5 VCC = 5 V; IP = 0 A,
After excursion to 20 A 0.15
3.0
3.5 0.10
4.0
0.05
4.5
5.0 0
-50 -25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150
TA (C) TA (C)
Mean Total Output Error versus Ambient Temperature Sensitivity versus Ambient Temperature
8 133.5
6 133.0
Sens (mV/A)
4 132.5
ETOT (%)
2 132.0
0 131.5
2 131.0
4 130.5
6 130.0
8 129.5
50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150
TA (C) TA (C)
Output Voltage versus Sensed Current Sensitivity versus Sensed Current

5.0 140
4.5 139
138
4.0 137
Sens (mV/A)
3.5 VCC = 5 V 136

VIOUT (V)
135
3.0 134
TA (C) 133
2.5
132
40 131
2.0 TA (C)
20 130
1.5 25 40
129
85 128 25
1.0
125 127 85
0.5 126 150
0 125
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Ip (A)
IP (A)
0 A Output Voltage versus Ambient Temperature 0 A Output Voltage Current versus Ambient Temperature
514 0.080
512
510 0.060
508 IP = 0 A IP = 0 A
VIOUT(Q) (mV)
0.040
506
IOUT(Q) (A)
504 0.020
502
500 0
498
-0.020
496
494 -0.040
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (C) TA (C)

DEFINITIONS OF ACCURACY CHARACTERISTICS

Sensitivity (Sens). The change in device output in response to a Accuracy is divided into four areas:
1A change through the primary conductor. The sensitivity is the
0 A at 25C. Accuracy at the zero current flow at 25C,
product of the magnetic circuit sensitivity (G/A) and the linear
without the effects of temperature.
IC amplifier gain (mV/G). The linear IC amplifier gain is pro-
0 A over temperature. Accuracy at the zero current flow
grammed at the factory to optimize the sensitivity (mV/A) for the
including temperature effects.
full-scale current of the device.
Full-scale current at 25C. Accuracy at the the full-scale current
Noise (VNOISE). The product of the linear IC amplifier gain at 25C, without the effects of temperature.
(mV/G) and the noise floor for the Allegro Hall effect linear IC Full-scale current over temperature. Accuracy at the full-
(1 G). The noise floor is derived from the thermal and shot scale current flow including temperature effects.
noise observed in Hall elements. Dividing the noise (mV) by the Ratiometry. The ratiometric feature means that its 0 A output,
sensitivity (mV/A) provides the smallest current that the device is VIOUT(Q), (nominally equal to VCC 0.1) and sensitivity, Sens, are
able to resolve. proportional to its supply voltage, VCC.The following formula is
used to derive the ratiometric change in 0 A output voltage,
Linearity (ELIN). The degree to which the voltage output from
VIOUT(Q)RAT (%).
the IC varies in direct proportion to the primary current through
its full-scale amplitude. Nonlinearity in the output can be attrib- VIOUT(Q)VCC / VIOUT(Q)5V

uted to the saturation of the flux concentrator approaching the 100
full-scale current. The following equation is used to derive the VCC / 5 V
linearity: The ratiometric change in sensitivity, SensRAT (%), is defined as:
{ [
100 1
(VIOUT_full-scale amperes VIOUT(Q) )
2 (VIOUT_half-scale amperes VIOUT(Q)) [{ SensVCC / Sens5V

100
where VIOUT_full-scale amperes = the output voltage (V) when the VCC / 5 V
sampled current approximates full-scale IP .
Quiescent output voltage (VIOUT(Q)). The output of the device
Increasing VIOUT(V)
when the primary current is zero. For a unipolar supply voltage, Accuracy
Over Temp erature
it nominally remains at VCC 0.1 . Thus, VCC = 5 V translates
into VIOUT(Q) = 0.5 V. Variation in VIOUT(Q) can be attributed to Accuracy
25C Only
the resolution of the Allegro linear IC quiescent voltage trim and

Average
thermal drift. VIOUT
Accuracy
Electrical offset voltage (VOE). The deviation of the device Over Temp erature
output from its ideal quiescent value of VCC 0.1 due to non-
Accuracy
magnetic causes. To convert this voltage to amperes, divide by the 25C Only
device sensitivity, Sens. 30 A

IP (A) +IP (A)
Accuracy (ETOT). The accuracy represents the maximum devia- Full Scale
tion of the actual output from its ideal value. This is also known
as the total output error. The accuracy is illustrated graphically in 0A
the output voltage versus current chart at right.
Decreasing VIOUT(V)
Figure 1: Output Voltage versus Sampled Current

Accuracy at 0 A and at Full-Scale Current

DEFINITIONS OF DYNAMIC RESPONSE CHARACTERISITCS
Power-On Time (tPO). When the supply is ramped to its operat-

ing voltage, the device requires a finite time to power its internal
components before responding to an input magnetic field.
Power-On Time, tPO , is defined as the time it takes for the output
voltage to settle within 10% of its steady state value under an
applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in the
chart at right.
Figure 2: Power-On Time
Rise time (tr). The time interval between a) when the device I (%) Primary Current
reaches 10% of its full scale value, and b) when it reaches 90% 90
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the device, in which (3 dB) = 0.35/tr. Transducer Output
Both tr and tRESPONSE are detrimentally affected by eddy current 10

0
losses observed in the conductive IC ground plane. Rise Time, tr
t
Figure 3: Rise Time
Noise vs. Filter Cap

Power on Time versus External Filter Capacitance Noise versus External Filter Capacitance
200 10000
180
160 IP = 5 A
140 1000
120
Noise(p-p) (mA)
tPO (s)
IP = 0 A
100 100
80
60
40 10
20
0
1
0 10 20 30 40 50 0.01 0.1 1 10 100 1000
CF (nF)
CF (nF)
Rise Time versus External Filter Capacitance Rise Time versus External Filter Capacitance
1200 CF (nF) tr (s) 180
160
1000 Open 3.5
1 5.8 140
800 4.7 17.5 120
tr(s)
tr(s)
Expanded in chart at right 22 73.5 100

600
47 88.2 80
}
400 100 291.3 60

220 623 40
200 470 1120 20
0 0
0.1 1 10 100 1000 0.1 1 10 100
CF (nF) CF (nF)
Figure 4: Power-On and Rise Time Characteristics

CHOPPER STABILIZATION TECHNIQUE

Chopper Stabilization is an innovative circuit technique that is This technique is made possible through the use of a BiCMOS
used to minimize the offset voltage of a Hall element and an process that allows the use of low-offset and low-noise amplifiers
associated on-chip amplifier. Allegro has a Chopper Stabiliza- in combination with high-density logic integration and sample
tion technique that nearly eliminates Hall IC output drift induced
and hold circuits.
by temperature or package stress effects. This offset reduction +5 V
VS1 Regulator
technique is based on a signal modulation-demodulation process.
Modulation is used to separate the undesired DC offset signal CBYP
0.1 F
from the magnetically induced signal in the frequency domain. 1
8 Clock/Logic
VCC
Then, using a low-pass filter, the modulated DC offset is sup- 2
IP+
7 VElement
Hall OUT + U1
LMC6772
Low-Pass
IP+ VIOUT Filter
pressed while the magnetically induced signal passes through
Sample and
ACS715 VREF
the filter. As a result of this chopper stabilization approach,
IP1 the
Hold
Amp
3 6
FILTER
output voltage from the Hall IC is desensitized to the effects4 IP CF
IP
of temperature and mechanical stress. This technique produces GND 5
devices that have an extremely stable Electrical Offset Voltage, Q3
2N7002
are immune to thermal stress, and have precise recoverability Q1 R3
after temperature cycling. FDS6675a 10 k
R1
100 k Figure 5: Concept of Chopper Stabilization Technique
VS2 +5 V LOAD
+5 V +5 V
CBYP
CBYP CBYP 0.1 F
R1 R1
0.1 F 33 k 8 0.1 F
1 VCC 100 k
IP+ U2
RPU 2
IP+ VIOUT
7 VOUT + LMC6772
R2 100 k R2
100 k ACS715 VREF 100 k
8 IP2 1 + LM321
1 VCC 6 8 5 VOUT
IP+ 3 1 VCC 4
IP FILTER IP+
2
IP+ VIOUT
7 VOUT 4 5 CF
2 7 3
1 Fault 4 IP 5 IP+ VIOUT 2
GND RF
IP ACS715 3 + C1
2 U1 IP ACS715 1 k
3 6 Q4 R3 1000 pF
LMV7235 6
IP FILTER 3 2N7002
IP FILTER 3.3 k
CF CF
4 Q2 4R4
IP 5 0.01 F
GND FDS6675a 10IP
k GND 5
D1 R2
1N914 100 k
Application 2. 10 A Overcurrent Fault Latch. Fault threshold set by R1 Application 3. This configuration increases gain to 610 mV/A (tested
and R2. This circuit latches an overcurrent fault and holds it until the using the ACS712ELC-05A).
5 V rail is powered down.
VS1 +5 V VS2 +5 V
CBYP CBYP
0.1 F 0.1 F
8 8
1 VCC 1 VCC
IP+ IP+ U2
U1
2 7 VOUT + LMC6772 2
IP+ VIOUT
7 VOUT + LMC6772
IP+ VIOUT
ACS715 VREF ACS715 VREF

IP1 IP2
3 6 3 6
Application 4. Control circuit for MOSFET ORing. IP FILTER IP FILTER
CF CF
4 4
IP 5 IP 5
GND GND
Q3 Q4
2N7002 2N7002
Q1 R3 Q2 R4
FDS6675a 10 k FDS6675a 10 k
R1 R2
100 k 100 k
LOAD
Figure 6: Typical Applications

IMPROVING SENSING SYSTEM ACCURACY USING THE FILTER PIN

In low-frequency sensing applications, it is often advantageous resistance values will most likely drift by different amounts over
to add a simple RC filter to the output of the device. Such a low- temperature. Therefore, signal attenuation will vary as a function
pass filter improves the signal-to-noise ratio, and therefore the of temperature. Note that, in many cases, the input impedance,
resolution, of the device output signal. However, the addition of RINTFC, of a typical analog-to-digital converter (ADC) can be as
an RC filter to the output of a sensor IC can result in undesirable low as 10 k.
device output attenuation even for DC signals.
The ACS715 contains an internal resistor, a FILTER pin connec-
Signal attenuation, VATT, is a result of the resistive divider tion to the printed circuit board, and an internal buffer ampli-
effect between the resistance of the external filter, RF (see Appli- fier. With this circuit architecture, users can implement a simple
cation 5), and the input impedance and resistance of the customer RC filter via the addition of a capacitor, CF (see Application 6)
interface circuit, RINTFC. The transfer function of this resistive from the FILTER pin to ground. The buffer amplifier inside of
divider is given by: the ACS715 (located after the internal resistor and FILTER pin
RINTFC connection) eliminates the attenuation caused by the resistive
VATT = VIOUT .
RF + RINTFC divider effect described in the equationfor VATT. Therefore, the
ACS715 device is ideal for use in high-accuracy applications that
Even if RF and RINTFC are designed to match, the two individual cannot afford the signal attenuation associated with the use of an
external RC low-pass filter.
+5 V
Pin 3 Pin 4 VCC

IP IP Pin 8
Allegro ACS706
Voltage
Regulator
To all subcircuits
Application 5. When a low pass filter is con-
structed externally to a standard Hall effect VIOUT
Pin 7
Resistive Divider
Dynamic Offset
Input
Cancellation
device, a resistive divider may exist between RF

Filter
Amp Out N.C. Application

the filter resistor, RF, and the resistance of the 0.1 F Pin 6 Interface
Circuit
customer interface circuit, RINTFC. This resis- Low Pass Filter
tive divider will cause excessive attenuation,
as given by the transfer function for VATT. Gain
Temperature
Coefficient
Offset
CF
RINTFC
Trim Control
IP+ IP+ GND

Pin 1 Pin 2 Pin 5
+5 V
VCC
Pin 8
Allegro ACS715
Hall Current
Drive
Application 6. Using the FILTER
pin provided on the ACS715 elimi- IP+ Sense Temperature
Pin 1
nates the attenuation effects of the Coefficient Trim
resistor divider between RF and IP+

Pin 2
Buffer Amplifier
Dynamic Offset
and Resistor
Cancellation
RINTFC, shown in Application 5. Signal VIOUT

Recovery Pin 7
Input
IP Application
Pin 3 Interface
Sense
Trim Circuit
IP
Pin 4 0 Ampere
Offset Adjust
RINTFC
GND FILTER
Pin 5 Pin 6
CF
Figure 7: Typical Applications

PACKAGE OUTLINE DRAWING
For Reference Only Not for Tooling Use

(Reference MS-012AA)
Dimensions in millimeters NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
8
4.90 0.10 0
0.65 1.27
8
8
0.25
0.17
3.90 0.10 6.00 0.20 5.60

A
1.04 REF
1.75
1 2
1.27 1 2
0.40
C PCB Layout Reference View
0.25 BSC
SEATING PLANE
Branded Face
GAUGE PLANE
8X C
1.75 MAX NNNNNNN
0.10 C
SEATING
PLANE PPT-AAA
LLLLL
0.51 0.25
0.31 0.10
1.27 BSC 1
A Terminal #1 mark area B Standard Branding Reference View
N = Device part number
B Branding scale and appearance at supplier discretion P = Package Designator
T = Device temperature range
C Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M); A = Amperage
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary L = Lot number
to meet application process requirements and PCB layout tolerances. Belly Brand = Country of Origin
Figure 8: Package LC, 8-pin SOIC

Revision History
Revision Revision Date Description of Revision
9 November 16, 2014 Update rise time and isolation, IOUT reference data, patents
10 June 24, 2015 Revised performance characteristics
11 June 5, 2017 Updated product status
Copyright 2006-2017, Allegro MicroSystems, LLC

The products described herein are protected by U.S. patents: 5,621,319; 7,598,601; and 7,709,754.
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegros products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, go to our website at:


ACS715

Загружено:

Сведения о документе

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

ACS715

Загружено:

Авторское право:

Доступные форматы

ACS715

Automotive Grade, Fully Integrated, Hall Effect-Based Linear Current Sensor IC

Not for New Design

Date of status change: June 5, 2017

NOTE: For detailed information on purchasing options, contact your

FEATURES AND BENEFITS DESRIPTION

Continued on the next page

Approximate Scale 1:1

ACS715-DS, Rev. 11 June 5, 2017

TV America Parameter Specification

Allegro MicroSystems, LLC 2

Allegro MicroSystems, LLC 3

IP+ Sense Temperature

Functional Block Diagram

Package LC, 8-Pin SOIC Pin-out Diagram

Terminal List Table

Allegro MicroSystems, LLC 4

COMMON THERMAL CHARACTERISTICS1

Allegro MicroSystems, LLC 5

Allegro MicroSystems, LLC 6

Allegro MicroSystems, LLC 7

Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

Allegro MicroSystems, LLC 8

90.8 VCC = 5 V 10.2

Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

2.0 0.20 VCC = 5 V

Output Voltage versus Sensed Current Sensitivity versus Sensed Current

3.5 VCC = 5 V 136

Allegro MicroSystems, LLC 9

DEFINITIONS OF ACCURACY CHARACTERISTICS

the resolution of the Allegro linear IC quiescent voltage trim and

device sensitivity, Sens. 30 A

the output voltage versus current chart at right.

Figure 1: Output Voltage versus Sampled Current

Allegro MicroSystems, LLC 10

DEFINITIONS OF DYNAMIC RESPONSE CHARACTERISITCS

Power-On Time (tPO). When the supply is ramped to its operat-

Figure 2: Power-On Time

Both tr and tRESPONSE are detrimentally affected by eddy current 10

Figure 3: Rise Time

Noise vs. Filter Cap

Expanded in chart at right 22 73.5 100

400 100 291.3 60

Figure 4: Power-On and Rise Time Characteristics

Allegro MicroSystems, LLC 11

CHOPPER STABILIZATION TECHNIQUE

ACS715 VREF ACS715 VREF

Figure 6: Typical Applications

Allegro MicroSystems, LLC 12

IMPROVING SENSING SYSTEM ACCURACY USING THE FILTER PIN

Pin 3 Pin 4 VCC

device, a resistive divider may exist between RF

Amp Out N.C. Application

IP+ IP+ GND

resistor divider between RF and IP+

RINTFC, shown in Application 5. Signal VIOUT

Figure 7: Typical Applications

Allegro MicroSystems, LLC 13

PACKAGE OUTLINE DRAWING

For Reference Only Not for Tooling Use

3.90 0.10 6.00 0.20 5.60

Figure 8: Package LC, 8-pin SOIC

Allegro MicroSystems, LLC 14

Copyright 2006-2017, Allegro MicroSystems, LLC