Timing and Control

ECEg3202 Computer
Architecture and Organization
Basic Computer

Consider the basic computer with

Memory unit with 4096 16-bit words

Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR,
SC

Flip-flops: I, S, E, R, IEN, FGI, FGO

3 x 8 op decoder and 4 x 16 timing decoder

16-bit common bus

Control logic gates

Adder and logic circuit connected to input of AC

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Instruction Code

Computer instruction is binary code that
specifies a sequence of microoperations

Operation Code + Address

Op code must have n bits for 2n operations

Op code sometimes called a macrooperation

Address is register or memory location

Memory location is operand address

Instructions (Instruction Code) and data are

stored in memory

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Instruction Code

Stored Program Organization

One processor register

AC accumulator

Instruction format

4-bit op code

12-bit address (for 212 = 4096 memory words)

Instruction execution cycle

Read 16-bit instruction from memory

Use 12-bit address to fetch operand from memory

Execute 4-bit op code

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 Stored Program Organization

Both Data and Instruction are stored in same
memory unit

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 Stored Program Organization
 12-bit instruction address

Immediate

Actual data value

Direct

Memory address where data
(operand) resides

Indirect

Memory address where
memory address of data
(operand) resides
 Effective address is the
address of the operand
 Leading bit of instruction is
used as indirect flag
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Organization 6
Basic Computer Registers
Register Number Register Name Function
Symbol of Bits
DR 16 Data Register Holds data from memory (operand)

AR 12 Address Register Holds address of memory

AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code

PC 12 Program Counter Holds address of next instruction

TR 16 Temporary Register Holds general temporary data

INPR 8 Input Register Holds input character

OUTR 8 Output Register Holds output character

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 Basic Computer Registers

Register and Memory layout

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Organization 8
 Basic Computer Registers

Registers control inputs
 Load (LD)
 Increment (INR)
 Clear (CLR)

Common Bus
 Connects registers and memory
 Specific output selected by S2S1S0

When register has < 16 bits, high-order bus bits are set to 0
 Register with LD enabled reads data from bus
 Memory with Write enabled reads bus
 Memory with Read enabled puts data on bus

When S2S1S0 = 111
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 Basic Computer Registers

Program Counter (PC)

Holds memory address of next instruction

Next instruction is fetched after current instruction
completes execution cycle

PC is incremented right after instruction is fetched
from memory

PC value can be replaced by new address when
executing a branch instruction

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 Basic Computer Registers

Address Register (AR)

Always used to specify address within memory unit

Dedicated register eliminates need for separate
address bus

Content of any register output connected to the bus
can be written to memory

Any register input connected to bus can be target of
memory read

As long as its LD is enabled

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 Basic Computer Registers

Accumulator (AC)

Input comes from adder and logic circuit

Adder and logic circuit

Input

16-bit output of AC

16-bit data register (DR)

8-bit input register (INPR)

Output

16-bit input of AC

E flip-flop (extended AC bit, aka overflow)

DR and AC inputs are used for arithmetic and
logic microoperations
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Organization 12
 Basic Computer Registers
 Content of any register
Bus Connection
output connected to the bus
can be applied to the bus and
content of any register input
connected to the bus can be
loaded from the bus during
the same clock cycle
 These 2 microoperations can
be executed at the same time

DR AC and AC DR

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Computer Instruction

Instruction Format

Only 3 bits used for op code

For op code 111, one of the low-order 12 bits is

turned on to extend the op code definition
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 Computer Instructions

16 bits of instruction

1 bit addressing mode

3 bits operation code

12 bits address

Three types of instructions

Memory Reference

Register Reference

Input - Output

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Memory Reference Instructions
Hexadecimal Code

Symbol I=0 I=1 Description

Memory Reference Instructions

AND 0XXX 8XXX AND memory word to AC

ADD 1XXX 9XXX ADD memory word to AC

LDA 2XXX AXXX Load memory word to AC

STA 3XXX BXXX Store content of AC in memory

BUN 4XXX CXXX Branch unconditionally

BSA 5XXX DXXX Branch and save return address

ISZ 6XXX EXXX Increment and skip if zero

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Register Reference Instructions
Hexadecimal Code
Symbol I=0 I=1 Description
Register Reference Instructions
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E'
CIL 7040 Circulate left AC and E'
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E zero
HLT 7001 Halt Computer
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Input - Output
Hexadecimal Code

Symbol I=0 I=1 Description

Input - Output Instructions

INP F800 Input character to AC

OUT F400 Output character from AC

SKI F200 Skip on input flag

SKO F100 Skip on output flag

ION F080 Interrupt on

IOF F040 Interrupt off

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Instruction Set Completeness

Arithmetic, Logic, Shift instructions

AND, ADD

CLA, CLE, CMA, CME, CIR, CIL, INC

Move data from and to memory and register

LDA, STA

Program control and status check

BUN, BSA, ISZ

SPA, SNA, SZA, SZE

SKI, SKO, ION, IOF

Input and Output

INP, OUT
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Organization 19
Timing and Control

Control Unit
 Instruction read from
memory and put in IR

Leftmost bit put in I flip-flop

3-bit op code decoded with 3 x
8 decoder into D0 to D7

4-bit sequence counter (SC)
decoded with 4 x 16 decoder
into T0 to T15 (timing signals)

I, D0 to D7, T0 to T15,
rightmost 12 bits of IR, and
other inputs are fed into
control and logic gates.

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Timing and Control

Sequence Counter
Timing Diagram
 Inputs are increment
(INR) and clear (CLR)
 Example

SC incremented to provide
T0, T1, T2, T3, and T4

At time T4, SC is cleared to
0 if D3 is active

Written as:

D3T4: SC 0

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Instruction Cycle
1. Fetch instruction from memory
2. Decode the instruction
3. Read effective address from memory if
indirect address
4. Execute the instruction

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Fetch and Decode

SC cleared to 0, generating timing signal T0

After each clock pulse, SC is incremented
generating T1, T2, T3

Fetch micro-operation

T0: AR
PC

T1: IR
M[AR], PC
PC + 1

Decode micro-operation

T2: I
IR(15), D0D7
decode IR(12-14), AR
IR(0-11)

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Hardwiring Fetching Phase

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Instruction Cycle Flow Chart

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Instruction Paths

Memory (000 - 110)

Direct

D7IT3: Do nothing

Indirect

D7IT3: AR
M[AR]

Non Memory (111)

I=0

D7IT3: Register Reference Instruction

I=1

D7IT3: Input Output Instruction

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Basic Computer Instructions

Register Reference

D7IT3

Memory Reference

D7IT3 and D7IT3

D0 D6

T4 -

Input Output

D7IT3

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Register Reference Instruction
Basic Computer Instructions

Symbol Control Operation Description

CLA rB11 AC 0, SC 0 Clear AC

CLE rB10 E 0, SC 0 Clear E
CMA rB9 AC AC, SC 0 Complement AC
CME rB8 E E, SC 0 Complement E
CIR rB7 AC shr AC, AC(15)E, E AC(0), SC 0 Circulate right AC and E'

CIL rB6 AC shl AC, AC(0)E, E AC(15), SC 0 Circulate left AC and E'
INC rB5 AC AC + 1, SC 0 Increment AC

SPA rB4 if(AC(15)=0) then (PC PC + 1), SC 0 Skip next instruction if AC positive

SNA rB3 if(AC(15)=1) then (PC PC + 1), SC 0 Skip next instruction if AC negative
SZA rB2 if(AC=0) then (PC PC + 1), SC 0 Skip next instruction if AC zero
SZE rB1 if(E=0) then (PC PC + 1), SC 0 Skip next instruction if E zero
ECEg431 - Computer Architecture and
HLT rB0 S 0, SC 0 Organization Halt Computer 28
Memory Reference Instruction
Basic Computer Instructions
Symbol Control Operation Description
AND D0T4 DR M[AR] AND memory word to AC

D0T5 AC AC DR, SC 0

ADD D1T4 DR M[AR] ADD memory word to AC

D1T5 AC AC + DR, SC 0

LDA D2T4 DR M[AR] Load memory word to AC

D2T5 AC DR, SC 0

STA D3T4 M[AR] AC, SC 0 Store content of AC in memory

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 Memory Reference Instruction
Basic Computer Instructions
Symbol Control Operation Description
BUN D4T4 PC AR, SC 0 Branch unconditionally

Branch and save return

BSA D5T4 M[AR] PC, AR AR +1 address
D5T5 PC AR, SC 0

ISZ D6T4 DR M[AR] Increment and skip if zero

D6T5 DR DR + 1
D6T6 M[AR] DR, SC 0
if(DR = 0) then (PC PC +
1)

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Memory Reference Instruction Summary

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Operation Flow Chart

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Design of Basic Computer

Design of Bus Structure

Design of Control Logic Gates

Design of Accumulator Logic

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Inputs to Control Logic Gates

Two decoders

8 bit instructions (D0 D7)

16 bit sequence (T0 T15)

Seven flip-flops

I, S, E, R, IEN, FGI, FGO

IR bits 0 through 11

AC bits 0 through 15

DR bits 0 through 15

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Outputs of Control Logic Gates

Control inputs of nine registers

AR, PC, DR, AC, IR, TR, OUTR, INPR, SC

Control Read & Write inputs of memory

Set, Clear or Complement flip-flops

Bus selectors S2, S1, and S0

Control AC adder and logic circuit

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Design of Control Logic Gates

Control of Registers

Control of Memory

Control of Flip-Flops

Control of Common Bus Selectors

Control to AC

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 Control of Registers

DR

LD
D0T4 DR M[AR]
D1T4 DR M[AR]
D2T4 DR M[AR]
D6T4 DR M[AR]

INC
D6T5 DR DR + 1

CLR

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 Control of Registers

IR

LD
RT1 IR M[AR]
RT1 IR M[AR]

INC

CLR

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 Control of Registers

AR

LD
RTo AR PC
R T2 AR IR(0-11)
D7IT3 AR M[AR]

INC
D5T4 AR AR + 1

CLR
RT0 AR 0

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Circuits Associated with AC

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AC Control Gates

Statements that alter AC content

Load AC
D0T5 AC AC DR

D1T5 AC AC + DR
D2T5 AC DR
pB11 AC(0-7) INPR, FGI 0
rB9 AC AC
rB7 AC shr AC, AC(15)E, E AC(0)
rB6 AC shl AC, AC(0)E, E AC(15)

Increment AC
rB5 AC AC + 1

Clear AC
rB AC 0
11

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 AC Control Gates

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Adder and Logic Circuit

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