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1
Common Combinational Logic Circuits B A a b c d e f g
0 0 1 1 1 1 1 1 0
In addition to the standard logic functions (NAND, 0 1 0 1 1 0 0 0 0
OR, etc) some combinational logic functions are 1 0 1 1 0 1 1 0 1
widely used and are often available as SSI ICs and 1 1 1 1 1 1 0 0 1
as library blocks for ASIC design:
From the truth table we can then write out the sum
a decoder is a circuit with inputs and
of products expressions for each of the outputs:
outputs. The output selected by the input bits
a = AB + AB + AB
(treated as a binary number) is set true and the
b = 1
other outputs are false. This circuit is often used
c = AB + AB + AB
for address decoding.
d = AB + AB + AB
a priority encoder does the inverse operation. e = AB + AB
The output bits represent the number of the f = AB
(highest numbered) input line. g = AB + AB
Exercise: Draw a schematic of a circuit that imple-
a multiplexer copies the value of one of in- ments the above logic function.
puts to a single output. The input is selected by
an -bit input.
Combinational Logic Design with
a demultiplexer does the inverse operation and
copies one input to one of outputs. VHDL
adders, comparators and ALUs (arithmetic VHDL is a Very-complex Hardware Description
logic units) implement the basic arithmetic and Language that we will use to design logic circuits.
logic functions
2
VHDL is case-insensitive. There are many cap- Example 2 - if/then/else
italization styles. I prefer all lower-case. You
Within a process we can use other programming
may use whichever style you wish as long as
language constructs such as if/then/else and
you are consistent.
case statements.
Everything following two dashes -- on a line The next example uses an if/then/else state-
ment in a process:
is a comment and is ignored.
Statements can be split across any number of -- example 2: XOR using if/then/else
lines. A semicolon ends each statement. In- entity example2 is port (
dentation styles vary but an end should be in- x1, x2: in bit ;
dented the same as its corresponding begin y: out bit ) ;
end example2 ;
Entity and signal names begin with a letter fol- architecture rtl of example2 is
begin
lowed by letters, digits or underscore ( ) char- process(x1,x2)
acters. begin
if x1 /= x2
then
A VHDL description has two parts: an entity part y <= 1 ;
else
and an architecture part. The entity part defines the y <= 0 ;
input and output signals for the device or entity end if ;
end process ;
being designed while the architecture part describes end rtl ;
the behaviour of the entity.
Each architecture is made up of one or more pro- which synthesizes to the following:
cesses, all of which execute at the same time (con-
currently). Within each process, statements are exe-
cuted one after the other (sequentially). Relational operators that can be used in expres-
The (a,b) after process is called the sen- sions include = (equal), /= (not equal), >, <, >=,
sitivity list and should include all the signals that and <=. The result of relational operators is of type
might affect the value(s) computed in the process. boolean.
The single statement in this examples single pro- The logical operators (e.g. and) can also be ap-
cess is a signal assignment that assigns the value of plied to values of type boolean. However, note that
an expression to the output signal c. Expressions in general there is no automatic type conversion in
involving signals of type bit can use the logical op- VHDL. For example, boolean values cannot be as-
erators and, nand, or, nor, xor, xnor, and not. signed to bit values and integers cannot be assigned
Parentheses can be used to force evaluation in a cer- to bit vectors.
tain order. Exercise: What schematic would you expect if the /=
To ensure that well end up with a simple combi- were replaced with = ?
national circuit each output signal should be assigned
a value exactly once in the architecture.
Example 3 - Vectors
From this VHDL description a program called a
logic synthesizer can design a circuit that has the re- VHDL also allows signals of type bit_vector
quired functionality. In this case its not too surpris- which are one-dimensional arrays of bits. The next
ing that the result is the following circuit: example is a VHDL description of the 7-segment
LED driver and demonstrates the case statement
and bit vectors.
The resulting hardware doesnt actually execute but this -- example 3: 7-segment LED driver for
point of view is useful when using VHDL for simulation. -- 2-bit input values
3
Exercise: Re-write example 3 so that the architecture
entity example3 is port (
uses only signal assignments.
n: in bit_vector (1 downto 0) ;
seg: out bit_vector (6 downto 0) ) ;
end example3 ;