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Defect: A defect in an electronic system is the unintended difference

between the implemented hardware and its intended design.


Typical defects in VLSI chips are:
1. Process Defects missing contact windows, parasitic
transistors, oxide breakdown, etc.
2. Material Defects bulk defects (cracks, crystal
imperfections), surface impurities, etc.
3. Age Defects dielectric breakdown, electromigration, etc.
4. Package Defects contact degradation, seal leaks, etc.
Defects occur either during manufacture or during the use of
devices. Repeated occurrence of the same defect indicates the need
for improvements in the manufacturing process or the design of the
device. Procedures for diagnosing defects and finding their causes
are known as failure mode analyses (FMA).
Error: A wrong output signal produced by a defective system is
called an error. An error is an effect whose cause is some
defect.
Fault: A representation of a defect at the abstracted function
level is called a fault.
Processingdefects
Missing contact windows
Parasitic transistors
Oxide breakdown ----
Material defects
Bulk defects (cracks, crystal imperfections)
Surface impurities (ion migration) -----
Time-dependent defects
Dielectric breakdown
Electromigration -----
Packaging defects
Contact degradation
Seal leaks. . .

Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -


Semiconductor Devices and Circuits, Wiley, 1981.
Let us consider the testing of a ten-input AND function. Suppose
that we apply an input pattern 0101010101, and observe a 0 output.
This is a correct output, but what can we conclude: the gate under
test is (A) an AND, (B) not a NAND, (C) not a NOR, or (D) not an
OR function?
We could use another pattern, 1111111111, to make sure that the gate
is not a NOR. However, that does not guarantee that the given
circuit will function correctly as an AND gate for all 210 = 1024
possible input patterns.
10
Given ten inputs, it is possible to construct 22 Boolean functions,
and in the present situation our functional test must allow us to
conclude that the function is AND and not one of the others.
A complete functional test will check each entry of the truth
table. Though possible with ten inputs, such a test will be too
long and impossible to use with a real circuit with several
hundred input lines.
use of functional tests is often found necessary for verification of
design.
Back in 1959, Eldred derived tests that would observe the state of
internal signals at primary outputs of a large digital system. Such
tests are called structural because they depend on the specific
structure (gate types, interconnects, netlist) of the circuit.
One of the greatest advantages of structural testing is that it allows
us to develop algorithms. Central to these algorithms are fault
models.
Modelling of faults is closely related to the modelling of the circuit.
In the design hierarchy, the level refers to the degree of abstraction.
Thus, the behavioural level has fewer implementation details and
fault models at this level may have no obvious correlation to
manufacturing defects. High level fault models play a greater role in
the simulation-based design verification, than in testing.
Exceptions are the functional fault models of semiconductor
memories. Since the function of the memory is simple, exhaustive
functional test is possible and is normally used in practice.
The register-transfer level (RTL) or logic level consists of a netlist
of gates and the stuck-at faults at this level are the most popular
fault models in digital testing. Other fault models at this level are
bridging faults and delay faults.
Transistor and other lower levels (referred to as component levels)
include stuck open types of faults that are also known as technology-
dependent faults.
Finally, there are fault models that may not fit any of the design
hierarchies. A typical example is the quiescent current defect.
The usefulness of these models stems from the fact that they can
represent some physical defects not represented by any other model.
Therefore, sometimes these models have been called realistic.
Assertion Fault: An assertion expresses a property of a high-level
function in the form: antecedent consequent, An assertion
fault means that the corresponding property is not true for some
input of the system. This fault model has been used for generating
tests for a microprocessor.
Behavioral Faults: The behaviour of an electronic system is
described in programming language (such as C) or some other
hardware description language. Behavioural faults refer to incorrect
execution of the language constructs used in the description.
Examples of behavioural faults are assertion faults, branch faults,
and instruction faults.
Branch Fault: This fault is modelled at the behavioural level where
the circuit function is described in a programming language. A
branch fault affects a branch statement and causes it to branch to an
incorrect destination.
Bridging Fault: Usually modelled at the gate or transistor level, a
bridging fault represents a short between a group of signals. The logic
value of the shorted net may be modelled as 1-dominant (OR bridge),
0-dominant (AND bridge), or indeterminate, depending upon the
technology in which the circuit is implemented.
Bus Fault: A bus fault specifies the status for each line in a bus as
stuck-at-0, stuck-at-1, or fault-free. Thus, for an n-bit bus, there are 3n
- 1bus faults. A total bus fault assumes all lines of the bus to be stuck
at the same 0 or 1 state.
Cross-point Fault: These faults are modelled in programmable logic
arrays (PLA.) In the layout of a PLA, input and output variable lines
are laid out perpendicular to the product-lines. Crossing signal lines
either form specific types of connections or remain unconnected at
cross-points, depending on the function implemented. Two types of
cross-point faults: A missing cross-point and extra cross-point.
Defect-Oriented Faults: Faults at the physical level that usually occur
during manufacture are called defects. The electrical or logic-level faults
that can be produced by physical defects are classified as defect-oriented
faults. Examples of physical defects are broken (open) wires, bridges,
improper semiconductor doping, and improperly formed devices.
Delay Fault: These faults cause the combinational delay of a circuit to
exceed the clock period. Specific delay faults are transition faults, gate-
delay faults, line-delay faults, segment-delay faults, and path-delay
faults.
Gate-Delay Fault: The fault increases the input to output delay of a
single logic gate, while all other gates retain some nominal values of
delay.
Hyperactive Fault: A hyperactive fault causes a large number of signals
in the circuit to differ from their correct values. The fault thus produces
very high fault related activity in the circuit. If not readily detected, fault
simulators usually remove hyperactive faults for later consideration to
save CPU time and memory.
Initialization Fault: Circuits with memory elements (e.g., flip-
flops) are designed so that they can be initialized by applying
suitable input signals. Faults that interfere with such an initialization
procedure are called initialization faults. A typical example of such
a fault is the clock line of a flip-flop being stuck in the inactive state.
Instruction Fault: Usually modelled in programmable systems like
microprocessors or digital signal processors, an instruction fault
causes an intended instruction to be incorrectly executed.
Intermittent Fault: A fault that appears and disappears as a
function of time is called an intermittent fault. A fracture in an
interconnect may produce an intermittent open for some time before
it becomes a permanent fault.
Line-Delay Fault: This fault models rising and falling delays of a
given signal line. In contrast with the transition fault where the
transition can be propagated through any path, a test for a line-delay
fault must propagate the transition through the longest sensitizable
path.
Logical Faults: These faults affect the state of logic signals.
Normally, the state may be modelled as {0, 1, X (unknown), Z (high
impedance)}, and a fault can transform the correct value to any
other value.
Memory Faults: Faults modelled in memory blocks are single cell
stuck-at-[0,l] faults, pattern sensitive faults, cell coupling faults, and
single stuck-at faults in the address decoder logic.
Multiple Fault: A multiple fault represents a condition caused by
the simultaneous presence of a group of single faults. Frequently
considered multiple faults consist of the same type of single faults.
Non-classical Fault: Although a non-classical fault, in general,
refers to a fault other than a stuck-at fault, the term has been used
for the stuck-open and stuck-short faults of MOS technologies.
Oscillation Fault: These faults cause oscillating signals in the
faulty circuit when the fault-free circuit remains stable. Such a
condition can occur due to certain single stuck-at faults in sequential
circuits that contain combinational feedback.
Parametric Fault: Such a fault changes the values of electrical
parameters of active or passive devices from their nominal or
expected values. Examples are the threshold voltage of a transistor
(active device) and values of resistors and capacitors.
Path-Delay Fault: This fault causes the cumulative propagation
delay of a combinational path to increase beyond some specified
time duration. The combinational path begins at a primary input or a
clocked flip-flop, contains a connected chain of logic gates, and
ends at a primary output or a clocked flip-flop. The specified time
duration can be the duration of the clock period. Propagation delay
is defined for the propagation of a signal transition through the path.
Thus, for each combinational path there are two path-delay faults,
which correspond to the rising and falling transitions, respectively.
Pattern Sensitive Fault: This fault causes an incorrect behaviour in
a certain part of the circuit only when a specific state occurs in some
other part. Usually modelled in memories, a typical example is a
fault condition that prevents writing a 1 in a memory cell when its
physical neighbours have 0s stored in them.
Permanent Fault: Any faulty behaviour that does not change with
time is called a permanent fault. Faults that are not permanent and
affect the circuit only at certain times are called intermittent faults.
Physical Faults: These faults cause physical changes in the circuit.
Examples of physical faults are broken wires, bridges (shorts)
between conductors carrying unconnected signals, shorted or open
transistors, etc.
Pin Fault: When a circuit is modelled as an interconnect of
modules, the terminals of those modules are referred to as pins. Pin
faults are the stuck-at faults on the signal pins of all modules in the
circuit.
PLA Faults: A programmable logic array (PLA) is a physical
implementation of two-level AND-OR combinational logic. The
design consists of three sets of parallel wires: inputs, product-terms,
and outputs. Three types of faults are modelled in a PLA:
1. Stuck-at faults on inputs and outputs.
2. Cross-point faults These occur at the points where product
lines cross input or output lines.
3. Bridging faults Shorting between any set of lines that is not
covered by the extra cross-point faults is classified as a bridging
fault.
Potentially Detectable Fault: When a test is applied to a sequential
circuit, certain faults produce an unknown state at the output when a
deterministic output is expected in the fault-free circuit. This
condition is known as potential (or probabilistic) detection.
Quiescent Current IDDQ Fault: These faults are relevant to the
CMOS technology. In the steady state (i.e., when the gate is not
switching) the CMOS logic gate provides no conducting path
between the power supply and ground. Thus, the steady state
current, also known as the leakage or quiescent IDDQ current, of a
CMOS gate is on the order of only a few microamperes.
Under various fault conditions in the gate, this current can rise by
several orders of magnitude thus allowing fault detection via current
measurement. Faults detectable by this method are called IDDQ
faults.
Race Fault: Stuck-at faults that cause a race condition in the circuit
are called race faults. For a certain initial state and input, the final
state of an asynchronous sequential circuit can vary depending on
specific delays of its logic gates. Such a condition is known as a
race. In the absence of the exact delay values, a logic simulator
usually assumes a unit delay for each gate. When a race condition
occurs, the simulator will place unknown signal values.
Redundant Fault: Consider a combinational circuit. Any fault that
does not modify the input-output function of the circuit is called a
redundant fault. A redundant fault cannot be detected by any test.
Such faults can be removed from the circuit without changing its
output function. Removal of redundant stuck-at faults is often used
for circuit optimization.
Segment-Delay Fault: A segment of length L is a chain of L
combinational gates. Such a segment can be contained in one or
more input to output paths. A segment-delay fault increases the
delay of a segment such that all paths containing the segment will
have a path-delay fault.
Structural Faults: The structure of a circuit may refer to its
topology or to physical geometry. However, the term structural
faults is commonly used not for faults modelled in the layout, but
rather in gate-level interconnects.
Stuck-at Fault: This fault is modelled by assigning a fixed (0 or 1)
value to a signal line in the circuit. A signal line is an input or an
output of a logic gate or a flip-flop. The most popular forms are the
single stuck-at faults, i.e., two faults per line, stuck-at-1 (s-a-1 or
sal) and stuck-at-0 (s-a-0 or sa0.)
Stuck-Open and Stuck-Short Faults: Considering a MOS
transistor as an ideal switch, a defect is modelled as the switch being
permanently in either the open or the shorted state.
Transition Fault: It is assumed that in the fault-free circuit all gates
have some nominal delays and that the delay of a single gate has
changed. The gate delay, usually an increase over the nominal value,
is assumed to be large enough to prevent a passing transition from
reaching any output within the clock period, even when the
transition propagates through the shortest path. Possible transition
faults of a gate are slow-to-rise and slow-to-fall types and hence the
total number of transition faults is twice the number of gates.
Untestable Fault: A fault for which no test can be found is called
an untestable fault. There are two classes of untestable faults:
1. Faults that are redundant
2. Faults that change the input-output behaviour of the circuit but
no test can be found by a given method of testing or test
generation. Initialization faults of sequential circuits belong to
this class
Real defects too numerous and often not analyzable
A fault model identifies targets for testing
Model faults most likely to occur
Fault model limits the scope of test generation
Create tests only for the modeled faults
A fault model makes analysis possible
Associate specific defects with specific test
patterns
Effectiveness measurable by experiments
Fault coverage can be computed for specific test
patterns to reflect its effectiveness
Single stuck-at faults
Transistor open and short faults
Memory faults
Functional faults (processors)
Delay faults (transition, path)
Analog faults (parametric deviations)
Single stuck-at fault: The circuit is modelled as an interconnection
of Boolean gates.
Stuck-at fault assumed to affect only the interconnection between
gates.
Each connecting line can have two types of faults:
stuck-at-1 (s-a-1 ) and
stuck-at-0 (s-a-0)
Thus, a line with a stuck-at-1 fault will always have a logic state 1
irrespective of the correct logic output of the gate driving it.
In general, several stuck-at faults can be simultaneously present in
the circuit. A circuit with n lines can have 3n -1 possible stuck line
combinations, because each line can be in one of the three states: s-
a-1, s-a-0, or fault-free.
Clearly, even a moderate value of n will give an enormously large
number of multiple stuck-at faults. It is a common practice,
therefore, to model only single stuck-at faults. An n-line circuit can
have at most 2n single stuck-at faults.
Definition: Three properties (or assumptions) characterize a single
stuck-at fault:
1. Only one line is faulty.
2. The faulty line is permanently set to either 0 or 1.
3. The fault can be at an input or output of a gate.
Example 2.1: Consider the circuit of Figure 2.1. A stuck-at-1 fault as
marked at the output of the OR gate means that the faulty signal
remains 1 irrespective of the input state of the OR gate.
If the normal output of the OR
gate is 1, as it would be if the
inputs were 01, 10, or 11, then
this fault will not affect any
signal in the circuit. However,
a 00 input to the OR gate will
produce a 0 output in the
normal circuit. The faulty Fig. 2.1: Example of a single
circuit will have a 1 there. stuck-at fault
Notice that gates are assumed to function correctly. Only the signal
interconnects are considered to be faulty. The above circuit has
seven lines, which are the potential sites for single stuck-at faults.
The number of possible faults is 14. As the next example shows,
fanouts give rise to additional fault sites.
Example 2.2: Consider the exclusive-OR function implemented by
the circuit of Figure 2.2. As shown, the single fault h s-a-0 is
detectable by a 10 input. The 10 input also activates single s-a-0
faults on g and i.

But, only g s-a-0 is


detectable by this input. The
effect of fault i s-a-0 is
blocked from propagating to
the primary output z by f = 0
which uniquely sets k = 1.
Fig. 2.2 Single Stuck at Fault
We notice that the faults on the fanout branches of a net are not
identical. In a logic circuit, a net contains a stem or source (g in this
circuit) and fanout branches (h and i.) The stem is the output of some
gate and fanout branches are inputs of some other gates. To consider
all possible faults, we model single stuck-at faults on the stem and all
fanout branches of the net. Considering all nets in the circuit, this is
equivalent to modelling faults on inputs and outputs of all gates.
The exclusive-OR circuit of Figure 2.2 has 12 fault sites and hence we
would model 24 single stuck-at faults in this circuit. To reduce this
number, we will use the concepts of fault equivalence and fault
dominance.
Fault Equivalence: Let us consider a single-output combinational
circuit with n input variables. We will denote its output function as f0
(V) where V is an n-bit Boolean vector. To consider two faults,
designated as fault 1 and fault 2, let the output function in the presence
of fault 1 be f1 (V) and that in the presence of fault 2 be f2 (V)
Any test V for fault 1 must produce different values for f0 (V) and f1
(V). This condition can be expressed as:
2.1
Similarly, a test for fault 2 must satisfy
2.2

When fault 1 and fault 2 have exactly the same tests, i.e., all vectors
that satisfy Equation 2.1 and 2.2, and vice-versa, then the Boolean
functions on the left hand sides of the two equations are identical.
That is,
2.3

With some manipulation this leads to


2.4

Equation 2.4, known as the indistinguishability condition, shows


that the two faulty functions are identical when the faults have the
same set of tests.
Definition, Fault equivalence: Two faults of a Boolean circuit are
called equivalent iff they transform the circuit such that the two
faulty circuits have identical output functions. Equivalent faults are
also called indistinguishable and have exactly the same set of tests.
Equivalence of Single Stuck-at Faults: Equation 2.4 can determine
the equivalence of any pair of faults. For an n line circuit that has 2n
single stuck-at faults, we will have to apply this equation to 2(n2- n)
pairs of faults to determine all equivalences. Besides, manipulations
of large Boolean functions can be cumbersome.
Alternatively, if we determine equivalences among faults of simple
Boolean gates, then those results can be applied to arbitrarily large
circuits.
Consider a k input AND gate. It has k + 1 s-a-0 faults on its input
and output lines. Each s-a-0 fault transforms the AND gate to a
constant 0 output function. Thus all s-a-0 faults are equivalent. No
such equivalence relation is found among the k + 1 s-a-1 faults.
Similar analysis of other Boolean gates leads to the equivalences
shown in Figure 2.3, which also includes connecting wire and fanout
that are necessary components for a circuit. A two-way arrow shows
pair-wise equivalence. Note that the NOT gate is identical to a
single-input NAND or NOR gate. The wire (or a non-inverting
buffer) is identical to a single-input AND or OR gate.

Fig 2.3: Equivalent fault collapsing for Gates


Fan-out case: Let us denote the stem signal as a and the two fanout
branches as y and z. We specify its function as (y = a , z = a).
Consider the three s-a-0 faults all of which are tested by an input 1.
The output functions and tests for these faults are summarized in Table
2.1, which also includes a multiple s-a-0 fault of the two branches.
The test outputs containing fault effects are shown as 1/0, meaning a
fault-free state 1 and faulty state 0. It is evident from Table 2.1 that the
three single s-a-0 faults of the fanout have neither the same test nor the
same faulty function. However, the stem fault a s-a-0 is equivalent to
the multiple s-a-0 fault of the two branches. Similar arguments apply
to the s-a-1 faults in the fanout.

Table 2.1: Stuck at -0 faults of a fanout structure


Fault Collapsing: The set of all faults in a circuit can be partitioned
into equivalence sets, such that faults in an equivalent set are
equivalent to each other. Equivalence sets divide faults into disjoint
sets because if a fault exists in two equivalence sets then those sets
can be merged together as one equivalence set.
The process of selecting one fault from each equivalence set is
called fault collapsing. The set of selected faults is known as the
equivalence collapsed set. The relative size of the equivalence
collapsed set with respect to the set of all faults is the collapse ratio:

Example: Equivalence fault collapsing: Figure 2.4 shows two


circuits, one without a fanout and the other with fanouts. Fault
collapsing is performed in a level-by-level pass from inputs to
output using local gate fault equivalences shown in Figure 2.3.
The procedure begins at primary inputs and a gate is not processed
until all gates feeding its inputs have been processed. At a gate, first
input faults are examined. Only one among the equivalent faults is
retained. Then any input faults that are equivalent to some output
fault are deleted. Note that the collapse ratio is around 50 or 60%
and that more reduction occurs in the absence of fanouts.

Fig. 2.4: Example of Fault Collapsing


Example Fault collapsing by functional equivalence: Figure 2.5
shows a gate level implementation of an exclusive-OR (XOR)
circuit in which faults have been collapsed by the procedure of the
last example. Faulty output functions corresponding to four s-a-1
faults, F1, F2, F3, and F4, are also shown. We find that F1 and F4
are equivalent and F2 and F3 are equivalent. Such equivalences,
where fault sites have no directed path in between, can be found by
using Equation 4.4.

Fig. 2.5 Functional equivalence fault collapsing


Fault Dominance and Checkpoint Theorem: Figure 2.6 shows a
three-input AND gate for which we will analyze two single s-a-1
faults shown as Fl and F2. Suppose that T(F1) is the set of all tests
for Fl and T(F2) is the set of all tests for F2. T(F1) contains one
vector and T(F2) has seven vectors. As shown in Figure 2.6, T(F2) is
larger and completely contains T(F1). According to the following
definition, fault F2 dominates fault Fl.
Definition: Fault dominance: If all tests of fault F1 detect another
fault F2, then F2 is said to dominate F1. The two faults are also
called conditionally equivalent with respect to the test set of F1.
When two faults F1 and F2 dominate each other, then they are
equivalent

Fig. 2.6 fault F2 dominates fault F1


Alternative form of fault collapsing, known as dominance fault
collapsing, we further eliminate the dominating faults from the
equivalence collapsed set. For the AND gate shown in Figure 2.6,
we will thus eliminate the s-a-1 fault from the output. The figure
also shows the three-input AND gate with four faults left after
dominance fault collapsing. Since the output s-a-0 is equivalent to
any input s-a-0 we have moved all faults to inputs. Similar
collapsing is possible for all other Boolean gates. Thus we can
summarize dominance fault collapsing as:
1. An n-input Boolean gate requires n + 1 single stuck-at faults to be
modelled.
2. To collapse faults of a gate, all faults from the output can be
eliminated retaining one type (s-a-1 for AND and NAND; s-a-0 for
OR and NOR) of fault on each input and the other type (s-a-0 for
AND and NAND; s-a-1 for OR and NOR) on any one of the inputs.
3. The output faults of the NOT gate, the non-inverting buffer, and the
wire can be removed as long as both faults on the input are retained.
No collapsing is possible for fanout.
Example: Dominance fault collapsing: Figure 2.7 shows the
application of the above rules of dominance fault collapsing to the
circuits without and with fanouts.
Collapsing is done in an output to input pass. A comparison with
Figure 2.4 shows the lower collapse ratio for dominance fault
collapsing. For the fanout-free circuit, the collapsed fault set only
contains input faults. This is an important result. For the circuit with
fanouts, the collapsed set contains faults located at checkpoints
defined below.

Fig 2.7:
dominance
fault
collapsing
Theorem: Fault detection in fanout-free circuit.
A test set that detects all single stuck-at faults on all primary inputs
of a fanout-free circuit must detect all single stuck-at faults in that
circuit.
Checkpoints: Primary inputs and fanout branches of a
combinational circuit are called the checkpoints.
Checkpoint theorem: A test set that detects all single stuck-at faults
of the checkpoints of a combinational circuit detects all single stuck-
at faults in that circuit.
Proofs of these theorems can be constructed from the notions of
fault equivalence and dominance. Checkpoints provide a starting set
for dominance fault collapsing in which further reduction is possible
with the three rules specified above.
structural testing with stuck-at fault model helps in reduction of the
number of test patterns
If there are n nets in a circuit then there can be 2 n stuck-at faults
and one test pattern can verify the presence/absence of the fault.
One pattern can test multiple stuck-at faults, implying the total
number of test patterns required is much lower than 2 n.
Consider the example of an AND gate in Figure 1, with all possible
stuck-at-0 faults. To test the fault at I1, input pattern is I1=1,I2=1; if
the output is 0, s-a-0 fault in I1 is present, else it is absent. Now, also
for the s-a-0 fault in net I2, the pattern is I1=1,I2=1. Same, pattern
will test the s-a-0 fault in the output net O. So, it may be stated that
although there are three s-a- 0 faults only one pattern can test them.
In other words, keeping one fault among these three would suffice
and these faults are equivalent.
Two stuck-at faults f1 and f2 are called equivalent iff the output
function represented by the circuit with f1 is same as the output
function represented by the circuit with f2. Obviously, equivalent
faults have exactly the same set of test patterns.
However, an interesting case occurs for fanout nets. The faults in the
stem and branches are not equivalent.
Figure 3 shows the stuck-at faults in a fanout which drives two nets
and the corresponding test patterns.

if s-a-0 fault is in the


stem, function of stem is
I1=0 and for the branch
I1' (I1) function is I1'=0
(I1=0). So, fault at stem
results in same output
functions of the stem and
the branches.
However, if fault is in branch I1', then function of stem is I1=0/1 (as
driven) and for the branch I1' (I1) function is I1'=0 (I1=I1). So
output function of I1' is different from I1 and I1. Similar logic
would hold for s-a-1 fault.
Let us consider a circuit and observe the reduction in the number of
faults by collapsing using fault equivalence. Figure 4 gives an
example of a circuit without any fanout and illustrates the step wise
collapsing of faults.
Step1: Collapse all faults at level-1 gates (G1 and G2). In the AND
gate G1 (and G2) the s-a-0 faults at output and one input (first) are
collapsed; s-a-0 fault is retained only at one input (second).
Step-2: Collapse all faults at level-2 gates (G3). In the OR gate G3
the s-a-1 faults at output and one input (from G1) are collapsed; s-a-
1 fault is retained only at one input (from G2).
Now we consider a circuit with
fanout.
Step1: Collapse all faults at
level-1 gate (G1). In the AND
gate G1 the s-a-0 faults at
output and one input (first) are
collapsed; s-a-0 fault is
retained only at one input
(second).
Step-2: Collapse all faults at
level-2 gates (G2). In the OR
gate G2 the s-a-1 faults at
output and one input (from G1)
are collapsed; s-a-1 fault is
retained only at one input
(from fanout net).
If all tests of a stuck-at fault f1 detect
fault f2 then f2 dominates f1. If f2 dominants f1 then f2 can be
removed and only f1 is retained.
Let us consider the example of an AND gate with s-a-1 faults in the
inputs and output. To test the s-a-1 fault in the input I1 of the gate, test
pattern is I1=0,I2=1. Similarly, for the s-a-1 fault in the input I2 of the
gate, test pattern is I1=1,I2=0.
But for the s-a-1 fault in the output
of the gate, test pattern can be one
of the three (i) I1=0,I2=0, (ii)
I1=1,I2=0 (iii) I1=0,I2=1. So s-a-1
fault at the output dominates the s-
a-1 faults at the inputs. So
collapsing using dominance would
result in dropping the s-a-1 fault at
the output and retaining only the
faults at inputs.
Figure 7, illustrates dominant faults in AND, NAND , OR , and
NOR gates and fault which can be collapsed.
Figure 8 illustrates fault collapsing using dominance for the circuit without
fanout.
Step1: Collapse all faults at level-
1 gates (G1 and G2). In the AND
gate G1 (and G2) the s-a-1 faults
at output is collapsed; s-a-1 faults
is retailed only at the inputs.
Step-2: Collapse all faults at
level-2 gates (G3). In the OR gate
G3 the s-a-0 fault at output is
collapsed and the s-a-0 faults at
the inputs are retained. It may be
noted that the s-a-0 faults at
inputs of G3 are retained
indirectly by s-a-0 faults at the
inputs of G1 and G2 (using fault
equivalence).
Now we consider the circuit with fanout given in Figure 9 and see
reduction in the number of faults by collapsing using fault
dominance.

Step1: Collapse all faults at


level-1 gate (G1). No faults can
be collapsed.
Step-2: Collapse all faults at
level-2 gates (G2). In the OR
gate G2 the s-a-0 fault at the
output is collapsed, as s-a-0
fault at the inputs are retained;
s-a-0 fault from the fanout
branch is retained explicitly
and the one at the output of
gate G1 is retained indirectly
by s-a-0 faults at the inputs of
G1 (using fault equivalence).
The following can be observed after faults are collapsed using
equivalence and dominance:
A circuit with no fanouts, s-a-0 and s-a-1 faults is to be
considered only at the primary inputs. So in a fanout free circuit
test patters are 2. (Number of primary inputs).
For circuit with fanout, checkpoints are primary inputs and
fanout branches. Faults are to be kept only on the checkpoints.
So a test pattern set that detects all single stuck-at faults of the
checkpoints detects all single stuck-at faults in that circuit.
Points 1 and 2 are termed as check point theorem.
Equivalence Example
sa0 sa1 Faults
sa0 sa1
removed by
sa0 sa1 equivalence
collapsing
sa0 sa1 sa0 sa1
sa0
sa0 sa1 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1


sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32
Dominance Example
sa0 sa1 Faults in blue
sa0 sa1
removed by
sa0 sa1 equivalence
collapsing
sa0 sa1 sa0 sa1
sa0
sa0 sa1 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1 Faults in


sa0 sa1 red
sa0 sa1 removed by
sa0 sa1 dominance
sa0 sa1 collapsing
15
Collapse ratio = ----- = 0.47
32