Lane Manager

Q[31:0]
a[8:0]

b[8:0] Data storing block

FIFO
[23:0]store
c[8:0]

d[8:0] clk
FIFO

rst_b

BLOCK DIAGRAM OF LANE MANAGER

Input/output Behaviour Requirement from the Designing Module:-

Inputs :- a, b, c and d(each 9 bits long)

Clock signal and rst_b(reset) signal

Output Q (which is input to the FIFO block) is a 32 bits signal.

The first bit of 9 bits (i.e. 0th bit) of each of the inputs denotes the validity of the bit.

If first bit =

1 - Valid

0 - Invalid

When clock signal is obtained, if the first bit of the input is valid then the remaining 8 bits data will be
stored in data storing register otherwise the 8 bits data will be discarded .
Then at the application of next clock it will look for the next valid bit and the cycle repeats at every
positive edge of the clock signal. Thus at the time when the value of stored bits get 32 bits, it will
become the output [31:0] Q which will be given to the FIFO block as shown in the block diagram.

Solving the design problem:

a, b, c, d each of 9 bits are taken as the input.

status[1:0] is taken as the count of the already stored bytes

store is taken as a temporary register of 24 bits which will temporarily store the bits.

Q of 32 bits is taken as the output.

Pass is taken as the output of the flip flop.

When RST_b = 0

Set all the outputs to be zero.

Else

For all the possible combinations of the first bit of each input and previously stored bytes output will
be taken and each time status and pass is updated.

For instance

if (a[0]==0 && b[0]==1 && c[0]==0 && d[0]==1)

begin

if(status=='d0)

begin

store[7:0]<=b[8:1];

store[15:8]<=d[8:1];

status<='d2;

f<=1'b0;

end
 else

if(status=='d1)

begin

store[15:8]<=b[8:1];

store[23:16]<=d[8:1];

status<='d3;

pass<=0;

end

else

if(status=='d2)

begin

Q[31:0]<={d[8:1],b[8:1],store[15:0]};

store[23:0]<='h000000;

status<='d0;

pass<=1;

end

else

if(status=='d3)

begin

Q[31:0]<={b[8:1],store[23:0]};

store[23:16]<='h00;

store[7:0]<=d[8:1];

status<='d1;

pass<=0;

end
 end

In the above case, b[0] & d[0] represents the valid bit and rest are invalid. Now there are 4 cases

i) If status=0, it means already stored bytes are 0 i.e. nothing is stored in the temporary
stored register.
So,
Bits b [8:1] gets stored in register store [7:0] memory location,
Bits d [8:1] gets stored in register store [15:8] memory location,
Updated value of status becomes 2 &
Updated value of pass will be 0

ii) If status=1, it means already stored bytes are 1 i.e. 1 byte is already stored in the
temporary register at store [7:0] memory location.
So,
Bits b [8:1] gets stored in register store [15:8] memory location,
Bits d [8:1] gets stored in register store [23:16] memory location,
Updated value of status becomes 3 &
Updated value of pass will be 0

iii) If status=2, it means already stored bytes are 2 and there are 2 valid bits thus in this case
pass will be 1 and output of the block will be as follows:-
Q [7:0] = store [7:0]
Q [15:8] =store [15:8]
Q[23:16] =b [8:1]
Q[31:24] =d [8:1]
Updated value of status becomes 0 &
Updated value of pass will be 1

iv) If status=3, it means already stored bytes are 3 and there are 2 valid bits thus 4 of them
will be output and 1 will get stored in the temporary register at store [7:0] memory
location like this:-
Q[23:0] =store [23:0]
Q [31:24] =b [8:1]
store [7:0] =d [8:1]
Updated value of status becomes 1&
Updated value of pass will be 1

Thus in the similar way all possible cases are written.