Custom IC Design Tutorial Using

SYNOPSYS Custom Designer and HSPICE

for 28/32nm node

Prepared by: Ibrahim I. Abdo / Eng. Hazem W. Marar

Introduction
In this tutorial, you will design and simulate a CMOS inverter using 28/32nm technology and
Synopsys Custom Design Tools. The tutorial includes the detailed steps of schematic design,
layout design and HSPICE simulations.

Connecting to the server

In order to use Custom Designer, your computer should be connected to the university server or
use the computers that have Red Hat Linux OS in the PC-Lab. However, you will need a student
account to login to the server. Contact the course instructor (Dr. Khaldoun Abu Gharbieh) or the
course teaching assistant (Eng. Hazem Marar) for login info.

Starting Custom Designer (cdesigner)

Setup
If you are inside PSUT, then you can proceed to the following section. However, if you would
like to connect from outside PSUT, then you will need a VPN connection. You can get the VPN
connection details with the login info mentioned earlier. You will not be able to open the
cdesigner without connecting to PSUT server.

From Windows
To run the synopsys packages from Windows operating system you need to download two
applications; Xming and PuTTY. These applications are used to provide SSH communication
with the server that we have at PSUT. Download the applications from the following links:

1- Xming: http://sourceforge.net/projects/xming/
2- Xming fonts: http://sourceforge.net/projects/xming/files/Xming-fonts/
3- PuTTY: http://www.chiark.greenend.org.uk/~sgtatham/putty/download.html

Install and start Xming and its fonts. Xming is a service that runs in background, so you will not
be seeing any graphical interface. Run PuTTY and the screen should look as in fig. 1.
 Fig. 1 PuTTY user interface

After that, expand the SSH tab on the left and enable the X11 Forwarding as seen in fig. 2.

Fig. 2 X11 forwarding

Next, go back to the Session tab and enter your username followed by @172.30.200.203.
You can save the session by choosing a name like synopsys and then click Save as seen in
fig. 3 below. When you want to get access next time, just choose synopsys and click Load
 Fig. 3 adding the username and saving the session

A screen Terminal for the Linux RedHat operating system should appear prompting the user to
enter his password.

From RedHat OS
- Open a terminal window (Right click > Open Terminal)

- Enter the following command:

ssh X <your_user_name>@172.30.200.203

- A message will appear prompting the user to enter the password.

Starting cdesigner
- After entering the password, the following statement will appear:

[<user-name>@psutsynopsys ~]$

-Type the following commands (% is not included in the command):

% cd <work directory>/28nm/

% cdesigner

Note: The work directory name will typically be work. However, the work directory name will
be workdir throughout this tutorial.
The software will start and the window in fig. 4 will appear. This window is called the Custom
Designer Console and it everything starts from here.

Fig.4 Custom Designer Console

Getting Started
When using SYNOPSYS Custom Designer, a certain hierarchy should be followed to get the
work done neatly and correctly. Fig. 5 shows this hierarchy for a simple library.

Fig.5 Custom Designer Hierarchy

Creating a Library
To create a new library for your projects:

- File > New > Library

- The window in fig. 6 will show up
- Fill the name of the library and follow the instructions in fig. 6.

Note: When you name any library, cell, file, session, etc., use alphanumeric characters only.
Using other characters may result in errors in the last steps. Avoid using spaces and use
underscores ( _ ) to separate words.

Note: The name abd in this tutorial represents the username. So when you need to specify a
path (in some later steps), use your username instead of abd.
 Fig. 6 Creating a new library

Creating Categories
When you design a lot of cells within the same library, it may be cumbersome to find a specific
cell. So, as a good practice, you should categorize your cells into groups.

- On the console, go to Tools > Library Manager. This will be the place where all your
work can be accessed.
- From the new window go to Edit > cell category.
- Select a library in the left field, then fill in the category name (ex, CMOS_INVERTER)
and click create.
- Repeat the last step to create other categories.
 Fig. 7 Creating categories

Creating Cell Views

To create a new cell, create a schematic cell view. From the console, go to File > New > Cell
view. The window in fig. 8 will appear.
 - Select you library and the suitable cell category.
- Write the cell name (remember the naming rules).
- Choose the schematic view and the schematic editor.

Fig. 8 Creating a new cell

After pressing OK, the schematic editor will open as in fig. 9.

 Fig. 9 Schematic editor GUI

Tools

Fig. 10 Tools

Tools function:

1. Add instance.

2. Add node.
3. Name wire or node.

4. Add PIN.

5. New Cell view from cell view.

6. Undo.

7. Redo.

8. Move instance.

9. Stretch Instance.

10. Copy cell.

11. Rotate 90 left.

12. Rotate 90 right.

13. Flip horizontal.

14. Flip vertical.

15. Delete Instance.

16. Cut.

17. Copy.

18. Paste.
CMOS Inverter Design
This part will show the design steps of the CMOS inverter. Fig. 11 shows the logic symbol of the
inverter and its circuit diagram.

Fig. 11 CMOS inverter

Schematic Design
Steps:

1. Place instance (component) in the work place, there are two ways:

a. Go to ADD menu > Instance or

b. Press (I) key on your keyboard.

2. You will get the window in fig. 12.

3. In this window, do the following:

a. Select library (SEAD_PDK_32_28).

b. Select Cell (pmos4t).

c. Select view (Symbol).

d. Name the instance (MP1) and specify its parameters (width, length, fingers, etc.)

e. Move the cursor to your workspace and click.

f. The window will stay opened.

g. Repeat steps (3a-3g) but select (nmos4t) and name it (MN1), click cancel to close.
Fig. 12 Adding instance
 Fig. 13 Placing transistors

4. Connect the transistors as in fig. 13:

a. Move the cursor to the red square at the instance terminal you want to connect.

b. Click and Hold the mouse button.

c. Move the mouse to the other terminal you want connected.

d. Release the button.

e. To add a wire to connect wires, go to Add > wire (Or press W on keyboard)
 f. Connect wire.

5. Add pins to the schematic to define the terminals. Go to Add > Pin or (Ctrl+P). Pins can only
be placed on wire ends. When placing a pin after selecting it from the top menu, the bar in fig. 14
will appear at the top of the workspace.

Fig. 14 Pin properties

Fill the information you need under each field (name, pin type, and its orientation). Last step
before getting the final result is to name the wires and nodes. Use tool #3 in fig. 10. Your
workspace should look like that in fig. 15 which is an inverter cell schematic view.

Fig. 15 CMOS inverter schematic

Now we need to create a symbol view for the inverter, so we can use it as single instance in
future designs. While you are in the schematic view, go to Design > New cell view > from cell
view, the screen in fig. 16 will pop up.

Fig. 16 Create symbol cell view from schematic cell view window

Press OK and take a look at the symbol (fig. 17). You may need to modify it when you design
bigger circuits.

Fig. 17 Symbol editing

After creating the symbol, a new view (symbol view) will be added to the cell.

Test Bench
To create a test bench where the inverter cell can be simulated, use the steps below:

1. Create a new cell that and relate its name to test bench (like: *_TB, *_TestBench, etc.). Use
the schematic view (fig. 18).

2. Place the inverter instance inside it. This is the same cell you created under VLSI_HW
library.

3. From the analoglib add:

a. cap

b. vsource

c. vpulse (parameters shown in fig. 19)

d. gnd

Your workspace should look like that in fig. 20.

Fig. 18 Creating the test bench

Fig. 19 vpulse parameters
 Fig. 20 Test bench

Note: Naming the wire is like connecting it to the node that has the same name. That can be very
helpful in designing huge and complex circuits with large number of wires.

Simulations
SYNOPSYS Custom Designer uses the SAE "Simulation & Analysis Environment" simulator.

We need to run two types of simulation on our design:

1. DC sweep analysis. (dc)

2. Transient Analysis. (tran)

To run SAE, from the test bench schematic go to Tools > SAE. This will launch the window in
fig. 21, which consists of three main parts:

1. Design Variables section.

2. Output Section. (Choose the variables to be displayed after simulation).

3. Enabled analysis for this test bench.

Fig. 21 SAE main window

The bar on the right contains the shortcuts for the most commonly used commands in SAE. To
setup simulation options:

1. Choose the appropriate Models for you instances. (Transistors)

a. Go to Setup > Models Files.

b. See window in fig. 22.

c. Click in section one. Use the file browser to determine the directory of your models
library file. (In the example, you will find it under >> work/28nm/hspice/saed32nm.lib)

d. In section two chose your transistor corner type (i.e. TT, FF, SS, SF and FS). Pick TT.

e. Click OK.
 Fig. 22 Model setup Window

2. To select the analysis type:

a. Go to Setup > Analysis, window in fig. 23 will appear.

b. Stay in the General tab.

c. Select tran (For transient analysis). Fill the option like the ones in fig. 23 where:

i. Start Time = when the simulation begins.

ii. Time Step = when to recalculate the variables.

iii. Stop Time = when to stop your simulation.

d. Now check the box at the lower left corner.

e. Click Apply.

f. Select dc (For DC sweep). Fill the option like the one in fig. 24 where:

i. Sweep Variable = the variable you want to change. (Select Source)

ii. Sweep type= describe the relation between sweep points.

iii. Start = min value for the variable.

iv. Stop = the Max value for the variable.

v. Step size= the difference between each two reading.

g. Now check the box at the lower left corner.

h. Click OK.

Fig. 23 Transient simulation window

 Fig. 24 DC simulation window

3. The following step is to choose the desired simulations results. In section TWO in fig. 21, do
the following steps (fig. 25):

a. Click under output field, and write the name for a specific output variable.

b. Click under expression column and choose the node from the schematic, or write an
equation that uses the values of some nodes in that schematic.

c. Under analysis, just check the simulation option. Select the one that applies for this
variable. (For now select both of them dc and tran).

4. Save your simulation options by going to Session > save state, select Openaccess from the
main three options at the top. Then name the state without any spaces in the name. See fig. 26.
 Fig. 25 Simulation setup

Fig. 26 Save State window with the options

To run the simulation:

1. Go to Simulation > Netlist and Run, in the main window of SAE.

2. Simulation time depends on the complexity of the design.

3. A Wave Viewer window will appear. The graphs for the specified output variables will be
plotted in this window.

4. At the lower left corner, there are two tabs. (dc and tran)

5. See fig.27 for the tran tab results.

6. See fig.28 for the dc tab results

Fig. 27 Transient simulation results

 Fig.28 DC simulation results

Layout Design
In this section, we are going to create a layout view for the same inverter. Go to Custom Design
Console. Create a new cell view after selecting the library and cell (i.e. CMOS inverter cell),
select layout view. Click OK and you will get a new window like that in fig. 29 which is the
main window of the layout editor.

Like the schematic editor, we have the shortcut bar to left of the window, see fig. 30. The
object/layer panel on the right side of the window, see fig. 31. All the layers that can be used in
the design are included in that panel.
Fig. 29 Layout editor main window

Fig. 30 LE Tools
 Fig. 31 Object/Layers Panel

Layers marked inside the green rectangles, in figure 31, are the one we are going to use in this
tutorial. The left portion is the color and the look of the layer, the middle portion is the layer
name, and the right portion drw indicates a drawing layer. The meaning of each layer is the
following:

. NWELL: N-type Well.

. DIFF: Diffusion Layer.

. PIMP: P-type Diffusion (to define the P-diffusion type)

. NIMP: N-type Diffusion (to define the N-diffusion type)

. PO: Polysilicon layer.

. M1: is Metal #1 (first level) layer.

. CO: Contact layer.

Steps:

1. Go to Create > Ruler.

2. Measure the dimensions of the object you need to create (Ex. Polysilicon gate). See fig. 32

3. Now go to Create> Rectangle or press R.

4. Select the desired layer (PO) from the layer panel.

5. Draw it according to you measurements in step 2. See fig. 33.

Fig. 32 Ruler placement

 Fig. 33 Drawing the Poly (gate)

Important: In the smaller processes (32nm and below), the gate length is very small. That
makes the gate poly (polysilicon) easy to etch during the fabrication process. The solution is to
protect the active poly (transistor gate) by other dummy poly. These dummy polys do not have
any functional purpose, but they are important for the protection of active gates. One dummy
poly is sufficient for every active poly. However, in this tutorial, two dummy polys will be used.
You can remove one of them to get a more compact design.

Copy the poly two times and place the new polys as in fig. 34. The distance between two polys
must be 0.122m.

Note: This tutorial should not be used as a reference for the design rules. To get the Design Rule
Manual (DRM), do the following:

- In the terminal type the following commands:

% cd /home/<username>/<work directory>/28nm/documentation/
% evince SAED32nm_Disign_Rules_Rev_1.0._02282011.pdf
 Fig. 34 The three polys placement

Exercise: Try to delete one of the dummy polys and to reduce the size of the second dummy as
much as you can.

The PMOS transistor will be placed first. Place the rulers as in fig. 34 and draw the diffusion
layer (DIFF) as in fig. 35. Notice that the width of the transistor is measured along the poly and
the length is the width of the poly.
 Fig. 35 PMOS diffusion layer

DIFF layer determines the area of the diffusion (the etched area), but it does not determine the
type (N- or P-type). So, another layer called PIMP (P-Implant) must be added. This layer covers
the area that will receive the dopants which will result in a P-type material. Fig. 36 illustrates this
layer. Remember to depend on the DRM for the rules.

Fig. 36 The PIMP layer

There are four main process types for CMOS technology: n-well process, p-well process, twin-
well process and triple-well process. The process used here is the n-well process. In this process,
the substrate is P-type by default. Adding NMOS transistors to the circuit can be done by the
implantation process only. However, the PMOS transistors will need an N-type body. So, an N-
well is used to provide the PMOS with the needed N-type body.

Exercise: Read more about the CMOS technologies and the multi-well processes. You can find
them in the text book (3.2.1 in the old edition, 3.2.3 in the new edition)

Add the NWELL layer as in fig. 37.

Fig. 37 NWELL layer placement

Place the NMOS transistor using the NIMP layer as in fig. 38.
 Fig. 38 The NMOS transistor

Note: You can go now to the DRC Design Rule Check section to make sure that your work is
OK. When you work on bigger layouts, try to do the DRC after every step so that the errors will
not stack up at the end.

Add the two taps and start adding contacts and metal1 routes. The contacts have an exact size
(0.042X0.042), so you can make one contact and use it anywhere in the layout by taking a copy
of the closest contact. Contacts have minimum allowed distance from adjacent polys and
diffusions. Check fig. 39 and refer to the DRM for more info.
Metal routes can be realized using the path tool (#2 in fig. 30, shortcut: CTRL+SHIFT+P). This
tool will enable you to connect the parts by a minimum width trace of metal1. If you want to
make a wide metal1 trace, use the rectangle tool. See fig. 40.
 Fig. 39 Placing contacts and metal1 traces

Fig. 40 Adding taps

The polysilicon gate should have a metal1 input port. So, we will connect the poly to the metal1
by a contact. The contact may not be fully enclosed by the poly. However, it must be centered at
the half line of the poly strip. This can be found in the DRM document as a minimum enclosure
of (-0.006m). Check fig. 41. (This is a special case. Other cases can be found in the DRM).
 Fig. 41 poly contact placement

During the design process, you may need a simple, neat way to remember the different nets. This
can be done be naming the metal traces using the label tool. Name the confusing nets using M1
text layer. Fig. 42 shows the complete layout of the inverter.

Fig. 42 completed Layout

Layout Design Rule Check (DRC)
To check that the layout does not violate design rules, follow these steps in the layout editor
window:

1. Go to Verification > DRC >Setup and Run.

2. A window like the one in fig. 43 will pop up. This window is used to set the options for the
DRC (Design Rules Check).

3. Do not change the defaults.

4. Define the path for the Runset file.

a. Click the folder icon to the right of runset field.

b. Browse to the directory of the file.

/<work directory>/28nm/Hercules/drc/saed32nm_1p9m_drc_rules.ev

c. Click OK.

d. Go to custom designer console window. If your design is clean of errors, you will see a
massage like the one in fig. 46.

Fig. 43 DRC Setup and Run window

Fig. 44 DRC control variable tab

Fig. 45 DRC Custom Options tab

 Fig. 46 Message in custom designer console window

f. If your design has layout violations, a window like fig. 47 will pop up.

g. Fig. 47 can also be obtained by going to verification > DRC > Debug. This window
will give you a list of the errors in your design and will help you identify them by
highlighting them as shown in fig. 48.

Fig. 47 DRC debug window

 Fig. 48 Error details and highlighting

Layout vs. Schematic Run (LVS)

Once your design is DRC clean, next step is to do LVS test, which is layout vs. schematic. They
need to match. Make sure all the layout pins have names that match the schematic pin names by
following these steps:

1. Go to Create > Text > Labels.

2. A bar like that in fig. 49 will appear at the top of your workspace.

3. Write the net name in the text field.

4. The texts will appear over the mouse curser. (The text layer type LPP MUST be M1PIN)

5. In the layout editor, click at the layer where the text needs to be attached.

Fig. 49 Text label bar

Note: You can use a rectangle of M1PIN layer to name the ports. Just enter the net name in the
connectivity section. (Press Q to get the connectivity section as in fig. 50).

Note: M1 text layer does not have the same effect as M1PIN.

Fig. 50 Naming the output net

To run LVS:

1. Go to Verification >LVS > Setup & Run.

2. See fig. 51.

3. Do not change the defaults for now.

4. Select the Runset file from the directory ( /<work directory>/28nm/Hercules/lvs/*.ev)

5. Click OK.

6. See figures (52-56) for more details.

7. Fix the mismatch error, and you will see a window like shown in fig. 57. Your design is LVS
clean.
 Fig. 51 LVS setup window

Fig. 52 LVS Setup "Netlisting options"

Fig. 53 LVS Setup "Control variable " tab

Fig. 54 LVS Setup "Custom options" tab

 Fig. 55 Run summary of the LVS

Fig. 56 Error details & mismatch between layout and schematics

 Fig. 57 LVS Debug window and the main custom designer window with no errors

LPE (RC extraction)

The last step before doing post layout simulation is to extract the RC components of the circuit.
These components were not captured by schematic simulations. The only way to reach this point
is to finish the design with clean DRC and LVS. Then in the layout editor, go to Verification >
LPE > Setup and Run, you will get a window like that in fig. 58, with a view of all the tabs in the
following figures (59 61). Fill the options in these windows as shown figures (58-61), and then
click OK. You will get a new editor view like the one in fig. 62. If no errors are shown, the next
step is post-layout-simulation.
Fig. 58 LPE Setup "Main tab"
Fig. 59 LPE Setup "Extraction Options" tab
Fig. 60 LPE Setup "Output Option" tab
Fig. 61 LPE Setup "Custom Option" tab
 Fig. 62 StarRC view (LPE Results)

Create Config view

To run post layout simulation, follow these steps:

1. Go to Custom Designer Console window.

2. File > new Cell view.

3. Select the testbench cell.

4. Moreover, create new cell view under it.

5. Choose Config in view type field.

6. Moreover, Config editor in the second field, see fig. 63.

7. You will get a window like that in fig. 64.

8. In this window, fill empty fields with same data as shown in fig. 64 which are marked with
blue boxes.

9. Click under selected column, in your cell line, and you will see drop down menu.
10. Select starrc from that menu as shown in fig.65 - red marked area.

Fig. 63 New config cell view window

Fig. 64 Config editor window

Fig. 65 Config editor window (selecting view)
 Fig. 66 Custome Designer library manager

Post-layout-Simulation
To start post-simulation open Custome Designer library manager fig. 66, and follow the steps:

1. Right click on Config under Views.

2. From drop menu select, open both.

3. Two windows will open, the one in fig. 65 and another one that look like schematics editor
window.

4. To check if your Config viewpoints to starrc view double click on the inverter cell in
schematics editor view, you will see starrc view.
5. Now in the schematics view window, go to Tools > SAE. (Refer to SAE section for details
how to run simulation).

6. Run the simulation and see the difference between pre-layout-simulation and post-layout-
simulation.

Exercise: Using your CMOS inverter, build a simple ring oscillator as the one shown in fig. 67
following the same procedure. To use your inverter add it as an instance in the schematic view,
and go to create > instance in the layout view. Observe the output of each stage and try to figure
out the delay of your CMOS inverter. Try to make the layout as compact as possible.

Fig. 67 Ring oscillator