Thyne500 - 600 Model Rev10

THYNE500/THYNE600 Model for Power System Stability Studies
THYNE 500/THYNE 600

Model for Power System Stability Studies
10 20.04.2017
09 06.02.2017
08 01.12.2016
07 13.07.2016
06 02.02.2016
05 17.12.2015
04 18.11.2015
Index Modification Date Prepared Checked Approved
TITLE:
THYNE 500/THYNE 600
Model for Power System Stability Studies
Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

Project - Chk. Index / Date Filedate 21.04.2017
Project N - Appr. 01 Page 1 of 25
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Table of content
1 INTRODUCTION ......................................................................................................................3
2 REGULATOR STRUCTURE .......................................................................................................3
2.1 Cascaded regulator (ST8C) ................................................................................................................ 3
2.2 Non-cascaded regulator (ST4C) ........................................................................................................ 4
2.3 Reactive power and power factor regulator ..................................................................................... 5
3 BLOCK DIAGRAM OF THE POWER PART....................................................................................8
4 BLOCK DIAGRAMS OF REGULATOR COMPONENTS ....................................................................9
4.1 Voltage and field current regulator ................................................................................................... 9
4.1.1 Voltage regulator (AVR) ........................................................................................................................ 9
4.1.2 Field current regulator (FCR) .............................................................................................................. 10
4.1.3 Representation of ST8C model........................................................................................................... 12
4.1.4 Representation of ST4C model........................................................................................................... 13
4.2 Reactive power regulator (VAR) ...................................................................................................... 14
4.3 Power system stabilizer (PSS) ......................................................................................................... 15
4.4 Limiters............................................................................................................................................... 17
4.4.1 Instantaneous minimum / maximum field current limiter (UEL.IFU, OEL.IFU) ................................... 17
4.4.2 Load angle limiter (UEL.LA) and PQ-curve limiter (UEL.PQ) ............................................................. 18
4.4.3 Inverse-time generator current limiter (UEL/OEL.IT) .......................................................................... 21
4.4.4 Inverse-time field current limiter (OEL.IFD)......................................................................................... 23
4.4.5 Over fluxing limiter (OEL.FX) .............................................................................................................. 25

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1 INTRODUCTION
This document provides the mathematical models of the THYNE 500/THYNE 600 static excitation
system equipped with a HIPASE Regulator. The regulator can be configured either as a cascaded
structure according to the IEEE standard 421.5 model ST8C or as a non-cascaded structure ac-
cording to model ST4C.
2 REGULATOR STRUCTURE
2.1 Cascaded regulator (ST8C)
Figure 1 shows the principal block diagram of the THYNE 500/THYNE 600 excitation system con-
figured as a ST8C type according to the IEEE standard 421.5.
The model consists of the digital regulator and the power part. Exciter quantities are normalized
with respect to the field current/voltage at nominal load, while the generator model quantities are
normalized with respect to no-load air-gap. Therefore, a re-normalization with the factor KN is intro-
duced.
The regulator consists of a PI-type field current controller (FCR) and a cascaded PID-type voltage
controller (AVR). Both regulators have non-wind-up integrator limits and a bump less change over
between manual mode and auto mode. The PSS output is fed to the summation point of the voltage
regulator. For operating the system within a safe area two pairs of over and under excitation limiters
are provided, namely the AVR.UEL/OEL acting at the voltage summing point:
AVR.UEL: (A) either load angle limiter (UEL.LA) or P/Q-curve limiter (UEL.PQ)
(B) inverse-time generator current limiter on under excited range (UEL.IT)
AVR.OEL: (A) inverse-time field current limiter (OEL.IFD)
(B) inverse-time generator current limiter on the over excited range (OEL.IT)
(C) over fluxing limiter (OEL.FX)
and the FCR.UEL/OEL acting at the field current summing point:
FCR.UEL: instantaneous minimum field current limiter (UEL.IFU)

FCR.OEL: instantaneous maximum field current limiter (OEL.IFU)
Figure 1: THYNE 500/THYNE 600 excitation system model (cascaded regulator).

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2.2 Non-cascaded regulator (ST4C)
Figure 3 shows the principal block diagram of the THYNE 500/THYNE 600 excitation system con-
figured as a regulator type ST4C according to the IEEE 421.1.
Here, the regulator consists of a non-cascaded PID-type voltage controller (AVR) for operation in
auto mode and a PI-type field current controller (FCR) for the operation in manual mode. Both regu-
lators have non-wind-up integrator limits and a bump less change over between manual mode and
auto mode is provided. The PSS output is fed to the summation point of the voltage regulator. For
operating the system within a safe area two different types of over and under excitation limiters can
be configured.
(1) Summation-type limiters:
One pair of over and under excitation limiters AVR.UEL/OEL acting at the voltage summing point:
AVR.UEL: (A) either load angle limiter (UEL.LA) or P/Q-curve limiter (UEL.PQ)
(B) inverse-time generator current limiter on under excited range (UEL.IT)
AVR.OEL: (A) inverse-time field current limiter (OEL.IFD)
and one pair FCR.UEL/OEL acting at the field current summing point:
FCR.UEL: instantaneous minimum field current limiter (UEL.IFU)

FCR.OEL: instantaneous maximum field current limiter (OEL.IFU)
...
Figure 2: THYNE 500/THYNE 600 excitation system model

(non-cascaded regulator with summation type limiters).

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(2) Take over-type limiters:
One pair of over and under excitation limiters that is connected by min/max gates:
UEL: (A) either load angle limiter (UEL.LA) or P/Q-curve limiter (UEL.PQ)
(B) inverse-time generator current limiter on the under excited range (UEL.IT)
(C) instantaneous minimum field current limiter (UEL.IFU)
OEL: (A) inverse-time field current limiter (OEL.IFD)
(D) instantaneous maximum field current limiter (OEL.IFU)
...
(non-cascaded regulator with take over-type limiters).
2.3 Reactive power and power factor regulator
The reactive power regulator (VAR) of the THYNE 500/THYNE 600 excitation system is a PI type
regulator which provides the reference voltage (set-point) for the AVR. If power factor regulator
(PFR) is selected the power factor set-value is recalculated to a reactive power set-value. Figure 3
shows the principal block diagram.

(reactive power and power factor regulator).

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A list of the corresponding input, output and internal signals that can be found in Figure 1 and Fig-
ure 3 as well as in the detailed block diagrams below is given in Table 1.
Symbol Signal name Unit

VT Terminal voltage magnitude p.u.
IT Terminal current magnitude p.u.
IP Terminal current active component p.u.
IQ Terminal current reactive component p.u.
IQj Terminal current reactive component of parallel unit j=1,2, p.u.
P Active power p.u.
Q Reactive power p.u.
w Speed p.u.
q Load angle deg
VC Compensated voltage p.u.
VC,F Filtered compensated voltage p.u.
IF Field current p.u.
VF Field voltage p.u.
VR Regulator output p.u.
IF,F Filtered excitation current p.u.
VREF Reference voltage (set-point) p.u.
IF,REF Reference excitation current (set-point) p.u.
VS PSS output p.u.
VUEL Under excitation limiter output p.u.
VOEL Over excitation limiter output p.u.
QREF Reference reactive power (set-point) p.u.
PFREF Reference power factor (set-point) p.u.
Table 1: Excitation model signals.

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The re-normalization factor KN is calculated as shown in Table 2.

Symbol Parameter name Unit
IF,r Rated generator field current A
(to get rated generator voltage at rated power factor)
IF,ag Air-gap generator field current A
(to get rated generator voltage at the air-gap line)
KN Re-normalization factor KN = IF,r / IF,ag
Table 2: Re-normalization parameter.

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3 BLOCK DIAGRAM OF THE POWER PART
The power part of the THYNE 500/THYNE 600 can be modelled according to the IEEE standard
421.5 as shown in Figure 5.
VR VF
KA
1+sTA
VB1 VB2
VB1max
VT y
y = |KPV VT |
A VSUP
KP B
IN = KC IE
IF FEX = f(IN) 0
SW1 = A for shunt field SW1 VSUP
SW1 = B for external supply
VB2max
IT
y = |KPI IT|
IN = KC IE
IF FEX = f(IN) 0
VSUP
Figure 5: Power part block diagram.
For a typical shunt field supply sample parameters can be found in Table 3.
Symbol Parameter name Value Unit

KA Power stage gain 1.35
TA Controlled rectifier bridge equivalent time constant 0.003 s
SW 1 Power source selector A
KC1 Rectifier loading factor proportional to commutating reactance 0.1
KPV Potential circuit (voltage) gain coefficient 2.0
KPI Potential circuit (current) gain coefficient 0
VBmax1 Maximum available exciter voltage 10 p.u.
KC2 Rectifier loading factor proportional to commutating reactance 0
KI2 Potential circuit (current) gain coefficient 0
VBmax2 Maximum available exciter voltage 10 p.u.
Table 3: Power part model parameters.
In all parameter tables hardware sample data are highlighted in green, sample data for tunable
software parameters are highlighted in blue and fixed equipment parameters are highlighted in red.

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4 BLOCK DIAGRAMS OF REGULATOR COMPONENTS
4.1 Voltage and field current regulator
4.1.1 Voltage regulator (AVR)
The voltage regulator has a PID structure with non-windup limits as shown in Figure 6. The integrator
is deactivated if TI,AVR = 0. The non-windup logic stops the integrator if the output signal VAVR has
reached the upper or lower limit. A list of all corresponding system parameters can be found in Table
4.
Figure 6: Voltage regulator block diagram.
The voltage feedback to the AVR comprises an active and reactive current compensation, which
can be used as line drop or droop compensation. Furthermore, the cross current compensation of
parallel generators can be provided. The corresponding block diagram is shown in Figure 7.
...
Figure 7: Load compensation LDC.
Symbol HIPASE identifier Parameter description Value Unit

a LDC.alpha Active power compensation (droop) factor 0
b LDC.beta Reactive power compensation (droop) factor 0
bj LDC.beta_cj Reactive power compensation (droop) factor for 0
parallel unit j=1,,4

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TFU - Time const. voltage transducer 0.010 s

KP,AVR AVR.KP Proportional gain 5.0
TI, AVR AVR.TI Integrator time constant 1.0 s
KD, AVR AVR.KD Differential gain, voltage controller 0.0
TD, AVR AVR.TD Differential filter time constant 1.0 s
Vmin, AVR - Min. output limit in ST4C configuration -0.8660 p.u.
*)
- Min. output limit in ST8C configuration 0 p.u.
Vmax, AVR - Max. output limit in ST4C configuration 0.9962 p.u.
*)
- Max. output limit in ST8C configuration 1.8 p.u.
Table 4: AVR and load compensation model parameters.
*) In the ST8C configuration in Auto mode the output of the voltage regulator is the set-value of the
field current regulator (inner loop). Therefore, the set-value limit of the field current regulator is the
output limit of the voltage regulator. The lower limit is fixed, while the upper limit is an adjustable pa-
rameter.
In the ST4C configuration the output of the voltage regulator is fed directly to the hardware outputs
(firing pulses) proportional to the firing angle. If no linearization of the firing pulses is selected, then
the output limits correspond to the hard ware firing angle limits of 150 to 5 are Vmin,AVR = 0.0278 and
Vmax, AVR = 0.8333. If the linearization of the firing pulse output is selected the arccos function of the
linearization has to be accounted for yielding different AVR output limit. Since, linearization is the
default configuration the corresponding limits can be found in Table 4.
4.1.2 Field current regulator (FCR)
The field current regulator has a PI structure with non-windup limits as shown in Figure 8. The integra-
tor is deactivated if TI,FCR = 0. The non-windup logic stops the integrator if the output signal VFCR has
reached the upper or lower limit. A list of the corresponding system parameters is provided in Table 5.
Vmax,FCR
IF,REF 1 VFCR
KP,FCR
sTI,FCR +
IF,F +
Vmin,FCR
1
1+sTFI
IF
Figure 8: Field current regulator block diagram.

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Symbol HIPASE Parameter description Value Unit

identifier
TFI - Filter time const. field current transducer 0.005 s
KP,FCR FCR.KP Proportional gain 4.0
TI,FCR FCR.TI Integrator time constant 0.0 s
Vmin,FCR *) - Min. output limit -0.8660 p.u.
Vmax,FCR *) - Max. output limit 0.9962 p.u.
Table 5: FCR model parameters.
*) The output of the field current regulator is fed directly to the hardware outputs (firing pulses) pro-
portional to the firing angle. If no linearization of the firing pulses is selected, then the output limits
correspond to the hard ware firing angle limits of 150 to 5 are Vmin,FCR = 0.0278 and Vmax,FCR =
0.8333. If the linearization of the firing pulse output is selected the arccos function of the lineariza-
tion has to be accounted for yielding different FCR output limit. Since, linearization is the default
configuration the corresponding limits can be found in Table 5.

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4.1.3 Representation of ST8C model
IEEE Symbol Parameter description Calculation Value Unit
RC Resistive component of load compensation -a 0
XC Reactance component of load compensation -b 0
TR Regulator input filter time constant TFU 0.010 s
KPR Voltage regulator proportional gain KP,AVR 5
KIR Voltage regulator integral gain KP,AVR / TI,AVR 5 1/s
VPImax Maximum voltage regulator output Vmax,AVR 1.8 p.u.
VPImin Minimum voltage regulator output Vmin,AVR 0 p.u.
KPA Field current regulator proportional gain KP,FCR 4
KIA Field current regulator integral gain KP,FCR / TI,FCR 0 1/s
VAmax Maximum field current regulator output Vmax,FCR 0.9962 p.u.
VAmin Minimum field current regulator output Vmin,FCR -0.8660 p.u.
KA Power stage gain KA 1.35
TA Controlled rectifier bridge equivalent time constant TA 0.003 s
VRmax Maximum field current regulator output KA * Vmax,FCR 1.3449
VRmin Minimum field current regulator output KA * Vmin,FCR -1.1691
KF Exciter field current feedback gain 1 / KN 0.5
TF Field current feedback time constant TFI 0.005 s
SW 1 Power source selector SW 1 A

Rectifier loading factor proportional to commutating
KC1 KC1 0.1
reactance
KP Potential circuit (voltage) gain coefficient KN * KPV 4.0
KI1 Potential circuit (current) gain coefficient - 0
XL Reactance associated with potential source - 0
qP Potential circuit phase angle (degrees) - 0 deg
VBmax1 Maximum available exciter voltage VBmax1 10 p.u.

KC2 KC2 0
reactance
KI2 Potential circuit (current) gain coefficient KN * KPI 0
VBmax2 Maximum available exciter voltage VBmax2 10 p.u.
Table 6: ST8C correspondence table.

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4.1.4 Representation of ST4C model
RC Resistive component of load compensation -a 0
XC Reactance component of load compensation -b 0
TR Regulator input filter time constant TFU 0.010 s
KPR Voltage regulator proportional gain KP,AVR 5
KIR Voltage regulator integral gain KP,AVR / TI,AVR 5 1/s
TA Thyristor bridge firing control equivalent time constant TA 0.003 s
VRmax Maximum regulator output Vmax,AVR 0.9962 p.u.

p.u.
VRmin Minimum regulator output Vmin,AVR -0.8660 p.u.
p.u.
KPM Forward proportional gain of inner loop field regulator - 1
KIM Forward integral gain of inner loop field regulator - 0 1/s
VMmax Maximum output of inner loop field regulator Vmax,AVR 0.9962 p.u.
p.u.
VMmin Minimum output of inner loop field regulator Vmin,AVR -0.8660 p.u.
p.u.
VAmax Maximum exciter output Vmax,AVR 0.9962 p.u.
p.u.
VAmin Minimum exciter output Vmin,AVR -0.8660 p.u.
p.u.
KG Feedback gain of inner loop field regulator - 0
TG Feedback time constant of field current regulator - 0 s
VGmax Maximum feedback voltage for field current regulator - 0
SW 1 Power source selector SW 1 A

KC KC 0.1
reactance
KP Potential circuit (voltage) gain coefficient KN * KPV * KA 5.4
KI Potential circuit (current) gain coefficient - 0
XL Reactance associated with potential source - 0
qP Potential circuit phase angle (degrees) - 0 deg
VBmax Maximum available exciter voltage VBmax1 10 p.u.
Table 7: ST4C correspondence table.

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4.2 Reactive power regulator (VAR)

The voltage regulator has a PI structure with non-windup limits as shown in Figure 9. The integrator is
deactivated if TI,VAR = 0. The non-windup logic stops the integrator if the output signal VVAR has
reached the upper or lower limit. A list of all corresponding system parameters can be found in Table
8.
Figure 9: Reactive power regulator block diagram.

KP,AVR VAR.KP Proportional gain 0.5
TI, AVR VAR.TI Integrator time constant 1.0 s
Vmin, VAR AVR.setpoint_min Min. output limit (=AVR set-point minimum limit) 0.9 p.u.
Vmax, VAR AVR.setpoint_max Max. output limit (=AVR set-point maximum limit) 1.1 p.u.
Table 8: VAR model parameters.

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4.3 Power system stabilizer (PSS)
The power system stabilizer is a PSS2C type according to IEEE 421.5 as shown in Figure 10. The
corresponding parameters are listed in Table 9. Two sets of parameters can be configured
(x {A,B}).
Figure 10: Power system stabilizer block diagram.
TW1 PSS2 / TW1_x Wash out time constant 1 5.0 s

T6 PSS2 / T6_x Low pass filter time constant 6 0.0 s
T7 PSS2 / T7_x Low pass filter time constant 7 5.0 s
KS2 PSS2 / KS2_x Proportional gain 2 1.0

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T8 PSS2 / T8_x Ramp tracking filter time constant of numerator 0.5 s

T9 PSS2 / T9_x Ramp tracking filter time constant of denominator 0.1 s
M PSS2 / M_x Ramp tracking filter exponent of denominator 5
N PSS2 / N_x Ramp tracking filter exponent of numerator 1
T1 PSS2 / T1_x Lead lag 1 time constant of numerator 0.15 s
T2 PSS2 / T2_x Lead lag 1 time constant of denominator 0.03 s
T13 PSS2 / T13_x Lead lag 4 time constant of denominator 0.0
VSmin PSS / LIML_x Min. PSS output limit -0.05 p.u.
VSmax PSS / LIMH_x Max. PSS output limit 0.05 p.u.
VPSS,on PSS / Pon_level Active power threshold for PSS on 0.2 p.u.
VPSS,off PSS / Poff_level Active power threshold for PSS off 0.15 p.u.
Table 9: Power system stabilizer parameters *).
*) The given values are settings for a specific hydro generator with static excitation system. PSS parameters
must be calculated for every generator individually based on the detailed system parameters (time constants,
reactances, inertia, etc.).

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4.4 Limiters
For the cascaded ST8C regulator structure the limiters are of summation-type with one group
AVR.UEL/OEL acting on the voltage summation point and one group FCR.UEL/OEL acting on the
field current summation point. The composition of the limiter groups is described in Section 2.
For the non-cascaded ST4C regulator structure the limiters can either be configured as summation-
type or as take over-type. If configured as summation-type, there is one limiter group AVR.UEL/OEL
acting on the voltage summation point and one group FCR.UEL/OEL acting on the voltage regulator
output. If configured as take over-type, there is only one limiter group that is acting on the voltage
regulator output. Thereby, the limiter outputs are connected via min- and max-gates. The composi-
tion of the limiter groups is described in Section 2.2.
4.4.1 Instantaneous minimum / maximum field current limiter (UEL.IFU, OEL.IFU)
The instantaneous field current limiter as shown in Figure 11 consists of parallel PI controllers with
non-wind-up integrators. The corresponding parameters can be found in Table 10.
VO,UEL,IFU
IFmin + 1 VUEL,IFU
KP,UEL,IFU
sTI,UEL,IFU +
+
IF 0
IFmax + 1 VOEL,IFU
KP,OEL,IFU
sTI,OEL,IFU +
+
IF
VO,OEL,IFU
Figure 11: Instantaneous field current limiter block diagram.

IFmin Instantaneous min. field current limit in 0.2 p.u.
UEL.IFU.IFmin_auto_load
auto mode
Instantaneous min. field current limit in 0.2 p.u.
UEL.IFU.IFmin_man_load
manual mode
KP,UEL,IFU UEL.IFU.KP Proportional gain 0.5
TI, UEL,IFU UEL.IFU.TI Integrator time constant 0.1 s

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VO, Output limit 1.0 p.u.

-
UEL,IFU
IFmax Instantaneous max. field current limit in 1.0 p.u.

OEL.IFU.IFmax_auto_noload
auto mode off-line
Instantaneous max. field current limit in 1.6 p.u.
OEL.IFU.IFmax_auto_load
auto mode on-line
OEL.IFU.IFmax_man_noload
manual mode off-line
OEL.IFU.IFmax_man_load
manual mode on-line
KP,OEL,IFU Proportional gain of maximum field cur- 0.6
OEL.IFU.KP
rent limiter
TI,OEL,IFU Integrator time constant of maximum 0.1 s
OEL.IFU.TI
field current limiter
VO,OEL,IFU - Output limit -1.0 p.u.
Table 10: Instantaneous field current limiter parameters.
4.4.2 Load angle limiter (UEL.LA) and PQ-curve limiter (UEL.PQ)
The classical under excitation limiter can either be configured as load angle limiter (UEL.LA) or as
PQ-curve limiter (UEL.PQ).
The structure of the load angle limiter is shown in Figure 12. For the calculation of the actual load
angle q, the parameter XQ,LAL can be entered. It determines the base-point of the limiting curve,
while the limiting angle qLIM determines the gradient of the limiting curve. The list of parameters can
be found in Table 11.
Figure 12: Load angle limiter block diagram.

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dmax UEL.LA.delta_max Rotor angle limit 65 deg

TFd - Filter time constant 0.050 s
XQ,UEL,LA UEL.LA.XQ Generator cross reactance for load angle limiter 0.6 p.u.
KP,UEL,LA UEL.LA.KP Proportional gain 0.1
TI,UEL,LA UEL.LA.TI Integrator time constant 0.5 s
VO,UEL,LA - Output limit 1.0 p.u.
Table 11: Load angle limiter parameters.
The structure of the PQ-curve limiter is shown in Figure 13. The limiting curve can be entered by
means of a look-up table with the pairs of P0/Q0, P1/Q1, etc. The list of parameters can be found in
Table 12. It is according to the IEEE standard 421.5 model UEL2 with the correspondence table
found in Table 13.
Figure 13: PQ-curve limiter block diagram.

Pj UEL.PQ.P0j Active power point j=0,1,n in limit curve p.u.
Qj UEL.PQ.Q0j Reactive power point j=0,1,n in limit curve p.u.
K1,UEL,PQ UEL.PQ.k1 Exponent 2
K2,UEL,PQ UEL.PQ.k2 Exponent 2
KP,UEL,PQ UEL.PQ.KP Proportional gain 0.1
TI,UEL,PQ UEL.PQ.TI Integrator time constant 0.5 s
VO,UEL,PQ - Output limit 1.0 p.u.
Table 12: PQ-curve limiter parameters.

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TUP UEL real power filter time constant TFP 0.020 s
TUQ UEL reactive power filter time constant TFQ 0.020 s
TUV UEL voltage filter time constant TFU 0.010 s
Vbias UEL voltage bias - 1
K1 voltage exponent for real power input to UEL table K2,PQL 2

voltage exponent for reactive power output of UEL KP,PQL
K2 2
table
KUF UEL excitation system stabilizer gain - 0
TQref UEL reactive power reference time constant - 0 s
Kfix UEL fixed gain reduction factor - 1
Tadj UEL adjustable gain reduction time constant - 0 s
SW 1 UEL logic switch for adjustable gain reduction - Pos. A
KUI UEL integral gain KP,PQL / TI,PQL 0.2 1/s
KUL UEL proportional gain KP,PQL 0.1
VUImax UEL PI control maximum output VO,PQL 1 p.u.
VUImin UEL PI control minimum output - 0 p.u.

st
TU1 UEL numerator (lead) time constant (1 block) - 0 s
st
TU2 UEL denominator (lag) time constant (1 block) - 0 s
nd
TU3 UEL numerator (lead) time constant (2 block) - 0 s
nd
TU4 UEL denominator (lag) time constant (2 block) - 0 s
VUELmax1 UEL maximum output VO,PQL 1 p.u.
VUELmin1 UEL minimum output - 0 p.u.
VUELmax2 UEL maximum output VO,PQL 1 p.u.
VUELmin2 UEL minimum output - 0 p.u.

th
Pj UEL lookup table real power (j point) Pj p.u.
th
Qj UEL lookup table reactive power (j point) Qj p.u.
Table 13: UEL2 correspondence table.

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4.4.3 Inverse-time generator current limiter (UEL/OEL.IT)
The structure of the inverse-time generator current limiter is shown in Figure 14. The list of parame-
ters can be found in Table 14. The implementation is in accordance to IEEE standard 421.5 model
SCL1C, see correspondence Table 15.
Figure 14: Inverse-time generator current limiter block diagram.

ITmax UEL/OEL.IT.ITmax Generator current limit 1.05 p.u.
TINV,IT UEL/OEL.IT.T_inv Time constant for inverse-time characteristic 50 s
K UEL/OEL,IT - Exponent 1
Q ,db,UEL,IT UEL/OEL.Q_db_neg Lower limit for reactive power dead zone 0.04 p.u.
Q,db,OEL,IT UEL/OEL.Q_db_pos Upper limit for reactive power dead zone 0.04 p.u.
KP,OEL,IT OEL.IT.KP Proportional gain, overexcited range 0.1
TI,OEL,IT OEL.IT.TI Integrator time constant, overexcited range 0.5 s
VO,OEL,IT - Output limit, overexcited range -1.0 p.u.
KP,UEL,IT UEL.IT.KP Proportional gain, under excited range 0.05
TI,UEL,IT UEL.IT.TI Integrator time constant, under excited range 0.3 s
VO,UEL,IT - Output limit, under excited range 1.0 p.u.
Table 14: Inverse-time generator current limiter parameters.

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ISCLlim SCL terminal current pick up level ITmax 1.05 p.u.
TIT terminal current transducer equivalent time constant - 0 s
K SCL timing characteristic factor K ITL 1
TQSCL reactive current transducer equivalent time constant - 0 s
IQmin dead-band for reactive current - 0 p.u.
VSCLdb dead-band for reactive power or power factor Qmin 0.04 p.u.
TINV inverse time delay after pickup TINV,ITL 50 s
TDSCL fixed time delay after pickup - 0 s
SW 1 reactive current/reactive power selector - B
SW 2 fixed time or inverse time selector - B (0)
KPoex SCL proportional gain (overexcited range) KP, ITLp 0.1
KIoex SCL integral gain (overexcited range) KP, ITLp / TI, ITLp 0.2 1/s
KPuex SCL proportional gain (underexcited range) KP, ITLn 0.05
KIuex SCL integral gain (underexcited range) KP, ITLn / TI, ITLn 0.17 1/s
VSCLmax SCL upper integrator limit -VO, ITLp 1.0 p.u.
VSCLmin SCL lower integrator limit VO, ITLn 1.0 p.u.
Table 15: SCL1C correspondence table.

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4.4.4 Inverse-time field current limiter (OEL.IFD)
The structure of the inverse-time field current limiter is shown in Figure 15. The list of parameters
can be found in Table 16. The implementation is in accordance to IEEE standard 421.5 model
OEL3C, see correspondence Table 17. Note, that this model only reflects the activation of the limiter
correctly. The de-activation of the limiter cannot be represented by the OEL3C.
Figure 15: Inverse-time field current limiter block diagram.

OEL.IFD.IFmax_auto_noload Field current pick up level off-line 0.7 p.u.
IFmax,D
OEL.IFD.IFmax_auto_load Field current pick up level on-line 1.05 p.u.
TINV,IFD OEL.IFD.T_inv Time constant for inverse-time 50 s
characteristic
K,OEL,IFD OEL.IFD.K Exponent 1
KP,OEL,IFD OEL.IFD.KP Proportional gain 0.2
TI,OEL,IFD OEL.IFD.TI Integrator time constant 0.3 s
VO,OEL,IFD - Output limit -1.0 p.u.
Table 16: Inverse-time field current limiter parameters.

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ITFpu OEL timed field current limiter pick up level IEmax,D 1.05 p.u.
KSCALE OEL input signal scaling factor - 1
TF OEL field current measurement time constant TINV,IFL 50 s
K1 exponent for OEL error calculation K,IFL 1
KOEL OEL gain - 25
TOEL OEL integral time constant - 1.5 s
KPOEL OEL proportional gain - 1
VOELmax1 OEL integrator maximum output - 0 p.u.
VOELmin1 OEL integrator minimum output VO,IFL -1.0 p.u.
VOELmax2 OEL maximum output - 0 p.u.
VOELmin2 OEL minimum output VO,IFL -1.0 p.u.
Table 17: OEL3C correspondence table.

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4.4.5 Over fluxing limiter (OEL.FX)
The structure of the over fluxing limiter is shown in Figure 16. The list of parameters can be found in
Table 18.
fG OFL-limit VT,lim + VOFL

1
abs Look-up KP,OFL
table sTI,OFL +
+
VT VO,OFL
VT,lim
VT,max
0
fG0 fGmax |fG|
Figure 16: Overfluxing limiter block diagram.

VT,max OEL.FX.Vt_max Flux maximum voltage limit 1.1 p.u.
fG0 OEL.FX.fg_at_Vt0 Flux limiter start frequency 0 p.u.
fGmax OEL.FX.fg_at_Vtmax Generator frequency at generator voltage 1.0 p.u.
maximum
KP,OEL,FX OEL.FX.KP Proportional gain 0.25
TI,OEL,FX OEL.FX.TI Integrator time constant 0.4 s
VO,OEL,FX - Output limit -1.0 p.u.
Table 18: Overfluxing limiter parameters.

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Thyne500 - 600 Model Rev10

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THYNE500/THYNE600 Model for Power System Stability Studies

THYNE 500/THYNE 600

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

2.1 Cascaded regulator (ST8C)

and the FCR.UEL/OEL acting at the field current summing point:

FCR.UEL: instantaneous minimum field current limiter (UEL.IFU)

Figure 1: THYNE 500/THYNE 600 excitation system model (cascaded regulator).

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

2.2 Non-cascaded regulator (ST4C)

(1) Summation-type limiters:

FCR.UEL: instantaneous minimum field current limiter (UEL.IFU)

Figure 2: THYNE 500/THYNE 600 excitation system model

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

(2) Take over-type limiters:

2.3 Reactive power and power factor regulator

Figure 4: THYNE 500/THYNE 600 excitation system model

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

Symbol Signal name Unit

Table 1: Excitation model signals.

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

The re-normalization factor KN is calculated as shown in Table 2.

Table 2: Re-normalization parameter.

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

3 BLOCK DIAGRAM OF THE POWER PART

Figure 5: Power part block diagram.

Symbol Parameter name Value Unit

Table 3: Power part model parameters.

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

4 BLOCK DIAGRAMS OF REGULATOR COMPONENTS

4.1 Voltage and field current regulator

4.1.1 Voltage regulator (AVR)

Figure 6: Voltage regulator block diagram.

Figure 7: Load compensation LDC.

Symbol HIPASE identifier Parameter description Value Unit

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

TFU - Time const. voltage transducer 0.010 s

Table 4: AVR and load compensation model parameters.

4.1.2 Field current regulator (FCR)

Figure 8: Field current regulator block diagram.

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

Symbol HIPASE Parameter description Value Unit

Table 5: FCR model parameters.

Client - Prep. 2015-10-01 Filename THYNE500_600 MODEL REV10.DOCX

4.1.3 Representation of ST8C model

IEEE Symbol Parameter description Calculation Value Unit

RC Resistive component of load compensation -a 0

XC Reactance component of load compensation -b 0

TR Regulator input filter time constant TFU 0.010 s

KPR Voltage regulator proportional gain KP,AVR 5

KIR Voltage regulator integral gain KP,AVR / TI,AVR 5 1/s

VPImax Maximum voltage regulator output Vmax,AVR 1.8 p.u.

VPImin Minimum voltage regulator output Vmin,AVR 0 p.u.

KPA Field current regulator proportional gain KP,FCR 4

KIA Field current regulator integral gain KP,FCR / TI,FCR 0 1/s

VAmax Maximum field current regulator output Vmax,FCR 0.9962 p.u.

VAmin Minimum field current regulator output Vmin,FCR -0.8660 p.u.

KA Power stage gain KA 1.35

TA Controlled rectifier bridge equivalent time constant TA 0.003 s

VRmax Maximum field current regulator output KA * Vmax,FCR 1.3449

VRmin Minimum field current regulator output KA * Vmin,FCR -1.1691

KF Exciter field current feedback gain 1 / KN 0.5

TF Field current feedback time constant TFI 0.005 s