CONFIDENTIAL

FINAL EXAMINATION
SEMESTER 2 SESSION 2014/2015

COURSE CODE : SKEE 1063/SKEU 1063

SUBJECT : ELECTRONIC DEVICES

INSTRUCTOR : MR. SAMURA ALI

DR. ASRUL IZAM
DR. FAUZAN KHAIRI CHE HARUN
MR. JOHARI KASIM
DR. MOHD AZHAR ABDUL RAZAK
MRS. ISMAWATI ABDUL GHANI
DR. NORLAILI MAT SAFRI
DR. MOHD AMRI MD. YUNUS
DR. MASTURA SHAFINAZ ZAINAL ABIDIN
DR. AZLI BIN YAHYA
DR. ZAHARAH JOHARI
MR. MUHAMMAD ARIF ABD. RAHIM
DR. SHAHARIN FADZLI ABD. RAHMAN

PROGRAMME : SKEE / SKEL / SKEM/ SKEU

SECTION : 01 09, SPACE

TIME : 2 HOUR 30 MINUTES

DATE : 2015

INSTRUCTIONS TO CANDIDATE:

PART A : ANSWER ALL (25) QUESTIONS

PART B : ANSWER THREE (3) QUESTIONS ONLY

THIS PAPER CONSISTS OF 17 PAGES INCLUDING THE COVER PAGE

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PART A: ANSWER ALL (25) QUESTIONS [25 MARKS]

Each question is followed by 5 options. Choose the best option for each question and blacken
the correct space on the objective answer sheet.
Q.1 At room temperature, the number of free electrons in an intrinsic semiconductor is
________ than/to the number of holes.
A. higher
B. lower
C. not equal
D. equal
E. sometimes higher, sometimes lower

Q.2 The merging of a free electron and a hole is called _________.

A. covalent bonding
B. lifetime
C. recombination
D. thermal energy
E. merger

Q.3 The resistance of an n-type semiconductor

A. increases if the number of donor atom increases.
B. depends on the number of holes in the valence band.
C. decreases when it is heavily doped.
D. is determined by the frequency of recombination of electron-hole pair.
E. becomes higher when it is exposed to high temperature.

Q.4 Diffusion of free electron across the pn junction of an unbiased diode produces ______.
A. forward bias
B. reverse bias
C. breakdown
D. depletion layer
E. avalanche
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Q.5 The holes that exist in the extrinsic semiconductor are mainly due to the
A. doping with the trivalent atoms.
B. thermal energy.
C. damage of the silicon structure.
D. kinetic energy.
E. conversion of kinetic energy to thermal energy.

Q.6 Which of the following that does not exist/happen at a p-n junction?
A. all spark
B. depletion region
C. dipole
D. diffusion
E. barrier potential

Q.7 Choose the correct statement about the diode in the forward bias.
A. Depletion region is widen.
B. Barrier potential increases.
C. Diode resistance decreases.
D. If the forward biased voltage is too large, avalanche can occur.
E. Diode is short-circuited.

Q.8 PIV of a diode

A. is the maximum limit that can be applied in reverse bias before the diode burns out.
B. is the diode voltage when avalanche occurs.
C. is the minimum voltage needed for the diode to function in reverse bias.
D. is the voltage across diode when it is used in a rectifier circuit.
E is the maximum voltage that can be applied to a diode in forward bias.

Q.9 A clipper circuit is a circuit that will _______.

A. clip the DC level of an ac signal
B. increase the DC level of an ac signal
C. regulate the output voltage
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D. crop part of the input signal
E. convert ac to DC signal

Q.10 Choose the correct statement about a rectifier circuit.

A. It converts ac signal to a non-pulsating DC signal.
B. It is used to increase the DC level of an ac signal.
C. It is the last block of DC power supply.
D. It converts a two-pole signal to a one-pole signal.
E. It amplifies the input signal.

Figure A1 is for questions Q.11 and Q.12.

1kW IL

IZ
VS VZ 2 kW

Figure A1

Q.11 If the zener diode works in the zener region, an increase in VS makes IL ___________
and IZ ____________.
A. larger, the same
B. the same, smaller
C. the same, larger
D. smaller, higher
E. larger, larger

Q.12 If VZ = 12 V and VS = 15 V, the zener diode ________.

A. works as a regulator
B. is in reverse bias
C. is in forward bias
D. burns out
E. acts as a crystal diode
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Q.13 Figure A2 is a block diagram of a particular circuit with the input and output
waveforms shown. The circuit is a _________.

Vi VO

Figure A2
A. rectifier
B. clamper
C. DC power supply
D. regulator
E. combination of several circuits above.

Q.14 What is the average value of the waveform in Figure A3?

VO(V)

1
0

Figure A3
A. 2.27 V
B. 1.91 V
C. 1.27 V
D. 2.12 V
E. 3.12 V
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Q.15 The first transistor was invented in December 1947 at Bell Lab by Walter Brattain,
John Bardeen and
A. Walter OBrien
B. Tony Stark
C. William Shockley
D. Robert Oppenheimer
E. Jean Mc Colland

Q.16 Choose the wrong statement about as used in BJT.

A. is the ratio of IC to that of IE.
B. increases when the collector is heavily doped compared to the emitter.
C. has a value of less than 1.
D. is the percentage of electrons from the emitter that arrives at the collector.
E. The relationship between and is = /(1+)

Figure A4 is for question Q.17, Q.18 and Q.19.

VCC IC
RC
RB
IC

VCE

VCE

Figure A4

Q.17 If Q point is at the centre of the load line, increase in RB will result in _______.
A. Q point moves up toward saturation
B. Q point moves down towards cutoff
C. Q point remains
D. VCE decreases
E. IC increases
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Q.18 If RB is short-circuited the transistor ________.

A. is overheated
B. becomes a super conductor
C. is cut-off
D. still works in the active region
E. Nothing happens.

Q.19 If the transistor saturates, VCE is _________.

A. equal to VCC
B. ideally 0
C. negative.
D. greater than ICRC.
E. equal to VCB

Q.20 An NPN transistor is biased in active mode. Which of the following is correct?
A. VC > VB > VE
B. VE > VB > VC
C. VB > VE > VC
D. VC > VE > VB
E. VB > VC > VE

Q.21 D

Figure A5
Figure A5 is the symbol of a/an _____________ field effect transistor.
A. n-channel depletion
B. n-channel enhancement
C. p-channel depletion
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D. p-channel enhancement
E. bipolar junction

Q.22 S G D

n substrate

Figure A6
Choose the wrong statement about the MOSFET in Figure A6.
A. If VGS is negative, ID > IDSS
B. The gate current is 0 because of the oxide between gate and channel.
C. Transistor acts as an open circuit when VGS is greater than VGS (off).
D. ID is maximum when VGS = 0.
E In the active region, the drain current is equal to the source current.

Q.23 Threshold voltage of an enhancement MOSFET is

A. VGS voltage when drain current is 0.
B. minimum voltage needed for channel starts to form between drain and source.
C. voltage between drain and source at Q point.
D. zero when ID = IDSS.
E positive for an p type enhancement.

Q.24 V1

V2
VO

Figure A7
The diode circuit in Figure A7 performs what logical functions?
A. AND
B. NOR
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C. NAND
D. OR
E. X-OR

Q.25 V

A B

F
A

Figure A8
The transistor circuit in Figure A8 is a/an _________ gate.
A. AND
B. NOR
C. NAND
D. OR
E. X-OR
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PART B: ANSWER THREE (3) QUESTIONS ONLY.

Q.1
(a) Figure Q1-B (a) shows a full-wave rectifier made from silicon diodes (D1, D2,
D3 and D4).

(i) Draw and label the waveform of output voltage, Vo. (4 marks)
(ii) Calculate the average value of output voltage, Vo. (1 mark)
(iii) Determine the peak inverse voltage, PIV, of diode D1. (2 marks)

Vi + +
D
240 Vrms Vsec D
1 2
50 Hz
- -
+
6:1
D D Vo
3 4
-

Figure Q1-B (a)

(b) Design a clamper circuit to perform the function indicated in Figure Q1-B (b) by
completing the connection for silicon diode and DC supply. Determine the
required value of DC supply. (6 marks)

1 F
Input, Vi (V) + + Output, Vo (V)
15 Si
diode 4
0
Vi 0.1M` Vo time
0
time DC
-15 - supply
- -26

Figure Q1-B(b)
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(c) Figure Q1-B(c) shows a Zener diode voltage regulator and its input voltage, Vi.
The minimum and maximum current of zener diode are 0 and 40 mA, respectively.

(i) Determine the range value of RS which allow operation of the voltage
regulator. (5 marks)
(ii) Sketch and label the output waveform, Vo when RS is within the range
determined in question Q.1(c)(i) (2 marks)
(iii) Calculate the maximum power rating of zener diode. (2 marks)
(iv) Sketch and label the output waveform when RS is set at 1.5 k (3 marks)

Vi (V) RS

+ +
25

20 RL Vo
Vi Vz=15 V =2k
-
-
time

Figure Q1-B(c)
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Q.2 Figure Q2-B (a), Q2-B (b) and Q2-B(c) show a C-E (Common Emitter) configuration
of Fixed-bias amplifier, Emitter-bias and Voltage Divider-bias circuit respectively.
R3 C2

Vcc Vo

R2
C1 R4
=100

R1
Vz 20V

ImVp-p A

Figure Q2-B(a)
(a) Figure Q2-B (a) has the following parameters;
R1= 500 W, R2=Unknown, R3=R4=4 kW, C1=C2=10 F, VCC=20V, =100,
VBE=0.7 V and an Ammeter, A shows a current of 5 mA. Determine R2 when
VZ = 25 V. (5 marks)
I=0.27mA

3V

500k

4.8k 3V

Figure Q2-B(b)
(b) Calculate the Current Gain ( and ), and VCE of Figure Q2-B(b) (8 marks)
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Rc

Ro

R1

Vcc Vcc R2 RE

Figure Q2-B(c)
(c) Parameters of Figure Q2-B(c) are VCC = 22 V, R1 = 39 k, R2=3.9 k,
RC=10 k, RD=1k, RE=1.5k, VZ= 25V and =140. Determine VCE.
(10 marks)
(d) What happen to the Q-point of Figure Q2-B (a) and Q2-B(c) when the connection
between VZ and ground is opened.
(2 marks)
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Q.3
(a) Figure Q3-B (a) shows a p-channel enhancement MOSFET using 0.25nm CMOS
technology. Given VGS(th) = -4 V, VGS(on) = -7 V, and ID(on) = 5 mA. Determine:
(i) k (2 marks)
(ii) IDQ, VGSQ, and VDSQ (6 marks)
(iii) VS, VG, and VD (5 marks)

(b) Design a DC bias circuit of the n-channel enhancement MOSFET amplifier of

Figure Q3-B(b) to meet the following specifications:
VDD = 20V; VDSQ = 6 V
MOSFET characteristics:
VGS(th) = 3V; k = kn = 115 A/V2
(i) Calculate VG, slope of bias line (load line), and VGSQ. (6 marks)
(ii) Determine the values of RS, RD, and R1. (6 marks)
The transfer characteristic and bias line are given in Figure Q3-B(c).

-20 V VDD

RD
1.2 kW ID (mA)
R1 RD
bias line
RG
1 MW 4
VDS

RS R2 RS
0.51 kW 1 MW 1.38

3 10 VGS (V)

Figure Q3-B(a) Figure Q3-B(b) Figure Q3-B(c)

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Q.4
(a) The circuits in Figure Q4-B(a) and Figure Q4-B(b) are E-MOSFET digital
switches with two inputs A and B. Determine the digital representation for:
(i) Output P for the circuit in Figure Q4-B(a),
(ii) Output Q for the circuit in Figure Q4-B(b).
(6 marks)
VDD

(INPUT)
A

P
(OUTPUT)

(INPUT)
B

Figure Q4-B(a)

VDD
(INPUT)
A

(INPUT)
B Q
(OUTPUT)

(INPUT) (INPUT)
A B

Figure Q4-B(b)
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(b) Figure Q4-B(c) shows a three-input (A, B, and C) NAND gate of Diode-
Transistor Logic (DTL). X is the output of the DTL.
VCC = 5 V

INPUT 2 k
2 k
D1
R DTL conditions
(OUTPUT)
A - Q1 saturate
D4 D5 VB
VP Q1
D2 when IB 0 A
B
20 k - VCEsat = 0.2V
D3 - VD = 0.65V
C
-2 V
BASE
RESISTOR

Figure Q4-B(c)
(i) Calculate the 20 k base resistor current when:

a. A, B, and C are equal to 0.2V. Show all your working steps.

(5 marks)
b. A, B, and C are equal to 5 V. Show all your working steps.
(5 marks)
(ii) Complete the Table Q4-B by filling in all the blank cells.
(9 marks)
Table Q4-B

Input State Diode State (on or off) VCE(V)

A (V) B (V) C (V) D1 D2 D3 D4 D5 Q1
5 5 0 off
5 0 5 on on
0 5 5
5 5 5 on on 0.2
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APPENDIX 1 - LIST OF EQUATIONS

PIV 2V p ( out) 0.7
1

Vrms
Vp I E I B IC
2
Vp I C I B I CBO
V AVG VDC

Vrms 1
V
r rms
1 r
VDC 2 3 fR L C VDC 4 3 fR L C

Vp Vp
Vr ( pp) Vr ( pp)
fR L C 2 fR L C

I D (ON )
Vr ( pp) k
Vr ( rms)
2 3
VGS ( ON ) VGS (TH )
2

VVD
I D I S e T 1

I D k VGS VGS (TH )

2
VGS 2
I D I DSS 1
V
GS ( OFF )
2
I C
V S
I D I DSS 1 GS
Vp

I C
S VBE
I C S I CO
VBE I CO
 CONFIDENTIAL

FINAL EXAMINATION
SEMESTER 2 SESSION 2014/2015
SOLUTIONS
COURSE CODE : SKEE 1063/SKEU 1063

SUBJECT : ELECTRONIC DEVICES

INSTRUCTOR : MR. SAMURA ALI

DR. ASRUL IZAM
DR. FAUZAN KHAIRI CHE HARUN
MR. JOHARI KASIM
DR. MOHD AZHAR ABDUL RAZAK
MRS. ISMAWATI ABDUL GHANI
DR. NORLAILI MAT SAFRI
DR. MOHD AMRI MD. YUNUS
DR. MASTURA SHAFINAZ ZAINAL ABIDIN
DR. AZLI BIN YAHYA
DR. ZAHARAH JOHARI
MR. MUHAMMAD ARIF ABD. RAHIM
DR. SHAHARIN FADZLI ABD. RAHMAN

PROGRAMME : SKEE / SKEL / SKEM/ SKEU

SECTION : 01 09, SPACE

TIME : 2 HOUR 30 MINUTES

DATE : 2015

INSTRUCTIONS TO CANDIDATE:

PART A : ANSWER ALL (25) QUESTIONS

PART B : ANSWER THREE (3) QUESTIONS ONLY

THIS PAPER CONSISTS OF 11 PAGES INCLUDING THE COVER PAGE

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PART A: ANSWER ALL (25) QUESTIONS [25 MARKS]

Q.1) D
Q.2) C
Q.3) C
Q.4) D
Q.5) A
Q.6) A
Q.7) C
Q.8) A
Q.9) D
Q.10) D
Q.11) C
Q.12) B
Q.13) C
Q.14) A
Q.15) C
Q.16) B
Q.17) B
Q.18) A
Q.19) B
Q.20) A
Q.21) B
Q.22) D
Q.23) B
Q.24) D
Q.25) C
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PART B: ANSWER THREE (3) QUESTIONS ONLY.

Q.1

(a) (i)
Peak of = 2 240 = 339.36
339.36
Peak of = = 56.56
6
Peak of = 56.56 1.4 = 55.16

VO(V)

55.16

0
10 20 30 time (ms)

(a)(ii)
2, 2 55.16
, = = = 35.11
3.142

(a)(iii)

PIV of D1 is when input is in positive cycle.

= , + 0.7 = 55.16 + 0.7 = 55.86
Or
= , 0.7 = 55.56 0.7 = 55.86

(b)
Input signal is shifted downward (magnitude: 11 V) capacitance needs to be charged up to 11V with polarity
as shown belowDiode should be connected according to current direction during capacitor charging
+ VC -

Vi
`

VDC

Assume the polarity of DC supply. KVL when charging of capacitor:

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0.7 = 0
15 11 0.7 = 0
= 3.3

1 F

Si
diode 0.1
M`
3.3 V

Confirmation:
At positive cycle of input: = 0.7 + = 0.7 + 3.3 = 4
At negative cycle of output: = = 15 11 = 26

(c)(i)
Condition1: Turn On zener (Vi min)

15
+
15

15
2 20 2 15

15
0.6667

Condition 2: zener current limit (Vi max)

< 40

< 40


< 40 +

25 15 15
< 40 +
2
10
>
47.5
> 0.2105

0.2105k < RS< 0.6667k

(c)(ii)
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VO(V)

15

0 time

(c)(iii)
=
= 40 15 = 600

(c)(iv)
When RS=1.5 kzener OFF
2
= = = 0.571
+ 2 + 1.5

When Vi=20VVo=11.42V (zener OFF)

When Vi=25VVo=14.28V (zener OFF)

Vo (V)

14.28

11.42

time
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Q.2
a)

b)

c)

d) Zener diode is OFF state. Q-point remains.

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Q.3

(a)
I D ( on)
k
(i)
VGS ( on)
VGS ( th ) 2
5m
0.56 mA/V 2
7 4 2

VGS 20 I D RD RS
(ii) 20 I D 1.2k 0.51k
20 1.71kI D (eqn.1)

I D k VGS VGS (th )

2
(eqn.2)

Substitute eqn.1 into eqn.2

I D 0.46m 20 1.71kI D 4
2

0.56m 1.71kI D 16
2

0.56m 2.92k 2 I D 54.72kI D 256
2

1.64kI D 30.64 I D 143.36m
2

0 1.64kI D 31.64 I D 143.36m

2

31.64 31.64 41.64k 143.36m

2

ID
21.64k
31.64 60.648

3.28k
31.64 7.788

3.28k
12.02mA; 7.27mA

When ID = 12.02 mA, VGS 20 12.02m1.71k 0.55V

When ID = 7.27 mA, VGS 20 7.27m1.71k 7.57V

For p-channel, VGSQ < VGS(th), therefore VGSQ = -7.57 V and IDQ = 7.27 mA
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VDD I D RD VDS I D RS 0
VDSQ VDD I D RD RS
20 7.27m 1.71k
7.57 V
VS I D RS
(iii) 7.27m 0.51k
3.71 V

Since IG = 0 A, therefore for the circuit, VG = VD

VG VD VDS VS
7.57 3.71
11.8 V

(b)

From Figure Q.3(c), VG = 10 V.

Slope of the bias line, m

I D 2 I D1 I DQ
m VGSQ VG
VGS 2 VGS1 m
4m 0 1.38m
0.4m 10 6.55 V
0 10 0.4m

VGS VG VS
VS VG VGS VS 3.45
RS 2.5 k
10 6.55 I D 1.38m
3.45 V

VDD I D RD VDS\ I D RS 0
VDD VDS VS
RD
ID
10 6 3.45
7.65 k
1.38m
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V
R1 GG 1 R2
VG
20
11M
10
1 M
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Q.4
(a)
(i) P A B (3 marks)
(ii) Q A B (3 marks)

(b)
(i)-a If any input goes low (0.2 V), VP= VCEsat + VD= 0.2 + 0.65 = 0.85 V

VB= VP VD4 VD5 = 0.85 0.65 0.65 = 0.45 V.

VBE = VB VE = 0.45 0 = 0.45 V

Region VBE (V) VCE (V) Current Relation

Cutoff < 0.6 Open circuit IB=IC=0

The Q1transistor cuts off.

V 2 0.85 2
I R 20k B = 0.143 mA (5 marks)
20 103 20 10 3

(i)-b If any input goes high (5 V), then the input diodes D1, D2, and D3 are off

VCC = 5 V

INPUT 2 k
R
D1 (OUTPUT)
5V
D4 D5 VB
VP Q1
D2
5V
20 k
D3
5V
-2 V
BASE
RESISTOR

The current from the course Vccnow ows through the 2 k resistorand the diodes D4 and
D5. Let us assume that the base current is IBand it is sucient to cause VB 0.75 V (i.e. due
to saturation of Q1).
Region VBE (V) VCE (V) Current Relation
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Saturation 0.7 to 0.8 0.2 IB IC/hFE

VB 2 0.75 2
I R 20k = 0.138 mA.
20 103 20 103
VP= VB + VD4 + VD5 = 0.75 + 0.75 + 0.75 = 2.25 V

VCC VP 5 2.25
ID4 = 1.4 mA
2 103 2 103

Then the base current IB= ID4 = 1.4 0.138 = 1.538 mA. Which is clearly sucient to drive
the Q1transistor into saturation. (5
marks)

(ii)
Input State Diode State (on or off) VCE(V)
A (V) B (V) C (V) D1 D2 D3 D4 D5 Q1
5 5 0 off off on on on 5
5 0 5 off on off on on 5
0 5 5 on off off on on 5
5 5 5 off off off on on 0.2

(9 marks)