Sachin Ravindran

717 University Avenue SE Apt #306, Minneapolis, MN-55414

+1 (612) 607 9477 | ravin038@umn.edu | www.linkedin.com/in/sachin-joshua

Objective
Seeking job opportunities in Physical Design starting December 2017.

Work experience
CAD INTERN POWER METHODOLOGY | APPLE, AUSTIN MAY 2017 SEP 2017
Worked with vendor and design teams, enhanced flows by 75% run-time reduction in power flows.
Wrappers developed in automating EMIR tool flows infrastructure development & top-level integrity.
Silicon signoff tool experience in analyzing static/dynamic power, grid resistance, EM analysis.
Enhanced user (PD team) experience by integrating vendor tools with a result analyzer for ease of use.
PHYSICAL DESIGN ENGINEER | MICROCHIP TECHNOLOGY, INDIA AUG 2013 AUG 2016
Experienced in library prep, pin placement, floor-planning, placement, clocks, routing, STA, power
EMIR analysis, physical verification, resistance extraction, sensitive analog routing aspects of 7 chips
Taped out full chip projects - Netlist to GDSII. GDS was released to production at 88% util. & 98% yield
Proficient in static timing analysis techniques used for timing closure, noise reduction, congestion fix.
Recognized for quick timing closure and physical verification of chips running behind schedule
Worked closely with IP vendors and analog teams in reducing noise and crosstalk on sensitive nets.
Numerous scripts developed in automating tasks and enhancing routing capabilities of IC compiler.
Worked extensively with the ECO flow, have completed around 6 post-silicon metal revisions.
Certificate of recognition Extraordinary efforts in Area reduction and Die estimation of mask
GRADUATE RESEARCH ASSISTANT(CAD) | UNIVERSITY OF MINNESOTA JAN 2017
Focused on algorithm mapping and complexity reduction techniques of EDA tools CAD research group

Education
MASTERS OF SCIENCE | UNIVERSITY OF MINNESOTA TWIN CITIES AUG 2016 DEC 2017
Major: Electrical Engineering VLSI (GPA 3.9/4.0)
BACHELOR OF ENGINEERING | PES UNIVERSITY BANGALORE AUG 2009 - AUG 2013
Major: Electronics and Communication Engineering (CGPA 8.7/10)

Academic projects
Design of a static timing analyzer tool completely in C++ to find the maximum circuit delay, slew,
slack and critical path of a given netlist-10k gates in 18s https://github.com/Joshua0791/STA--CAD
Implemented a minimum-cut partitioning tool in C++ using simulated annealing algorithm to assist in
standard cell placement and global routing phases https://github.com/Joshua0791/Part--CAD
Design of a 16-bit Han-Carlson adder using Cadence Virtuoso and post layout simulation in Synopsys
HSPICE. The design was optimized in terms of worst case path delay/frequency, total power, and area.
Design and layout of a 11-stage ring oscillator to understand the performance of a 45nm technology node.

Technical skills
Physical design: IC Compiler, PrimeTime, RedHawk, Design Compiler, PrimeRail, Milkyway, STAR-RC
Full custom/Simulation: Cadence Virtuoso, Totem, Calibre DRC/LVS/DFM/PEX/DRV, Synopsys HSPICE
Scripting/Programming: Perl, TCL, C++, Scheme, SKILL, System Verilog, VHDL, C, Java and MATLAB