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UNIVERSAL SHIFT REGISTER

module shiftregister(out,serial,clk,parallel);
output [3:0] out;
input [1:0] serial ;
input [3:0] parallel12
input clk;
reg [3:0] out;
always @(posedge clk)
begin
case(serial)
2'd0: out = parallel ;
2'd1: out = out>>1;
2'd2: out = out<<1;
endcase
end
endmodule

module stimulus;
wire [3:0] out;
reg [3:0] parallel;
reg clk;
reg [1:0] serial;
shiftregister(out,serial,clk,parallel);
initial
clk=1'b1;
always #5 clk=~clk;
initial
begin
serial=0;parallel=4'b1101;
#20 serial=1;
#20 serial=2;
#20 serial=0;parallel=4'b0110;
#20 serial=1;
#20 serial=2;
#20 $finish;
end
initial
$monitor($time,"parallel=%b, clk=%b, serial=%b, out=%b", parallel,clk,serial,out);
endmodule