Networking PCS Catalog

May 2009
Personal Connectivity Solutions
May 2009

Co n n e c t i v i t y S ta n da r d P ro d u c ts page
• IEEE 1394B
FW643E 3
FW420 4
FW430 5
FW843 6
• IEEE 1394A
FW533E 7
FW323 8
FW322 9
FW802 10
• 1394 Cards
FireStorm™ FW643/FW533 11
FireSide™ FW643 ExpressCard™ 12
1394 PC OEM Card 13
• Modem - PC
SV92EX 14
SV92A3 15
SV92U2 16
SV99PP 17
• Modem - Embedded Data
CV22A 18
CV92/34/22 19
• Modem - Embedded FAX
CFAX 20
DP3 21
SFAX 22
• Voice
FX1000 23
• Gigabit Ethernet Transceiver
ET1011C 24
 IEEE 1 3 9 4 B P RODU C T S

FW643E
PCI Express® 1394b
Link / PHY Open Host Controller Interface

F e at u r e s Brief Description LSI provides support for the FW643

n Single chip, integrated Link and
PHY for PCI Express 1394b
n Supports three 1394b 800Mb/s
ports
High performance, pipelined
n
data transfer
n Sustained performance of
87 MByte/s read and 78 MByte/s write
Dedicated asynchronous and
n
with:
The LSI FW643E is a second
generation 1394b OHCI controller n Evaluation adapter board
designed specifically for high
Ready-to-manufacture adapter
performance, PCI Express
n
applications. Based on LSI’s proven card reference design
TrueFire® technology, the FW643E
n Manufacturing test utilities
has enhanced performance and

isochronous descriptor-based
DMA engines power management features to n Configuration EEPROM image
n Large DMA FIFOs deliver improved data transfer rates
Enhanced power management
n
with lower power consumption.
n 480 mW typical power
consumption The FW643E is the fastest 1394b
Full ASPM and CLKREQ power
device and the only single-chip PCI
n

management support
n Single 24.576 MHz. crystal for Express 1394b device available on
lower BOM costs the market today.
n Single 3.3V supply
n Optional configuration EEPROM The FW643E is ideally suited
support
for high-end PC desktops and
n Small form factor Halogen Free
BGA package – 7x7mm footprint notebooks, adapter cards, PC
n Also available in 11x11 mm BGA gaming systems, external disk drive
package for lower-cost board backups, industrial vision systems,
layouts
n Support for Windows and MacOS
and other applications where high
operating systems performance, reliable data transfer
n Supports 8 isochronous contexts is required.
for greater number of concurrent
video streams

Networking PCS Catalog    

 IEEE 1 3 9 4 B P RODU C T S

FW420
1394b PCI Link Open Host Controller Interface

F e at u r e s

n Available in a 120-pin TQFP or — Autonomous configuration

129-pin VTFSBGA lead-free ROM updates.
package. — Enhanced power management support,
n 1394a link and 1394b link: including ack_tardy event.
— Compatible with current Microsoft — Enhanced SelfID protocol, including
Windows® drivers and other selfIDComplete2 event.
common applications.
— Compatible with Microsoft Windows and
— Compatible with existing and MacOS® operating systems.
older, 1394 consumer electronics
and peripherals products. — 4 Kbyte isochronous transmit FIFO.

— Supports low-power system — 2 Kbyte asynchronous transmit FIFO.

designs (CMOS implementation, — 4 Kbyte isochronous receive FIFO.
power management features).
— 2 Kbyte asynchronous receive FIFO.
— Provides LPS, LKON, and CNA
— Dedicated asynchronous and
outputs to support legacy power
isochronous descriptor-based
management implementations.
DMA engines.
— Cycle master and isochronous
resource manager capable.
— Supports 1394a and 1394b Ot h e r F e at u r e s
acceleration features.
n I2C serial ROM interface.
— Provides an 8-bit interface running
n CMOS process.
at 50 MHz for 1394a and 100 MHz
for 1394b. n 3.3 V operation, 5 V tolerant inputs.
n PCI:
— Revision 2.3 compliant.
The FW420 is the LSI imple-menta-
— 33 MHz/32-bit operation.
tion of a high performance,
— Programmable burst size for PCI
data transfer. PCI bus-based open host controller
— Supports PCI Bus Power for implementation of IEEE® 1394b
Management Interface
Specification v.1.1. compliant systems and devices.
— Supports clockrun protocol per Link layer functions are handled
PCI Mobile Design Guide.
by the FW420, utilizing the on-
— Global byte swap function.
chip 1394b compliant link core.
n 1394 OHCI specification revision 1.0
and 1.1: A high-performance and cost-ef-
— Isochronous receive dual-buffer mode. fective solution for connecting
— Enhanced isochronous transmit skip/ and servicing multiple IEEE 1394
over flow support.
(1394—1995, 1394a, and 1394b)
— ack_data_error improvements for
asynchronous and physical requests. peripheral devices can be realized.
— Enhanced CSR control register
implementation.

Networking PCS Catalog    

 IEEE 1 3 9 4 B P RODU C T S

FW430
1394a/b PCI PHY/Link Open Host Controller Interface

F e at u r e s

n 1394a-2000 OHCI link and PHY core n PCI: FW430 Functional Overview
function in a single device: — Revision 2.3 compliant.
— Single-chip link and PHY enables — 33 MHz/32-bit operation. LSI’ s FW430 is a high-performance
smaller, simpler, more efficient
— Supports optimized memory read line,
motherboard and add-in card designs. PCI busbased open host controller
memory read multiple, and memory
— Compatibility with current Microsoft write invalidate burst commands. for implementation of IEEE 1394a
Windows® drivers and common
— Supports PCI Bus Power Management
applications. or 1394b compliant systems and
Interface Specification v.1.1, including
n OHCI: D3cold wakeups. devices. The FW430 features a
— Complies with the 1394 OHCI 1.1 — Supports CLKRUN# protocol per PCI
Specification. switch to select 1394a mode or
Mobile Design Guide.
— Compatible with Microsoft Windows — CardBus support per PC Card Standard 1394b mode. The switch selects
and MacOS® operating systems. Release 8.0, including 128 bytes of on- between a 1394a-2000 compliant
— 4 Kbyte isochronous transmit FIFO. chip tuple memory.
— 2 Kbyte asynchronous transmit FIFO. — Supports Mini PCI Specification v1.0, on-chip physical layer core or an
including Mini PCI® power requirements.
— 4 Kbyte isochronous receive FIFO. off-chip 1394a (FW802b) or 1394b
n I2C serial ROM interface.
— 2 Kbyte asynchronous receive FIFO. (FW843) external PHY. In this way,
n 3.3 V operation, 5 V tolerant inputs.
— Dedicated asynchronous and
isochronous descriptor-based n 144-pin TQFP or 161-ball VTFSBGA package. a high-performance and cost-
DMA engines. n NAND tree test mode. effective solution for connection
— Eight isochronous transmit/receive
contexts.
and servicing multiple IEEE 1394
— Supports parallel processing of (1394-1995, 1394a, and 1394b)
incoming physical read and write
requests.
peripheral devices can be realized.
n 1394b link:
— Cycle master and isochronous
resource manager capable.
— Support for 1394b acceleration
features.
— Support for 1394a-2000 acceleration
features.
— Eight-bit interface running at 100 MHz.

n 1394a-2000 PHY core:

— Compliant with IEEE ® 1394a-2000,
Standard for a High Performance Serial
Bus.
— Provides three fully compliant cable
ports, each supporting 400 Mbits/s,
200 Mbits/s, and 100 Mbits/s traffic.

Networking PCS Catalog    


FW843
IEEE® 1394b Bilingual Three-Port
Cable Transceiver/Arbiter
F e at u r e s
n Provides three backward-compatible
IEEE-1394 bilingual cable ports.
n Fully supports provisions of IEEE
1394b-2002.
n Fully supports provisions of IEEE 1394a-
2000 and IEEE 1394-1995 standards.
n Supports 1394a speeds of S100, S200,
and S400.
n Supports 1394b-2002 speeds of S400B
and S800B.
n On-chip (PLL) for high-speed clock
generation.
n Full 1394a-2000 support includes the
following:
— Connection debounce.
— Extended resume signaling for
compatibility with legacy DV
(digital video) devices.
— Arbitrated short reset.
— Port disable/suspend/resume.
— Multispeed concatenation.
— Fly-by concatenation.
— Arbitration acceleration.
n Single 3.3 V supply and on-chip 1.2 V
voltage regulator.
Low-power sleep mode.
n
n Powerdown modes to conserve energy
for battery-operated applications.
n Fully compliant with open host controller
interface (OHCI) requirements.
n Cable power sense function to detect
external cable power.
n Register bits give software control of
contender bit, power class bits, link active
control bit, and 1394a-2000 features.
n External pin control of power-class bits.
n Data interface to link-layer mode is
pin-selectable from 1394a-2000 mode or
1394b-2002 mode.
n Interoperable with other 1394 physical
layers using 1.8 V, 3.3 V, and 5.0 V supplies.
IEEE 1 3 9 4 B P RODU C T S
n Low-jitter on-chip crystal oscillator provides
transmit and receive data at 98.304 Mbits/s,
196.608 Mbits/s, 393.216 Mbits/s, 983.04
Mbits/s, and a link-layer controller clock at
49.152 MHz or 98.304 MHz.
n Fail-safe circuitry senses sudden loss of
power to the device. The ports are disabled
to ensure that the FW843 does not load the
TPBIAS with any connected device and
blocks any leakage from the port back to
the power plane.
n 1394a-2000 compliant common-mode
noise filter on the incoming bias detect
circuit filters out crosstalk noise.
n Scan test modes.
n 84-pin MLCC package.
The FW843 provides the digital and The FW843 supports the following 1394
speeds:
analog functions needed to implement
a three-port node in a cable-based IEEE
n S100 (98.304 Mbits/s)
1394 network. All three ports are compli-
ant with IEEE-1394b-2002 and backward- S200 (196.608 Mbits/s)
n
compatible with IEEE 1394a-2000 and
IEEE 1394-1995. The three ports are n S400 (393.216 Mbits/s)
capable of monitoring the line conditions
n S400B (491.52 Mbits/s)
for determining the connection status,
initialization and arbitration, and for the n S800B (983.04 Mbits/s)
packet reception and transmission.
Description
The FW843 provides the digital and
analog functions needed to implement
a three-port node in a cable-based IEEE
1394 network. Each of the three ports
can be configured to work in data-strobe
mode only (1394a-2000) by pulling the
corresponding DSMO input pin to the
3.3 V supply.
Networking PCS Catalog    
 IEEE 1 3 9 4 A P RODU C T S

FW533E
PCI Express® 1394a PHY/Link
Open Host Controller Interface

F e at u r e s Brief Description
n Single chip, integrated Link and PHY for PCI The LSI FW533E is a second genera- LSI provides support for the FW533
Express 1394a
tion 1394a OHCI controller designed with:
Supports three 1394a 400Mb/s ports
specifically for high performance,
n

n Evaluation adapter board

High performance, pipelined data transfer
PCI Express applications. Based on
n

n Sustained performance of 37 MByte/s read LSI’s proven TrueFire® technology, the n Ready-to-manufacture adapter card
and 34 MByte/s write
F533E has enhanced performance reference design
Dedicated asynchronous and isochronous
and power management features to
n

descriptor-based DMA engines n Manufacturing test utilities

deliver improved data transfer rates
n Large DMA FIFOs
with lower power consumption. n Configuration EEPROM image
n Enhanced power management
n 480 mW typical power consumption
The FW533E is ideally suited for adapt-
n Full ASPM and CLKREQ power management
er card applications. The FW533E is
support pin compatible with the LSI FW643E
n Single 24.576 MHz. crystal for lower BOM device, so that a single design and
costs layout can be populated with either
n Single 3.3V supply device to support 1394a or 1394b
n Configuration via an external EEPROM applications.
– no need for BIOS changes or
The FW533E also supports high-end
configuration utility
PC desktops and notebooks, PC
n 11x11 mm BGA package with 0.8 mm ball
pitch for lower-cost board layouts
gaming systems, external disk drive
n Also available in a small form factor Halogen
backups, industrial vision systems,
Free BGA package – 7x7mm footprint and other applications where high
n Support for Windows and MacOS operating performance, reliable data transfer
systems is required.
n Supports 8 isochronous contexts for greater
number of concurrent video streams

Networking PCS Catalog    

 IEEE 1 3 9 4 A P RODU C T S

FW323
1394a PCI PHY/Link Open Host Controller Interface

F e at u r e s

n 1394a-2000 OHCI link and PHY core function in a n 1394a-2000 PHY core:
single device: — Compliant with IEEE ® 1394a-2000, Standard for a
High Performance Serial Bus (Supplement).
— Single-chip link and PHY enable smaller,
simpler, more efficient motherboard and — Provides three fully compliant cable ports, each
add-in card designs. supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic.
— Enables lower system costs.
— Does not require external filter capacitor for PLL.
— Compatibility with current Microsoft Windows®
drivers and common applications. — Supports link-on as a part of the internal PHY
corelink interface.
— Supports low-power system designs (CMOS
implementation, power management features). — Supports arbitrated short bus reset to improve
utilization of the bus.
— Provides LPS, LKON, and CNA outputs to
support legacy power management — Supports multispeed packet concatenation.
implementations.
— Supports PHY pinging and remote PHY access
n OHCI:
packets.
— Complies with the 1394 OHCI 1.1 Specification.
— Reports cable power fail interrupt when voltage
— OHCI 1.0 backwards compatible—configurable at CPS pin falls below 7.5 V.
via EEPROM to operate in either OHCI 1.0 or
n PCI:
OHCI 1.1 mode.
— Revision 2.3 compliant.
— Listed on Windows hardware compatibility list
— 33 MHz/32-bit operation.
http://testedproducts.windowsmarketplace.com/.
— Programmable burst size thresholds for PCI data
— Compatible with Microsoft Windows and
transfer.
MacOS® operating systems.
— Supports optimized memory read line, memory
— 4 Kbyte isochronous transmit FIFO.
read multiple, and memory write invalidate burst
— 2 Kbyte asynchronous transmit FIFO. commands.
— 4 Kbyte isochronous receive FIFO. — Supports CLKRUN# protocol per PCI Mobile
— 2 Kbyte asynchronous receive FIFO. Design Guide.

— Dedicated asynchronous and isochronous — Supports Mini PCI® Specification v1.0, including
descriptor-based DMA engines. Mini PCI power requirements.

— Eight isochronous transmit/receive contexts.
— Prefetches isochronous transmit data.
— Supports posted write transactions.
— Supports parallel processing of incoming — I2C serial ROM interface.
physical read and write requests.
— May be used without an EEPROM when the
system BIOS is programmed with the EEPROM
contents.
— CardBus support per PC Card Standard Release
8.0, including 128 bytes of on-chip tuple memory.
— Supports PCI Bus Power Management Interface
Specification v.1.1, including D3cold wake-ups.
n CMOS process.
n 3.3 V operation, 5 V tolerant inputs.
n 128-pin TQFP or 129-ball VTFSBGA package.
n NAND tree test mode.

Networking PCS Catalog    

 IEEE 1 3 9 4 A P RODU C T S

FW322
1394a PCI PHY/Link Open Host Controller Interface

F e at u r e s

n 129-ball VTFSBGA — Supports link-on as a part of the internal PHY

core-link interface.
n 100-ball FSBGA
— Supports arbitrated short bus reset to improve
n 100-pin TQFP lead-free package.
utilization of the bus.
n 1394a-2000 OHCI link and PHY core function in a
— Supports multispeed packet concatenation.
single device:
— Reports cable power fail interrupt when voltage
— Single-chip link and PHY enable smaller,
at CPS pin falls below 7.5 V.
simpler, more efficient motherboard and add-in
n PCI:
card designs.
— Revision 2.3 compliant.
— Compatibility with current Microsoft Windows®
drivers and common applications. — 33 MHz/32-bit operation.

— Interoperability with existing, as well as older, — Programmable burst size thresholds for PCI data
1394 consumer electronics and peripherals transfer.
products.
— Supports optimized memory read line, memory
n OHCI: read multiple, and memory write invalidate burst
commands.
— Complies with the 1394 OHCI 1.1 Specification.
— Supports PCI Bus Power Management Interface
— OHCI 1.0 backwards compatible: configurable
Specification v.1.1.
via PCI bus commands to operate in either OHCI
1.0 or OHCI 1.1 mode. — Supports CLKRUN# protocol per PCI Mobile
Design Guide.
— Listed on Windows hardware compatibility list
— Supports Mini PCI Specification v1.0, including
http://testedproducts.windowsmarketplace.com.
Mini PCI ® power requirements.
— Compatible with Microsoft Windows and
— CardBus support per PC card standard release 8.0,
MacOS® operating systems.
including 128 bytes of on-chip tuple memory.
— 4 Kbyte isochronous transmit FIFO.
Other Features
— 2 Kbyte asynchronous transmit FIFO.
n CMOS process.
— 4 Kbyte isochronous receive FIFO.
n 3.3 V operation, 5 V tolerant inputs.
— 2 Kbyte asynchronous receive FIFO.
n I2C serial ROM interface.
— Dedicated asynchronous and isochronous
Note: The T100 device does not support D3cold
descriptor-based DMA engines.
wakeup, CLKRUN protocol, Mini PCI applications, or
— Eight isochronous transmit/receive contexts. Card-Bus applications.
— Prefetches isochronous transmit data.

— Supports posted write transactions.

ASYNCHRONOUS
— Supports parallel processing of incoming
DATA
physical read and write requests. TRANSFER
— May be used without an EEPROM when the CABLE PORT 1
PCI PCI LINK PHY
system BIOS is programmed with the EEPROM BUS CORE OHCI CORE CORE
contents. ISOCHRONOUS CABLE PORT 0
DATA
n 1394a-2000 PHY core:
TRANSFER
— Compliant with IEEE ® 1394a-2000, Standard for
a High Performance Serial Bus.

— Two fully compliant cable ports, each ROM

I/F
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic.

— Does not require external filter capacitor

for PLL.

Networking PCS Catalog    

 IEEE 1 3 9 4 A P RODU C T S

FW802
Low-Power PHY 1394a-2000 Two-Port Transceiver/Arbiter Devices

F e at u r e s

n Available in the following package options: n Supports 1394a-2000 register set.

— 64-pin TQFP (lead-free) n Supports LPS/link-on as a part of PHY-link interface.

— 48-pin TQFP (lead-free)
— 48-ball VTFSBGA (lead-free)
n Compliant with IEEE® Standard 1394a-2000,
IEEE Standard for a High Performance Serial Bus
Amendment 1.
n Low-power consumption during powerdown or
microlow-power sleep mode.
n Support extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
n While unpowered and connected to the bus, will
not drive TPBIAS on a connected port even if
receiving incoming bias voltage on that port.
n Do not require external filter capacitors for PLL.
n Do not require a separate 5 V supply for 5 V link
controller interoperability.
n Interoperable across 1394 cable with 1394 physical
layers (PHY) using 5 V supplies.
n Interoperable with 1394 link-layer controllers
using 5 V supplies.
n 1394a-2000 compliant common mode noise filter
on incoming TPBIAS.
n Powerdown features to conserve energy in battery
powered applications include the following:
n Supports provisions of IEEE 1394-1995 Standard for
a High Performance Serial Bus.
n Fully interoperable with FireWire® and i.LINK®
implementations of IEEE 1394-1995.
n Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
n Separate cable bias and driver termination voltage
supply for each port.
n Meets Intel® Mobile Power Guideline 2000.
Other Features
n 48- and 64-pin TQFP, 48-ball VTFSBGA packages.
n Single 3.3 V supply operation.
n Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
n 25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at 50 MHz.
n Node power-class information signaling for system
power management.
n Multiple separate package signals provided for
analog and digital supplies and grounds.

— Device powerdown pin/ball.

— Link interface disable using LPS.

— Inactive ports power down.

— Automatic micro-low-power sleep mode during

suspend.
n Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
n Provides two compliant cable ports at 100 Mbits/s,
200 Mbits/s, and 400 Mbits/s.
n Supports OHCI requirements.
n Supports arbitrated short bus reset to improve
utilization of the bus.
n Supports ack-accelerated arbitration and fly-by
concatenation.
n Supports connection debounce.
n Supports multispeed packet concatenation.
n Supports PHY pinging and remote PHY access
packets.
n Supports full suspend/resume.
n Supports PHY-link interface initialization and reset

Networking PCS Catalog    10

 IEEE 1 3 9 4 C ARD S

FireStorm™ FW643/FW533
Evaluation Platform

F e at u r e s :

FW643 Features: Brief Description

PCI Express to 1394b
The FireStorm is a low-cost, flexible, FireStorm evaluation boards
n

n Three 1394b (S800) PHY ports

n Only single-chip PCIe to 1394b
4-layer PCB designed to allow users feature plug and play for
available to quickly evaluate the performance Microsoft® Windows® (2000/XP/
Backward compatible to 1394a
of the LSI’s TrueFIRE™ SOCs, the Vista) operating systems. The OS
n

FW533 Features:
n PCI Expressto 1394a
n Three 1394a (S400) PHY ports
Both Devices Feature:
n Single-lane PCI Expressversion 1.1
OHCI version 1.1+
n
n Improved performance with large FIFOs
n Low power through support for ASPM
n Very small 7 mm x 7 mm VTFSBGA
package
FW533/FW643, or aid in develop- will detect the FireStorm presence
ment of custom solutions. and load the appropriate drivers
automatically. Drivers for Linux®
The FireStormFW533 platform
and MacOS® are also available.
combines an OHCI (open host
controller interface) with LSI’s IEEE®
1394a-2000 technology and a high-
performance, standards-compliant
PCI Express® 1.0a host system
interface.

Each FireStormEvaluation Board Features: The FireStorm FW643 platform

FW533 or FW643 device, 7 mm x 7 mm
n

form-factor 127-pin VTFSBGA package

n Three 1394 bilingual interface ports
n Atmel®2-wire serial EEPROM, 100 kHz
n Single external 24.576 MHz crystal
Disk drive power header
n
combines an OHCI with LSI’s
1394b-2002 technology and a PCI
Express 1.1 host system interface
to provide S800 1394b-2002
compliant throughput.

n Complete bill of materials

n Board schematics in OrCAD®Capture
v9.0Ordering

Networking PCS Catalog    11


FireSide™ FW643 ExpressCard™
Reference Platform
F e at u r e s
FW643 Features:
n PCI Express to 1394b
n Three 1394b (S800) PHY ports
n Only single-chip PCIe to 1394b available
n Backward compatible to 1394a
Single-lane PCI Express version 1.1
n
n OHCI version 1.1+
n Improved performance with large FIFOs
n Low power through support for ASPM
n Very small 7 mm x 7 mm VTFSBGA
package
Each FireSide Expansion Card Features:
n FW643 device, 7 mm x 7 mm form-factor
127-pin VTFSBGA package
n Two 1394 bilingual interface ports
Atmel®2-wire serial EEPROM, 100 kHz
n
n Single external 24.576 MHz crystal
n Board schematics in OrCAD®
Capture v9.0
Turnkey design ready for volume
n
production
n Complete bill of materials
Brief Description
FireSide is an expansion card
that conveniently inserts into an
ExpressCard slot on PC laptops/
notebooks and thereby enables
a quick and seamless transition
to IEEE® 1394b capabilities. The
platform is produced in a compact,
ExpressCard/34 form-factor
configuration, which offer two
800 Mbits/s1394 ports for high-
speed connectivity.
FireSide is developed as a refer-
ence design for a fully packaged,
consumer-quality product. It is
designed for rapid technology
transfer to original design manu-
facturers (ODMs) worldwide. This
targeted approach enables reduced
engineering costs and faster time
to market for products based upon
LSI’s TrueFIRE™ technology.
IEEE 1 3 9 4 C ARD S
At the heart of the FireSide
platform is the LSI FW643 chip
that combines an OHCI with LSI’s
1394b-2002 technology and a
PCI Express® 1.1 host system
interface to provide S800 1394b-
2002 compliant throughput.
The FireSide expansion card
features plug and play for
Microsoft® Windows® (2000/XP/
Vista) operating systems. The OS
will detect the FireSide presence
and load the appropriate drivers
automatically. Drivers for Linux®
and MacOS® are also available.
Networking PCS Catalog    12
 IEEE 1 3 9 4 C ARD S

1394 PC OEM Card

F EATURE S

n LSI Inc. FWA323 1394 Host Controller PCA.

n 1394a 400 Mbits/s, 3 ports, OHCI 1.0, Power
Management 1.1.
n PCI 2.1s 32 bit, 33 MHz, 3.3 V powered.
n 2 external 1394 6-pin rear connectors. Options for
internal 1394 connection.
n Optional 1394 bus power provides up to 15 W.
n Single chip reliability with LSIFW323 integrated
PHY/Link.
n Short card form factor.
n MS Windows® compatible including DV and SBP-2
drivers, supports all common camcorders, disk
drives, printers and scanners with 1394 interfaces.
n Compatible with leading video editing
applications, including MGI VideoWave II, III,and
IV® and Ulead VideoStudio5®.
n WHQL certified.
n FCC, UL® approved.

Networking PCS Catalog    13

 Modem-PC

Product Brief

SV92EX
PCI-Express Soft Modem

F e at u r e s

n Two-chip, single-lane PCI-Express soft modem

solution with an integrated interface that supports
the PCI-Express revision 1.1 standard:

— SV92EX host interface in a 32-pin MLCC.

— CSP1040 DAA in a 20-pin TSSOP.

n Data mode capabilities:

— ITU-T ™ V.92*: 56000 bits/s—28000 bits/s.

— ITU-T V.90*: 56000 bits/s—28000 bits/s.

— ITU-T V.34: 33600 bits/s—2400 bits/s.

— V.32bis and fallbacks.

— V.44, V.42, V.42 bis, and MNP ™

- Class 5 data compression.

— High compression throughput due to parallel

access directly to the host PC.
n FAX mode capabilities:

— ITU-T T.31 class 1 FAX.

— ITU-T V.17: 14400 bits/s, 12000 bits/s,
9600 bits/s, 7200 bits/s (TCM).
— ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM).
— ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK).
The SV92EX chip set using LSI’s third-generation silicon DAA is a soft
modem solution for PCI-Express applications. The chip set works with LSI’s
standard soft modem drivers and supports V.92 and lower rates.

— ITU-T V.21 Channel 2: 300 bits/s (FSK).
n CSP1040:
— System-powered.
— Proprietary isolation barrier.
— Programmable event detect for caller-ID ing compliance with worldwide regulatory
reception and power ring detection.
— Programmable pulse shaping and spark
quench.
— Programmable dc-impedance termination for
country-specific VI templates.
— Programmable ac-impedance termination for full operation on marginal phone lines.
return-loss matching.
— Programmable ringer-impedance emulation.
n Hardware support for pulse dialing for accurate
make/break timing.
n Wake-on-ring and caller ID support.
n Common driver across multiple platforms.
The CSP1040 device is LSI’s third-generation
silicon DAA, which reduces the number of
components and board area required to imple-
ment a full-featured modem, while achiev-
requirements. A low-profile digital transformer
provides the communications link between the
CSP1040 and SV92EX devices. This digital link
also provides power to the CSP1040, allowing
The CSP1040 includes hardware support for
detecting line-in-use status, overcurrent, polar-
ity reversals, caller ID, and ringing, without
the need for additional external circuitry. This
allows for full-featured modem designs without
increased bill-of-materials or board space.
Op e r a t i n g S y s t e m S u pp o r t
n Windows ® 98, Windows 2000, Windows ME ®,
and Windows XP 32/64-bit Editions,
Windows VISTA 32/64-bit Editions
n Microsoft Designed for Windows logo device
requirement compliant

* Actual speeds over U.S. telephone lines vary and are less than 56K due to current FCC regulations and line conditions.

Networking PCS Catalog    14

 Modem-PC

SV92A3
HDA/AC97 Soft Modem

F EATURE S
The SV92A3 chip set using LSI’s The CSP1040 device is LSI’s third-generation
Two-chip HDA/AC97 soft modem solution: silicon DAA and reduces the number of
n

— SV92A3 host interface in a 16-pin TSSOP

(3.3v only), or
— SV92A35 host interface in a 16-pin TSSOP
(1.5v or 3.3v), and
— CSP1040 DAA in a 20-pin TSSOP.
n Data mode capabilities:
— ITU-T ™ V.92: 56000 bits/s—28000 bits/s.
— ITU-T V.90: 56000 bits/s—28000 bits/s.
— ITU-T V.34: 33600 bits/s—2400 bits/s.
— V.32bis and fallbacks.
— V.44, V.42, V.42 bis, and MNP ™ Class 5
data compression.
— High compression throughput due to parallel
access directly to the host PC.
FAX mode capabilities:
n
CSP1040 silicon DAA is a soft-
modem solution for AC’97 and
HD Audio applications. The chip
set works with LSI’s standard soft
modem drivers and supports V.92
and lower rates. The SV92A3 chip
set enables modem designs with
lowest parts count and minimum
board area, creating the best
components and board area required to
implement a full-featured modem, while
achieving compliance with worldwide
regulatory requirements. A low-profile digital
transformer provides the communications link
between the CSP1040 and SV92A3 devices. This
digital link also provides power to the CSP1040,
allowing full operation on even marginal
phone lines that caused problems with earlier
generation silicon DAAs. The CSP1040 includes
hardware support for detecting line-in-use

— ITU-T T.31 class 1 FAX.

— ITU-T V.17: 14400 bits/s, 12000 bits/s,
9600 bits/s, 7200 bits/s (TCM).
— ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM).
— ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK).
— ITU-T V.21 Channel 2: 300 bits/s (FSK).
n AC’97 bus interface:
— AC’97 specification 2.3 compliant.
— Configurable for secondary device 1 or 2.
n HD Audio bus interface:
— HD Audio specification 1.0 compliant.
— 1.5v or 3.3v signalling
n Hardware support for pulse dialing.
n Wake-on-ring and caller ID support.
n Single 3.3 V power supply.
n CSP1040:
— System-powered.
— Proprietary transformer-based isolation barrier.
— Programmable event detect for caller-ID
reception and power ring detection.
— Programmable pulse shaping and spark
quench.
— Programmable dc-impedance termination for
country-specific VI templates.
— Programmable ac-impedance termination for
return-loss matching.
— Programmable ringer-impedance emulation.
possible solution for MDC 1.0/1.5
status, overcurrent, polarity reversals, caller ID,
and modem-on-motherboard
and ringing, without the need for additional
applications. external circuitry. This allows for full-featured
modem designs without increased bill-of-
The SV92A3 device provides a dual-mode materials or board.
AC’97 and HD Audio interface with automatic
mode detection. The SV92A3 is available
in a 16-pin TSSOP package. A new version
(SV92A35) is also available that supports 1.5v
as well as 3.3v signalling. The SV92A3 includes
logic to provide robust ring detection and
qualification eliminating unintended wake-
on-ring events due to activity on the phone
line other than ringing. The SV92A3 also
handles pulse dial timing control in hardware
to eliminate system timing dependencies
common with earlier soft modem products.

Networking PCS Catalog    15

 Modem-PC

SV92U2
USB Soft Modem

F EATURE S
The SV92U2 chip set using LSI’s
Two-chip, USB 2.0-compliant soft modem solution:
n

— SV92U2 host interface in a 48-pin TQFP.

third-generation silicon DAA is
— CSP1040 DAA in a 20-pin TSSOP. a soft modem solution for both
USB 2.0 compliant device controller:
n

— Supports high-speed (480 Mbits/s

and full-speed (12 Mbits/s) data rates.
— Integrated high-/full-speed USB transceivers.
— Bus-powered USB
— 2 Kbytes USB FIFO memory.
n Data mode capabilities:
— ITU-T ™ V.92*: 56000 bits/s—28000 bits/s.
— ITU-T V.90*: 56000 bits/s—28000 bits/s.
— ITU-T V.34: 33600 bits/s—2400 bits/s.
— V.32bis and fallbacks— V.44, V.42, V.42 bis,
and MNP ™ Class 5 data compression.
— High compression throughput due to parallel
access directly to the host PC.
n FAX mode capabilities:
— ITU-T T.31 class 1 FAX.
— ITU-T V.17: 14400 bits/s, 12000 bits/s,
9600 bits/s, 7200 bits/s (TCM).
— ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM).
— ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK).
— ITU-T V.21 channel 2: 300 bits/s (FSK).
n CSP1040:
— System-powered.
— Digital transformer-based isolation barrier.
— Programmable event detect for caller-ID
reception and power ring detection.
— Programmable pulse shaping and spark quench
— Programmable dc-impedance termination for
country-specific VI templates.
— Programmable ac-impedance termination for
return-loss matching.
— Programmable ringer-impedance emulation.
n Serial EPROM support for optional vendor ID
information. May be eliminated to recover cost.
high-speed (480 MHz) and full-
speed (12 MHz) USB2.0 applica-
tions. The chip set works with LSI’s
standard soft modem drivers and
supports V.92 and lower rates.
The SV92U2 is available in a 48-pin TQFP
package. The SV92U2 includes logic to provide
robust ring detection and qualification elimi-
nating unintended wake-on-ring events due to
activity on the phone line other than ringing.
The SV92U2 also handles pulse dial control in
hardware to eliminate system timing depen-
dencies common with earlier soft modem
products.
The CSP1040 device is LSI’s third-generation
silicon DAA and reduces the number of compo-
nents and board area required to implement a
full-featured modem, while achieving compli-
ance with worldwide regulatory requirements.
A low-profile digital transformer provides the
communications link between the CSP1040
and SV92U2 devices. This digital link also
provides power to the CSP1040, allowing full
operation on even marginal phone lines. The
CSP1040 includes hardware support for detect-
ing line-in-use status, overcurrent, polarity re-
versals, caller ID, and ringing, without the need
for additional external circuitry. This allows for
full-featured modem designs without increased
bill-of-material or board space.

Networking PCS Catalog    16

 Modem-PC

SV92PP
PCI Soft Modem

F EATURE S
The SV92PP chip set using LSI’s
Two-chip PCI soft modem solution with an
n

integrated 5 V tolerant interface that supports

third-generation silicon DAA is
the PCI revision 2.3 standard: a soft modem solution for PCI
— SV92PP host interface in a 68-pin MLCC.
— CSP1040 DAA in a 20-pin TSSOP. applications. The chip set works
n Data mode capabilities: with LSI’s standard soft modem
— ITU-T ™ V.92*: 56000 bits/s—28000 bits/s.
— ITU-T V.90*: 56000 bits/s—28000 bits/s. drivers and supports V.92 and
— ITU-T V.34: 33600 bits/s—2400 bits/s.
— V.32bis and fallbacks.
lower rates.
— V.44, V.42, V.42 bis, and MNP ™
Class 5 data compression.
The CSP1040 device is LSI’s third-generation
— High compression throughput due to
parallel access directly to the host PC. silicon DAA, which reduces the number of
n FAX mode capabilities: components and board area required to
— ITU-T T.31 class 1 FAX. implement a full-featured modem, while
— ITU-T V.17: 14400 bits/s, 12000 bits/s,
9600 bits/s, 7200 bits/s (TCM). achieving compliance with worldwide
— ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM). regulatory requirements. A low-profile digital
— ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK).
transformer provides the communications link
— ITU-T V.21 Channel 2: 300 bits/s (FSK).
between the CSP1040 and SV92PP devices. This
n CSP1040:
— System-powered. digital link also provides power to the CSP1040,
— Proprietary isolation barrier. allowing full operation on marginal phone lines.
— Programmable event detect for caller-ID
reception and power ring detection.
— Programmable pulse shaping and The CSP1040 includes hardware support for
spark quench.
detecting line-in-use status, overcurrent,
— Programmable dc-impedance termination
for country-specific VI templates. polarity reversals, caller ID, and ringing, without
— Programmable ac-impedance termination the need for additional external circuitry. This
for return-loss matching.
— Programmable ringer-impedance emulation.
allows for full-featured modem designs without
n Hardware support for pulse dialing for accurate
increased bill-of-materials or board space.
make/break timing.
n Wake-on-ring and caller ID support.
n Common driver across multiple platforms.

Networking PCS Catalog    17


CV22A
V.22bis Modem Chipset for Low Speed Data Applications
F EATURE S
Two-chip controller-based modem solution:
n
– CV22A modem device in a 24-pin
ETSSOP or 48-pin TQFP.
– CSP1040 data access arrangement
(DAA) in a 20-pin ETSSOP.
n Data-mode capabilities:
– ITU-T V.29 fast connect: 9600 bits/s, alarm systems, remote monitoring,
7200 bits/s for point of sale (POS).
– ITU-T V.22 fast connect: 2400 bits/s.
(for POS)
– ITU-T V.22bis: 2400 bits/s.
– ITU-T V.23: 1200/75 bits/s.
– ITU-T V.21: 350 bits/s.
– Bell 212A: 1200 bits/s.
– Bell 103: 300 bits/s.
– MNP™ 2-4 error correction.
– SDLC/HDLC for POS applications.
n RS232 asynchronous serial data
terminal equipment (DTE).
interface with rates to 230.4K bits/s.
n CSP1040 features:
– System powered.
– Type I caller-ID support.
– Remote handset detection.
– Line-in-use detection.
– Digital transformer-based isolation barrier.
The CV22A Modem Chipset is
designed to serve embedded
applications that require lower-
speed dial-up data connections.
These applications include: digital
tv, set-top boxes, point of sale (POS),
and other telemetry applications.
The CV22A chip set includes the LSI CV22A
modem device and LSI CSP1040 silicon data
access arrangement (DAA), thereby providing
a complete V.22bis controller-based modem.
The CV22A device incorporates an ARM7
microcontroller for AT command processing,
modem protocols, and data modulation tasks.
It provides an RS232 serial host (system side)
interface as well as an interface to the CSP1040
(DAA side).
LSI CV22A-
CV22A-T48 E24
LSI
CV22A-T48
Actual Size
M ODE M - E M B EDDED DATA
The CSP1040 device is LSI’s third-generation
silicon DAA. It reduces the number of
components and board area required to
implement a full-featured modem while
achieving compliance with worldwide
regulatory requirements. A low-profile digital
transformer provides the communications link
between the CSP1040 and CV22A devices. This
digital link also provides power to the CSP1040,
allowing full operation on even marginal phone
lines. The CSP1040 includes hardware support
for detecting line-in-use status, overcurrent,
polarity reversals, caller ID, and ringing without
additional external circuitry. This allows for
full-featured modem designs without increased
bill-of-material (BOM) or board space.
CV22A-
E24
Networking PCS Catalog    18
 M ODE M - E M B EDDED DATA

CV92, CV90, CV34 and CV22

Controller-Based Modem Devices

F EATURE S

n Two-chip modem solution:

The CVxx family of devices is The CVxx devices support RS232 and 8-bit mi-
— CVxx Modem Device in 48-pin TQFP or 100-pin croprocessor interfaces. Additionally, the CVxx
FSBGA (CV92-F100 only) designed to serve embedded
devices can be configured for operation on a
— CSP1040 DAA in 20-pin ETSSOP applications that require high- 4-wire SPI bus.
n Data mode capabilities: speed dial-up data connections.
— V.92, V.90, V.34, V.32bis, V.32
There are several versions available Figure 1 shows a reference design using the 48-
— V.22bis, V.22. V.21
pin CVxx and the CSP1040. This is a 2-layer PCB
— Bell 212A, Bell 103
based on modulations and other
with components on top-side only. The layout
— V.17 and lower fax rates features. For designs that must
can be integrated into a larger PCB or built as a
— V.44, V.42bis, MNP 5 Data Compression support field-upgradeability or separate module with connectors.
— V.42, MNP 2–4 Error Correction
customized features, a version
CVxx Modem Device features: Typical applications include point-of-sale ter-
of the CV92 device is available
n

— ARM7TDMS Microcontroller minals, TV set-top-box, gaming consoles, video

— DSP1600S Digital Signal Processor
in a 100 FSBGA that can support
phones, alarm systems, remote monitoring and
— DAA interface and filters external flash ROM. All other other telemetry applications.
— Host interface configurable for 8-bit parallel, versions run from on-chip ROM.
asynchronous serial or SPI mode

— On-chip PWM speaker driver

The table on page 2 shows the
— SIO interface for audio codec used in voice and features supported for the various
handset applications
versions.
— 24.576 MHz crystal or external 27.0 MHz clock
CSP1040 DAA features:

— Derives power from system for reliable Figure 1. “Pisa” Embedded Modem Module
operation on all phone lines (shown approximately actual size when printed on 8.5” x 11” paper.)
— Digital transformer isolation barrier

— Programmable event detect for caller-ID

reception and power ring detection

— Programmable pulse shaping and spark quench

— Programmable dc-impedance termination for

country-specific VI templates

— Programmable ac-impedance termination for

return loss matching

— Programmable ringer-impedance emulation

n Hardware support for pulse dialing for accurate
make/break timing.
n Hardware support for ringing level and frequency
qualification for accurate ring detection.
n Line-in-use and remote handset detection
n Single 3.3V supply required for chip set.
n World-wide caller ID support

Networking PCS Catalog    19

 M ODE M S - e mb e d d e d f a x

CFAX34 and CFAX17

FAX Modem Devices

F EATURE S

n Two-chip modem solution:

The CFAX family of devices is
— CFAXxx modem in 48-pin TQFP or 100 FSBGA
with external memory interface. designed to serve embedded
— CSP1040 DAA in 20-pin ETSSOP.n FAX mode applications where a complete
capabilities:
FAX subsystem including protocol
— ITU-T T.31 (FAX class 1) interface.

— ITU-T T.32 (FAX class 2.1) interface.

processing is desired. The CFAX
— V.34: 33600—2400 bits/s (CFAX34 only). family includes two devices:
— V.17: 14400—2400 bits/s.

— V.29, V.27, V.21. n CFAXV34. Supports V.34, V.17, V.29, and lower
— ECM with on-chip 64 Kbytes buffer. FAX rates.
n CFAX modem controller includes:

— ARM7 microcontroller with on-chip RAM n CFAXV17. Supports V.17, V.29, and lower on a 4-wire SPI bus. Figure 1 shows a reference
and ROM. design using the 48-pin CFAX and the CSP1040.
FAX rates.
— DP3S with on-chip RAM and ROM. This is a 2-layer PCB with components on top-
— DAA interface and filters. The CFAX devices support RS232 and 8-bit side only. The layout can be integrated into a
— Host interface configurable for 8-bit parallel, micro-processor interfaces. Additionally, the larger PCB or built as a separate module with
serial, or SPI mode.
CFAX devices can be configured for operation connectors.
— On-chip PWM speaker driver.

— SIO interface for audio codec used in voice and

handset applications.
Figure 1 shows a typical application using a CFAX34 modem controller along with a CSP1040 silicon

— Internal PLL with external low-cost crystal.

DAA to add FAX capability to a system.
n CSP1040 DAA features:

— Derives power from system for reliable

operation on all phone lines.

— Programmable event detect for caller-ID

reception and power ring detection.

— Programmable pulse shaping and spark

quench.

— Programmable dc-impedance termination for

country-specific VI templates.

— Programmable ac-impedance termination for

return-loss matching.

— Programmable ringer-impedance emulation.

n Hardware support for pulse dialing for accurate
make/break timing.
n Hardware support for ringing level and frequency
qualification for accurate ring detection.
n Line-in-use and remote handset detection.n Single T y p i c a l App l i c a t i o n s
3.3 V supply required for chip set.
n FAX machines
n Worldwide caller ID support.
n Multifunction printers (MFPs)
n Multiport FAX servers

Networking PCS Catalog    20

 M ODE M S - e mb e d d e d f a x

DP3Vxx
Family of Data Pump Devices

F EATURE S
n Two-chip modem solution:
— DP3xx data pump in 48-pin TQFP
— CSP1040 DAA in 20-pin ETSSOP
n FAX mode capabilities:
— V.34: 33600—2400 bits/s (DP3V34X only)
— V.17: 14400—2400 bits/s
— V.29: 9600, 7200 bits/s
— V.27ter: 4800, 2400 bits/s
— V.21 ch 2: 300 bits/s
n DP3 data pump includes:
— Digital signal processor
— DAA interface and filters
— Host interface configurable for 8-bit parallel
or SPI mode
— On-chip PWM speaker-driver
— SIO interface for audio codec used in voice
and handset applications
n CSP1040 DAA features:
— Derives power from system for reliable
operation on all phone lines
— Programmable event detect for caller-ID
reception and power ring detection
— Programmable pulse shaping and spark quench
The DP3 family of devices is
designed to serve embedded
applications where a separate
modem microcontroller is not
required—e.g., where a suitable
system controller is already
available to perform protocol
processing. The DP3 family
includes two devices:
n DP3V34X. Supports V.34/V.17/V.29 (and
lower) fax rates for fax-only applications.
n DP3V17X. Supports V.17/V.29 fax modes, as ity reversals, and caller ID, as well as for ringing
well as V.32 and lower data rates.
The DP3xx devices support an 8-bit micropro-
cessor interface similar to earlier DP2 devices.
Additionally, the DP3 devices can be config-
ured for operation on a four-wire SPI bus.
The DP3 devices are used in conjunction with
the CSP1040 DAA. The CSP1040 device is
LSI’s third-generation silicon DAA. It reduces
the number of components and board area
required to implement a full-featured modem,
while achieving compliance with worldwide
regulatory requirements. A low-profile digital
pulse transformer provides the communica-
tions link between the CSP1040 and DP3
devices. This digital link also provides power
to the CSP1040, allowing full operation on all
phone lines.
The CSP1040 includes hardware support for
detecting line-in-use status, overcurrent, polar-
without the need for additional external
circuitry. This allows for fullfeatured modem
designs without increased bill-of- material or
board space.

— Programmable dc-impedance termination for

country-specific VI templates

— Programmable ac-impedance termination for

return-loss matching

— Programmable ringer-impedance emulation

n Hardware support for pulse dialing for accurate
make/break timing.
n Hardware support for ringing level and frequency
qualification for accurate ring detection.
n Line-in-use and remote handset detection.
n Single 3.3 V supply required for chip set.
n Worldwide caller ID support.

Figure 1. DP3V with T38 Audio Codec

Networking PCS Catalog    21

 M ODE M S - e mb e d d e d f a x

SFAX34/SFAX17
Soft FAX Modem for Embedded Products

F e at u r e s
n SFAX34 and SFAX17 devices for V.34 and V.17
FAX solutions
SFAX is a family of chips that Soft FAX Modem Stack running on SoC

n 24-pin MLCC production package

are designed to support soft
– 48-pin TQFP for backward compatibility to embedded FAX applications for SPI

DP3/CFAX
MFP and FAX machine. The family
n DTE interface:
includes two devices: LSI
CSP1040
– Serial Peripheral Interface (SPI)
LSI
T38
n Single 3.3V supply with 5V tolerant I/O n SFAX34: Soft embedded V.34 FAX chipset
n Supports all CSP1040 features and allows a
n SFAX17: Soft embedded V.17 FAX chipset
single world-wide hardware design
LSI
CSP1040
n LSI Soft FAX modem supports: The SFAX devices support a SPI interface which
– V.34 and lower Fax rates provides the interface between the embedded
– T.32 Command Set (T.30 w/ECM) processor and the modem chip set. It provides
– World-wide caller ID interfaces to the CSP140 Codec, the T38 To
UNF
– Handset, speakerphone and TAM (with T38 voice codec for handset and speakerphone
audio codec)
applications and the call progress speaker
– Supports proprietary OS’s with RTOS- Figure 1. SFAX System Block Diagram
independent architecture circuit.

The chipset would be used in conjunction with

Soft Modem code running on the System’s
embedded processor to implement the
complete FAX function including modulation
speeds up to V.34 and the T.30 protocol stack.

LSI LSI
SFAX34
SFAX34-T48 -M24

LSI LSI
SFAX34
SFAX34-T48 -M24

Actual Size

Networking PCS Catalog    22

 V o i c e P RODU C T S

FX1000/FX1041
FXO for Voice over IP Applications

F e at u r e s The FX1000, when used with the FX1041 line-side codec, provides all of
FX1000 plus FX1041 implements
n

complete Foreign Exchange Office

the functionality required to implement an FXO for Voice over IP (VoIP)
(FXO) functionality applications. The FX1000 provides the interface to the VoIP SoC through
24-pin MLCC (4 x 4 mm) FX1000
its TDM interface (for data) and SPI bus (for control), and an interface to the
n

package
n SoC interface (compatible with other FX1041 Line-side codec through a high-voltage isolation barrier.
Foreign Exchange Subscriber (FXS)
and FXO devices):
– Serial Peripheral Interface (SPI) for
control
– Time-division multiplexed (TDM)
interface for data (up to 8.192 MHz)
n Single 3.3-V supply with 5-V-tolerant I/O
n No external crystal required
(uses TDM clock) LSI LSI
FXO1000-
FX1041-E11 M24
n System-powered solution
n Greater than 4KV Isolation
n Single programmable solution for
worldwide support
n Overcurrent Protection
n Line snooping
n Supports multiple interrupt events
n FXO functionality:
LSI LSI

– Highest voice quality with low noise

FXO1000-
FX1041-E11 M24

(16-bit linear codec w/ >80 dB

dynamic range) Actual Size
– Ring detect
– Support for Type I and Type II caller ID
– General-purpose I/O (GPIO) interface
to support ground start applications
– FXO call-disconnect detection on
loop start lines
– Hardware support for pulse dialing

Networking PCS Catalog    23

 ETHERNET P RODU C T S

ET1011C
TruePHY™ Gigabit Ethernet Transceiver

F EATURE S
The LSI ET1011C is a Gigabit architectures.Using oversampling has allowed
10Base-T, 100Base-TX, and 1000Base-T Gigabit for the implementation of a fractionally spaced
n

Ethernet transceiver:
Ethernet transceiver fabricated
equalizer, which provides better equalization
— 0.13 µm CMOS process on a single CMOS chip. Packaged and has greater immunity to timing jitter,
— 84-pin MLCC: • RGMII, GMII, MII, RTBI, and TBI
interfaces to MAC or switch in either a 128-pin TQFP, an 84- resulting in better signal-to-noise ratio (SNR),
— 68-pin MLCC: RGMII and RTBI interfaces to
MAC or switch
pin MLCC, or a 68-pin MLCC, and thus improved BER. In addition, advanced

the ET1011C is built on 0.13 timing algorithms are used to enable operation
n Low power consumption:
— Typical power less than 750 mW in 1000Base-T over a wider range of cabling plants.
mode
µm technology for low power
— Advanced power management consumption and application
— ACPI compliant wake-on-LAN support
n Oversampling architecture to improve signal
in server and desktop NIC cards.
integrity and SNR It features single power supply
Optimized, extended performance echo and NEXT
operation using on-chip regulator
n

filters
n All-digital baseline wander correction controllers. The 10/100/1000Base-
n Digital PGA control T device is fully compliant with
On-chip diagnostic support
n
IEEE ® 802.3, 802.3u and 802.3ab
n Automatic speed negotiation
standards.
n Automatic speed downshift
n Single supply 3.3 V or 2.5 V operation:
— On-chip regulator controllers The ET1011C uses an oversampling architec-
— 3.3 V or 2.5 V digital I/O — 3.3 V tolerant I/O ture to gather more signal energy from the
pins (MDC, MDIO, COMA, RESET_N, and JTAG
pins) communication channel than possible with
— 1.0 V or 1.1 V core power supplies traditional architectures. The additional signal
— 1.8 V or 2.5 V for transformer center tap
energy or analog complexity transfers into the
n JTAG
digital domain. The result is an analog front end
n ET1011C is a pin-compatible replacement for the
that delivers robust operation, reduced cost,
ET1011 device
and lower power consumption than traditional
n Commercial and industrial temperature versions
available.

For more information and sales office locations, please visit the LSI web sites at:  lsi.com  lsi.com/contacts

LSI and the LSI logo are trademarks or registered trademarks of LSI Corporation.

All other brand and product names may be trademarks of their respective companies. LSI Corporation reserves the right to make changes to any
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Copyright ©2009 by LSI Corporation. All rights reserved.
Networking PCS Catalog    24
May 2009PR