SKASC 2017

UP / DOWN COUNTER

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity UP_DOWN_COUNTER is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
UD : in STD_LOGIC;
Count : out STD_LOGIC_VECTOR (3 downto 0));
end UP_DOWN_COUNTER;

architecture Behavioral of UP_DOWN_COUNTER is

signal tmp:STD_LOGIC_VECTOR (3 downto 0);
begin
process(clk,rst)
begin
if(rst='1') then
tmp<="0000";
elsif(clk'event and clk='1') then
if(UD='1') then
tmp<=tmp+1;
else
tmp<=tmp-1;
end if;
end if;
end process;
Count<= tmp;
end Behavioral;

M.SELVAM/VLSI LAB/ UPDOWN COUNTER Page 1

 SKASC 2017

UP-DOWN COUNTER

module upc( input clk,reset,up_down,output reg [3:0]Count);

always@(posedge clk)

begin

if(!reset) //synchronous reset

Count<=4b0000;

else if(up_down)

Count<=Count+1; //up counting

else

Count<=Count-1; //down counting

end

endmodule

M.SELVAM/VLSI LAB/ UPDOWN COUNTER Page 2