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A. D. Downey and G. M.

Wierzba: A Class-G/FB Audio Amplifier 1537

A Class-G/FB Audio Amplifier


Adam D. Downey and Gregory M. Wierzba, Senior Member, IEEE

Abstract A Class-G amplifier is a power amplifier that the use of Sspice (Symbolic Spice [4], [5]) and numerical
can achieve better power efficiency than the Class-B SPICE provides the designer with tools for identifying the
amplifier. For these amplifiers, low distortion is achieved with causes of some instabilities. A final design for a stable Class-
large values of power supply voltage. A new Class-G/FB G/FB audio amplifier is presented here along with the
amplifier is proposed using an operational amplifier with a improvements over an analogous Class-B/FB amplifier.
Class-G power stage and feedback to lower the total
harmonic distortion of the amplifier rather than using large II. DESIGN OF CLASS-G/FB AMPLIFIER
power supply voltages. Methods for identifying and solving
RF
the stability problems associated with this Class-G/FB
amplifier are presented. The efficiency of this amplifier is V2
examined along with experimental results.1 V1
Q2
Index Terms audio amplifier, amplifier stability, beta
RIN Q1 D1
network analysis, amplifier efficiency. QA
VIN -
+
QA' Q1' D1'
I. INTRODUCTION RL

Power efficient circuits are becoming more important as Q2'


V1'
technology advances to using more portable devices such as
cell phones, mp3 players, and laptop computers. The Class-G V2'
Class-B Class-G
amplifier gives improved efficiency for audio power
amplifiers compared to the conventional Class-B amplifier. Fig. 1: Schematic for Class-G/FB amplifier.
This amplifier can be particularly effective with signals that
have a Gaussian probability distribution such as music and The Class-G/FB amplifier designed here is shown in Fig. 1.
mixed sound where the ratio between maximum and average It uses TIP31 and TIP32 bipolar junction transistors (BJT) for
power is large (10 to 20dB). The Class-G amplifier discussed the output stage. Schottky diodes at the lower power supplies
here uses a series or stacked typology that incorporates a are used instead of PN junction diodes which store more
Class-B amplifier with two (+/- V1 and +/- V2) power charge [6] and cause distortion as the amplifier switches from
supplies. For an audio signal with a Gaussian probability the smaller to the larger power supply [7]. PN junction diodes
density function that has a peak-to-average ratio of 15dB, the are used to keep transistors Q1 and Q1' in the active region. It
average efficiency of an ideal Class-B is only 22.3% while an is important to keep the transistors in either the cut-off region
ideal two-voltage Class-G with proper values of transition or the active region of operation for maximum efficiency.
voltage increases the average efficiency to 50.4% [1]. This is because the maximum current in the collector of Q2 is
Without any additional biasing, the basic Class-G amplifier IB2 when transistor Q1 is in the saturation region causing
circuit [2], shown in Fig. 1, has more cross-over distortion more current to go through the base of Q1. More power will
than the Class-B amplifier. This is because of the additional be lost because of the diodes connected to the base, thus
two diodes in series with the base of transistors Q1 and Q1'. making the circuit less efficient for analog amplification.
The total harmonic distortion (THD), using simulation, is Keeping the transistors out of the saturation region is also
dramatically reduced from 11.91% to 0.02% at 1kHz by important because the switching speed of a BJT is slower if it
incorporating an operational amplifier with negative feedback, has to switch from the saturation region to the active region
which is proposed as a Class-G/FB (Class-G with feedback). [2], [8]. To keep transistors Q2 and Q2' from exceeding the
It is shown that the addition of this feedback presents a reverse breakdown voltage, PN junction diodes were placed at
stability problem for the amplifier. A method for solving the the base of the transistors [2], [9]. This caused a need for
instability of the circuit was developed based on the beta additional diodes at the base of transistors Q1 and Q1' to
network analysis technique of [3]. This technique along with maintain the functionality of the circuit. To dramatically
reduce the crossover distortion and distortions due to the of
1
A. D. Downey was with the Department of Electrical and Computer the transistor changing with current, an operational amplifier
Engineering, Michigan State University, East Lansing, MI 48824 USA. He is
now with Armor Holdings, Aerospace & Defense Group, Sterling Heights, MI (op-amp) with feedback was used. This biases the basic Glass-
48314 USA (e-mail: downeyad@msu.edu). G stage to maintain an output voltage, which is a ratio of -RF/
G. M. Wierzba is with the Department of Electrical and Computer RIN for various values of VIN. Adding the op-amp improves
Engineering, Michigan State University, East Lansing, MI 48824 USA (e-
mail: wierzba@msu.edu). the performance of the Class-G amplifier, but the current from
Contributed Paper
Manuscript received August 16, 2007 0098 3063/07/$20.00 2007 IEEE
1538 IEEE Transactions on Consumer Electronics, Vol. 53, No. 4, NOVEMBER 2007

the op-amp may limit the maximum voltage swing of the but would, however, allow high frequencies to appear in the
circuit. A UA741 op-amp was used to show that this new output stage of the amplifier if they were present. Also note
configuration of power amplifier works even with a low that the power supply values used in this simulation were +/-
performance op-amp. A UA741 op-amp can be powered with 15V and +/- 5V.
+/- 18 volts. In order to maximize the voltage swing out of RF
the op-amp without current limiting (~25mA), another Class- R L
V2
B stage (using 2N3904 and 2N3906 transistors) was added to
RIN V1
the output of the op-amp. The Class-B stage will cause all the
base currents for transistors Q1, Q1', Q2, and Q2' to come
VIN
from the larger power supplies (V2 and V2') instead of from
the op-amp. The smaller power supplies, V1 and V1', were -
VNOISE
chosen to be 1/3 of the larger power supplies to achieve +

maximum efficiency for audio signals that have a large peak- RL


to-average ratio [1], [2], [9]. A 10 load resistance was used
for testing this circuit. V1'

V2' R L
III. INITIAL EXPERIMENTAL RESULTS
Fig. 3: Schematic for testing stability.
Experimental results of the described circuit, which was
assembled on a protoboard, showed that adding negative The circuit in Fig. 3 has a small lossy inductance added to
feedback presented a stability problem with the amplifier. the large power supply lines. It also has VIN of 250Hz and an
High frequency oscillations appeared in the output of the added noise signal VNOISE that is a 1MHz square wave.
Class-G/FB amplifier (see Fig. 2) when switched mode power Many frequencies will trigger the circuit to become unstable
supplies were used. The circuit continued to be unstable with during a transient response; a 1MHz square wave was used for
high frequency oscillations when the circuit was tested using demonstration. Other waveforms rich in harmonics can also
four, 6-volt lantern batteries in place of the switched mode trigger instabilities. The SPICE output of this circuit is shown
power supplies to give +/- 6V and +/- 12V. in Fig. 4. In most of the output wave, remnants of the 1MHz
signal appeared but were attenuated. However, when the
larger power supplies are invoked with the appropriate input,
VOUT of op-amp the noise signal has triggered high frequency oscillations
(~20MHz) at the top and bottom of the waveform. This
output is very similar to the output that was collected in the
lab, however, lab data only showed instability on the positive
side of the output wave.

5.0V
VOUT across RL

Fig. 2: Oscilloscope output of VOUT across RL and VOUT of the op-amp.


The x-axis is 200s/div and the y-axis is 5V/div. The input signal
frequency is 1kHz.
0V
IV. IDENTIFYING THE INSTABILITY
The time domain simulated circuit did not show the high
frequency oscillations in the output even when noise was
added to the input (small high frequency signal tested at many
frequencies between 100kHz and 1MHz). Since the simulated -5.0V
data was not matching the lab data, the simulated circuit 1.2ms 2.0ms 3.0ms
model was revised. Because the change in current of the V(19)
power supplies with respect to time was high (di/dt), it was Time
conjectured that inductance in the power supply leads would Fig. 4: SPICE plot of VOUT across RL with simulated noise (1MHz square
wave, 1V amplitude) showing instability only at the top and bottom
cause problems with the output of the circuit. To see how the portion of the output wave.
circuit would behave if the power supply lines were allowed
to oscillate, a small inductance, 1H, in series with a small The discrepancy between the SPICE output showing
resistor, 1, was added to the large power supplies. This symmetrical instability points and lab results showing
would not affect the DC voltages needed to power the op-amp instability only on the positive side of the output wave was
A. D. Downey and G. M. Wierzba: A Class-G/FB Audio Amplifier 1539

further investigated. Due to the symmetrical circuit important feature of this method is that it is topologically
topology, it was conjectured that there was a problem with independent.
the macromodel for the op-amp being used. The SPICE Theorem 1 from [3] states that given a single op-amp
circuit uses a UA741 macromodel for the op-amp provided network as shown in Fig. 6, the transfer function,
by the simulation software. This macromodel was replaced G = Vout / Vin , is of the form
with a device level model for an ICL8741 op-amp [10]. As
shown in Fig. 5, only the positive side of the waveform 1 + 1 / ( A ') 1 + A '
shows instability. This non-symmetric behavior is believed G=K =K (1)
1 + 1/(A ) ' 1 + A
to be due to the non-symmetric impedance between the
power supply pins of the op-amp to the output pin of the op-
where A is the open-loop differential gain of the op-amp, K is
amp. One contributing factor may come from the substrate
of all the transistors in the 741 op-amp being connected to a the voltage transfer function using an ideal op-amp, is a
the negative supply pin. The macromodel for the UA741 voltage transfer function with Vin shorted and ' is a voltage
does not model the impedance from the power supply pins transfer function with Vin open-circuited and an ideal op-amp
to the output pin of the op-amp. Using the ICL8741 op-amp
placed from the output to input. K, , and ' are the
explains the non-symmetrical output behavior. Modeling
responses of the configurations shown in Fig. 7, Fig. 8, and
the impedance between the power supply pins of the op-amp
Fig. 9, respectively.
to its output needs further investigation and is not discussed
here. The remainder of this paper will use the UA741
V OUT
macromodel in the circuit analysis and acknowledge that Remaining Network
other circuits for analysis may require a more complete V IN
e a 11 a 12 VIN
macromodel, however, the one used here will be adequate =
for this circuit. VOUT a 21 a 22 v

5.0V
v
+ e -

-Ae

Fig. 6: Single op-amp network.


0V
V OUT
Remaining Network
V IN

-5.0V Ideal v
+ e - +
1.2ms 2.0ms 3.0ms -
V(19)
Fig. 7: K network where K = VOUT / VIN .
Time
Fig. 5: SPICE plot of VOUT across RL with simulated noise as in Fig. 4
except using a full model for the 741 op-amp. Instability is only found at V IN V OUT
Remaining Network
the top of the output wave.

With a SPICE circuit model that behaves similar to


experimental circuit, the next step was to analyze why this
inductance causes the circuit to be unstable. One method for
analyzing the stability of an amplifier with feedback is to do a
beta network analysis. + e -

V. IDENTIFYING INSTABILITY - BETA NETWORK ANALYSIS v


The beta network analysis [3] is a general method for
analyzing single, finite gain op-amp circuits. This technique
Fig. 8: network where = e / v .
is particularly useful for designing stable circuits. One
1540 IEEE Transactions on Consumer Electronics, Vol. 53, No. 4, NOVEMBER 2007

R2
-
+
Ideal
Remaining Network R1 Z out
V IN V OUT

Z in ZL

+ e -
+ e -
v
v
Fig. 9: ' network where '= e / v .

An example of creating the beta networks is given for the Fig. 12: Network.
inverting amplifier shown in Fig. 10 where the non-ideal op-
amp has an input impedance Zin, an output impedance Zout, Ideal -
and an open-loop gain A. The first step in creating the beta +
networks is to identify the Remaining Network shown in
Fig. 6. This is done by finding the terminals associated with R2
the voltage-controlled voltage source with gain A as shown in
Fig. 11. The and ' networks are shown in Fig. 12 and Fig.
R1 Z out
13.
R2
(a)
R1
V IN - Z in ZL
+
+
ZL V
OUT
-

R2
+ e -
(b)
R1 Z out
V IN v
- +
VX Z in ZL V
AVX -
OUT
+

Non-ideal op-amp Fig. 13: ' Network.

Fig. 10: (a) Inverting amplifier. (b) Replacing the op-amp with the non-
ideal op-amp model. This technique of using a circuit to describe and '
allows the use of CAD programs to find the voltage transfer
R2
functions, which can be particularly useful if the beta
R1 Z out V OUT networks are complicated. Furthermore, if the original
V IN
- network is found to be unstable or marginally stable, then
VX
the required circuit modifications to the beta networks can
Z in ZL be determined. These circuit modifications can then be
+
reverse-engineered into the original circuit to yield a stable
design.
Remaining
+ e - Network Right-half s-plane zeros of ' and 1 + A will cause the
system to be unstable. If right-half s-plane zeros exist in the
AVX = -Ae
' network, then the Bode plot of the magnitude of the
voltage transfer function would have positive slope at the
zeros cut-off frequency and this would be further
Fig. 11: Re-drawing to identify remaining network. substantiated with the phase response. A phase margin test
A. D. Downey and G. M. Wierzba: A Class-G/FB Audio Amplifier 1541

on the magnitude and angle plots of A and can determine


if 1 + A has right-half s-plane zeros. The phase margin is 75
180 A calculated at the frequency where 1 / and
50
A intersect. A phase margin that is negative indicates
25
instability.
0
Although the phase margin calculation is very precise it ... VdB(77)
does not always give much insight as to how to make the 200d
circuit stable. Many use the rate-of-closure technique [11] to
provide a strategy for moving the zeros of 1 + A back into
the left-half s-plane. The rate-of-closure is defined as the 100d

slope of 1 / minus the slope of A calculated where 1 /


SEL>>
and A intersect. 0d
1.0Hz 1.0KHz 1.0MHz 100MHz
The stability of the circuit can roughly be estimated if ... Vp(77)
the rate of closure between 1 / and A is less than Frequency
Fig. 15: SPICE plots showing the magnitude and phase of the ' network
12dB/octave. In order to guarantee a phase margin of 45 using many signal levels over the range of the amplifier.
degrees or more, the rate of closure is usually chosen to
be 6dB/octave. Once design modifications are made, a For most of the signal levels tested, the phase margin was
precise phase margin calculation can be done to ensure positive which indicated that the circuit would be stable.
stability. However, there were two signal levels (small region centered
The Class-G/FB amplifier beta network includes large approximately around 6.133V and -6.232V) that caused the
signal non-linear devices (diodes and transistors). These gain of 1/ to cross the open-loop gain of the op-amp a second
devices can be approximated to be linear over a small time (Fig. 14)! It has been shown by example that a beta
range. When small signal models are used for signal network analysis can be used to test for stability when the
levels of the Class-G stage close to zero, the transistors graph of 1 / and A versus frequency intersect at multiple
connected to the larger power supplies will be in the cut- points and that all intersections must have a positive phase
off region and will have different values for their small margin to be stable [8]. The phase margin at these two points
signal models than if the signal level is large enough to (-157 and -138 for signal levels 6.133V and -6.232V,
include the use of the larger power supplies. Therefore, it respectively) indicated that the circuit would be unstable.
is necessary to test many signal levels over the range of To analyze the beta network in further detail, high
the amplifiers output. Observing 1/ compared to the frequency models were used for the transistors (Giacoletto's
open-loop gain of the op-amp is done to test for the zeros hybrid- model [11] shown in Fig. 16) and the diodes.
of 1 + A (Fig. 14), and observing ' is needed to test for
the zeros of ' (Fig. 15, which shows no zeros below C
100MHz). B

C_BC
C_BE +
Vpi Rpi Ro
100 - gmVpi
|A|

| 1/ | E
50 VBIAS = 6.133 Fig. 16: Giacoletto hybrid- high frequency transistor model.

The full beta network is shown in Fig. 17. The values for the
0 transistor and the diode models were obtained from SPICE
VBIAS = -6.232 (operating point information) by setting the input of the
original circuit to the desired signal level and observing the
-50 small signal bias solution from the SPICE output file. The
1.0Hz 1.0KHz 1.0MHz
beta network was then simplified to just focus on what was
-VdB(77) VdB(73)
Frequency causing the gain of 1/ to cross the open-loop gain of the op-
amp a second time. This was done by eliminating circuit
Fig. 14: network analysis Graph of 1 / and A . For VBIAS = components and visually inspecting the SPICE plotted output
6.133V and -6.232V, the second crossing point is at 23.6MHz and to ensure the main feature of the 1/ network crossing the
20.8MHz, respectively.
1542 IEEE Transactions on Consumer Electronics, Vol. 53, No. 4, NOVEMBER 2007

open-loop gain of the op-amp a second time was TABLE I


NUMERICAL RESULTS OF REDUCED BETA NETWORK FOR TWO SIGNAL
approximately unaffected. Fig. 18 (disregard RADD and LEVELS WHICH WERE GOVERNED BY THE TRANSFER FUNCTION SHOWN IN
CADD at this point) shows the simplified beta network (2).
when the signal level was at 6.133V. A similar circuit was Network 1 Network 2
found for when the signal level was -6.232V. In order for VBIAS (V) 6.133 -6.232
the graph of the gain of 1/ versus frequency to dip in the A 0.162 0.187
negative direction with a large negative slope like it shows, f1 = 1 / 2 (MHz) 23.35 20.25
the Laplace Transform of the output equation probably
f 2 = 2 / 2 (MHz) 22.4 19.3
contains a second order zero with a very high Q (quality
factor). Sspice shows that for this reduced beta network, the f 3 = 3 / 2 (MHz) 1440 1080
transfer function takes on the form shown in (2). Sspice Q1
also provides numerical results for this transfer function,
Q2 507 391
which are shown in TABLE I.

s2 s
A 2 + + 1
VOUT 1 Q1
= 1 (2)
VIN s s2 s
+ 1 2 + + 1
3 2 2 Q2

C_DB2
LV2 RLV2

C_BC
R_DB2 +
Ro
Vpi
C_BE Rpi
- gm*Vpi
C_D1
C_BC C_DB1A C_DB1B

C_BE C_BC R_D1


+ R_DB1A R_DB1B + Ro
Ro
Vpi Vpi Rpi
Rpi
- gm*Vpi - gm*Vpi
C_BE RF RL

+ C_BE
Rpi Ri
Vpi Ro Ci RIN
+
-
gm*Vpi C_DB1AP C_DB1BP Vpi Rpi
C_BE
- gm*Vpi Ro
C_BC C_D2
Ro R_DB1AP R_DB1BP C_BC

R_D2
VBIAS C_BE
+
Ro
C_DB2P Vpi Rpi
- gm*Vpi
VAC
R_DB2P C_BC LV2P RLV2P

Fig. 17: Full network high frequency model.


A. D. Downey and G. M. Wierzba: A Class-G/FB Audio Amplifier 1543

For VBIAS = 6.133V, Sspice provides a symbolic result (see Fig. 20) and in the lab (see Fig. 21) where both
for this reduced beta network circuit shown in (3). The verified a stable Class-G/FB amplifier. Therefore, it can
numerator of the VOUT equation shows a zero at frequency, be concluded that one way to help eliminate stability
fc N , and a Q value, QN , given in (4). Using the problems for this amplifier design is to include RADD
approximation option in Sspice with a threshold of 0.9, the and CADD across the base and collector of the transistors
denominator shows a zero at frequency, fc D , and a Q connected to the larger power supplies.
value, QD , given in (5).
GMAV(2,3)


( )
LV 2 (CBCA + CBC 2 ) s 2 + 1

RO CBC_A R_DB1A RPI_1

VOUT = RO GMA RL REQDB1B (3)


R_DB1B

[ ]
VIN
1 1
(LV 2 CBC 2 ) s + 1
2 1/2RL VOUT
CBCA s + CBC_2
CADD
RL RO LV2
RADD 1/2RL

1 1
fc N
2 LV 2 (CBCA + CBC 2) ) (4) Fig. 18: Simplified schematic of the network when VBIAS = 6.133V.
Adding RADD and CADD lowers the Q of the beta network to make it
QN stable.

1 1
fc D
2 LV 2 CBC 2 (5) 1K 15V
10
QD 0.01F
15V 1N4148 5V
1K TIP31
The stability problem was solved by adding a small Q2N3904 1N4148 1N4148
resistance, RADD, into the circuit (which connects the VIN -
TIP31 1N5817

base to the collector of transistor Q2) to lower the Q value + 1N4148 1N4148
UA741 TIP32 1N5817
enough to make this condition stable. This is effectively 10
Q2N3906 1N4148
dampening the parallel LC circuit, seen in Fig. 18, with a TIP32
-5V
resistor where Q = R C/L . For VBIAS = 6.133V and -15V 0.01F
10
RADD = 10, Q 1 and Q 2 lowered from infinity and 507 -15V
to 0.068 and 0.074, respectively. By adding a capacitor
Fig. 19: Schematic for the final design of the Class-G/FB amplifier.
CADD (0.01uF) in series with RADD (10) as shown in
Fig. 18, the desired effect can be achieved without the
major power losses at low frequencies. The value of 5.0V
CADD was chosen so that a pole was added to the 1/
network at approximately 1.59MHz (arbitrary value,
much larger than the 20kHz audio frequency, but much
lower than the resonating frequency of the LC circuit).
At higher frequencies, CADD will effectively be a short
circuit. Adding the capacitor also shifted the frequencies
0V
of the transfer function causing the transfer function to
reduce down to only a pole at 1.6GHz (using Sspice).
This indicates that the dip in the 1/ network (at
~20MHz) has been eliminated making the circuit stable.
The values for RADD and CADD can be varied
depending on the value of the inductance in the power
supply lines and the capacitive component between the -5.0V
base and collector of the transistors used. To fix the case 1.2ms 2.0ms 3.0ms
when the signal level was -6.233V, RADD and CADD V(19)
were also used to connect the base to the collector of Time
transistor Q2'. The final design is shown in Fig. 19 with Fig. 20: SPICE plot showing stable VOUT across RL after the addition of
the SPICE circuit file shown in Appendix A. The RADD and CADD while using simulated noise (1MHz square wave, 1V
addition of RADD and CADD were tested using SPICE amplitude).
1544 IEEE Transactions on Consumer Electronics, Vol. 53, No. 4, NOVEMBER 2007

VOUT of op-amp 70%

60%

50%

Efficiency
40%

VOUT across RL 30%


Class G Sim
20% Class G Exp.
Class B Sim
Fig. 21: Oscilloscope output of VOUT across RL and VOUT of the op-amp. 10%
The x-axis is 200s/div and the y-axis is 5V/div. The input signal Class B Exp.
frequency is 1kHz.
0%
0 5 10 15
VOUT (V)
I. EFFICIENCY OF FINAL DESIGN
The efficiency of the Class-G/FB amplifier can be Fig. 23: Efficiency of Class-G/FB and Class-B/FB using 1kHz signal.
measured by dividing the average power of the load by
the average power of the power supplies. To compare the with feedback, identify the stability problem of the Class-
efficiency of the Class-G/FB amplifier to the Class-B/FB G/FB, and offer a method of solving this problem that
amplifier, a Class-B/FB amplifier circuit was modeled could be used in other amplifier designs. Therefore,
shown in Fig. 22. This Class-B/FB circuit uses an op- efforts to optimize this circuit for maximum efficiency
amp and an additional Class-B stage because the UA741 and lowest THD are ongoing.
op-amp cannot provide enough current for the voltage
swing required. Also note that the Class-B/FB amplifier
can have a voltage swing that is closer to the power rails
than the Class-G/FB amplifier. However, only the full II. CONCLUSION
voltage range of the Class-G/FB amplifier was used to This article has shown the basic design of a Class-G/FB
test the efficiency of the Class-B design. The power amplifier that uses bipolar junction transistors. Circuit
supplies were at +/- 15 volts but the output voltage range modeling and equations were used to get the desired
was from 0 to +/- 10.9 volts. The efficiency of the Class- performance with a limited number of parts in effort to
B/FB amplifier will continue to increase a little more as keep the design relatively simple. An operational amplifier
the input voltage increases before clipping begins. The with feedback was used to lower the THD from the basic
graph of the efficiency is shown in Fig. 23. This graph design. Data collected from the lab of the Class-G/FB
does show that the efficiency of the Class-G/FB amplifier amplifier with the op-amp showed an output that was only
is better than the Class-B/FB amplifier when the signal is partially stable.
smaller than the lower power supplies. The main purpose This stability problem caused concern in the performance
of this work was to show a working Class-G amplifier of the Class-G/FB amplifier and needed to be solved before
further analyzing this amplifier. Before any methods could
be used to identify the source of the problem, the simulated
VHIGH circuit model had to be revised to match the data collected
in the lab. This was done by making sure the op-amp was
Q2N3904 fully modeled and by including inductances associated with
UA741
TIP31 the power supply wires. Once the Class-G/FB amplifier
VIN + was modeled, the cause of the stability problem was
- identified using a variation on the beta network analysis
TIP32
RL method. This involved using a small signal input and
Q2N3906
changing the input signal level because the output was only
VLOW unstable at certain levels. With the help of Sspice, a
symbolic solution to the problem was found and
Fig. 22: Schematic of Class-B/FB amplifier for comparison. experimentally confirmed to work.
A. D. Downey and G. M. Wierzba: A Class-G/FB Audio Amplifier 1545

APPENDIX A - SPICE CIRCUIT FILE [4] Wierzba, G. M., Sspice User Manual version 1.0. East Lansing, MI:
Michigan State University Instructional Media Center, 1991.
Class G Amplifier
[5] Wierzba, G. M., Joshi, V., Srivastava, A., Noren, K. V., and Svoboda, J.
VIN 1 A DC 0V AC 1 SIN 0 -6 250
VNOISE A 0 PULSE [-.5 .5 1U 1N 1N .5U 1U] A., "Sspice-Symbolic SPICE for linear active circuits," Proc. 32nd
V2 27 0 15 Midwest Symp. Circuits and Systems, Urbana IL, pp. 1197-1201, Aug.
V1 3 0 5 1989.
V1P 4 0 -5 [6] Li, S. S., Semiconductor Physical Electronics. New York: Plenum
V2P 26 0 -15 Press, 1993.
RLV2P 25 26 1 [7] Self, D., A new look at class-G power, Electronics World, vol. 107,
RLV2 24 27 1 pp. 900-905, Dec. 2002.
LVP2 5 25 1U [8] Downey, A. D., Class G Amplifier, MS thesis, Michigan State
LV2 2 24 1U University, 2002.
X1 0 10 2 5 11 UA741 [9] Feldman, L., Class G high efficiency Hi-Fi amplifier, Radio
RIN 1 10 1K
RF 19 10 1K Electronics, vol. 87, pp. 47-49, Aug 1976.
CADD1 2 22 0.01U [10] Boyle, G. R., Cohn, B. M., Pederson, D. O., and Solomon, J. E.,
RADD1 22 13 10 Macromodeling of integrated circuit operational amplifiers, IEEE J.
CADD2 5 23 0.01U Solid-State Circuits, vol. SC-9, pp. 353-364, Dec. 1974.
RADD2 23 20 10 [11] Sedra, A. S., and Smith, K. C., Microelectronic Circuits. New York:
QA 2 11 12 Q2N3904 Oxford University Press, 2004.
QB 5 11 12 Q2N3906
Q2 2 13 16 TIP31
Q1 16 15 19 TIP31
Q1P 21 18 19 TIP32
Q2P 5 20 21 TIP32 Adam D. Downey received the B.S., M.S. and Ph.D.
DB2 12 13 D1N4148 degrees in electrical engineering from Michigan State
DB1A 12 14 D1N4148 University in 2000, 2002, and 2006, respectively. He
DB1B 14 15 D1N4148 was a Research Associate at Michigan State University
DB1AP 18 17 D1N4148 and joined Armor Holdings, Aerospace and Defense
DB1BP 17 12 D1N4148 Group in 2007.
DB2P 20 12 D1N4148
D1 3 16 D1N5817
D2 21 4 D1N5817
RL 19 0 10
.TRAN 1U 4000U 0 1U Gregory M. Wierzba (S70-M78-SM92) received the
* LIB FILES FROM PSPICE B.S. degree in electrical engineering from Marquette
.LIB OPAMP.LIB University, Milwaukee, WI, in 1972. He received the
.LIB DIODE.LIB M.S. and Ph. D. degrees in electrical engineering from
.LIB PWRBJT.LIB the University of Wisconsin, Madison, in 1974 and 1978,
.LIB BIPOLAR.LIB respectively. He joined the faculty in the Department of
.OP
.FOUR 1K 20 V(19) Electrical and Computer Engineering at the University of
.PROBE South Carolina, Columbia in 1978. In 1984, he joined the Department of
.END Electrical and Computer Engineering at Michigan State University as an
Associate Professor. His teaching and research interests are in field of analog
electronics. Dr. Wierzba is the recipient of the 1986 Myril B. Reed Best Paper
REFERENCES Award of the Midwest Symposium on Circuits and Systems; the 1992, 2000,
[1] Raab, F., Average efficiency of class-G power amplifiers, IEEE Trans. 2001, 2003 Withrow Teaching Excellence Award in Electrical and Computer
Consum. Electron., vol. CE-32, no. 2, pp. 145-150, May 1996. Engineering of the Michigan State University Engineering Alumni
[2] Sampei, T., Ohashi, S., Ohta, Y., and Inoue, S., Highest efficiency and Association; the 2002 All University Quality in Undergraduate Teaching
super quality audio amplifier using MOS power FETs in class G Award of the Michigan State University Alumni Club of Mid-Michigan; and
operation, IEEE Trans. Consum. Electron., vol. CE-24, no. 3, pp. 300- the 2007 Section Conference Outstanding Teaching Award of the North-
307, Aug. 1978. Central Section of the American Society for Engineering Education.
[3] Esmelioglu, S. and Wierzba, G. M., "Operational amplifier feedback
analysis using beta networks," Proc. 25th Midwest Symp. Circuits and
Systems, Houghton MI, pp. 489-493, Aug. 1982.