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Horas practicas 54
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Horas totales por semana 6
Horas teoricas 36
OBJETIVO DE LA ASIGNATURA
UNIDAD 1
Lenguaje VHDL
ENTITY
<entity_names> is
Generic declaretions
Ejemplo
ENTITY <entity_name> IS
Generic declaration
PORT (
SIGNAL clk, clr: IN BIT;
Q: OUT BIT
);
MORE EXAMPLES
GENERIC (
--NOTE constant is assumed and is not required tphz, tplz :TIME := 3ns;
);
ARCHITECTURE
CONFIGURATION
PACKAGE