Study of BICMOS(Bipolar Complementary Metal
Oxide Semiconductor) Technology
AGNIBHA DASGUPTA
Student of Dept. of Microelectronics & VLSI Technology
Maulana Abul Kalam Azad University of Technology, WB
(Formerly known as West Bengal University of Technology)
dasgupta.rony7@gmail.com
Abstract: The evolution and adaptation of the
microelectronics industry to the BICMOS technology
and its extended families provide a paradigm shift in the
development of high-speed, low-power digital and
analog integrated circuits. It has been proven in most
literatures that the integration of bipolar and CMOS
technologies are advantageous when used in optimized
microelectronic circuitry in different applications such as
telecommunications, mixed-signal, and radio-frequency
microelectronics. However, some problems still arise
when it comes to the design of such integrated circuits
due to its complexity. Nevertheless, researchers still
found ways to solve such problems using different
circuit configuration techniques. A review on the bipolar
and CMOS technologies is riveted concentrating on their
basic properties, features and advantages when applied
to microelectronic circuitry. The hybridization of bipolar
and CMOS technologies is also discussed here showing
its effectiveness that causes its emergence, including
factors that have driven the addition of bipolar
technology to CMOS, resulting into the emergence
BICMOS technology
I. INTRODUCTION
BICMOS has faced, as any emerging technology, fierce
opposition, but nevertheless has been widely accepted.
The need for BICMOS has been and still is a
controversial issue .The cost of high performance
BICMOS process speaks against it. However there are
other arguments supporting the need for such a
technology .The comparison between the cost of CMOS
and BICMOS is not trivial especially if we account for
the increasing expenses of sealing CMOS .In other
words adding bipolar to an existing CMOS process
might be cheaper than sealing CMOS to obtain the same
performance improvement. On the other hand ,the high
cost of BICMOS may be justified by the high
performance it can offer .In general ,the application itself
will dictate the technology that is to be used .If CMOS
alone can satisfy the requirements ,then it is more cost
effective to use CMOS. Yet there are applications where
the requirements can only be satisfied by using
CMOS .There are currently commercial BICMOS digital
products such as high speed SRAMs, fast
microprocessors, and gate arrays in addition to digital,
analog and mixed signal BICMOS ASICs.
The technology for BICMOS fabrication has matched
over the last decade, yet the development of circuits and
systems for such a technology is still lagging .There is a
great interest among digital or analog circuits and
systems designers to develop techniques to exploit the
flexibility that BICMOS offers.
II. EVOLUTION OF BICMOS
Most early BICMOS applications were analog;
BICMOS operational amplifiers were introduced in the
mid-70s followed by BICMOS power ICs. Digital LSI
BICMOS devices were introduced in the mid-80s,
motivated by high power dissipation of bipolar circuits,
speed limitations of MOS circuits & a need for high I/O
throughput .Development of VLSI BICMOS resulted in
very high performance memories, gate arrays & micro-
processors BICMOS follows the same scaling curve as
mainstream CMOS technology resulting in explosive
growth in BICMOS product growth. BICMOS has been
established as the technology of choice for high speed
VLSI.
 III. THE BICMOS PROCESS
BICMOS requires both bipolar junction and CMOS
transistors, in which CMOS requires both nMOS and
pMOS transistors. In the creation of CMOS, one
complication is that an n- channel MOSFET requires a
p-type background, while a p-channel MOSFET requires
an n-type background. A CMOS process basically
fabricates the circuit in bulk silicon. A single n-epitaxial
layer is used to implement both the PMOS transistors
and bipolar NPN transistors. Its resistivity is chosen so
that it can support both devices. An n+-buried layer is
deposited below the epitaxial layer to reduce the
collector resistance of the bipolar device, which
simultaneously increases the immunity to latch up. The
p-buried layer improves the packing density, because the
collector-collector spacing of the bipolar devices can be
reduced. It comes at the expense of an increased
collector-substrate capacitance. This technology opens a
wealth of new opportunities, because it is now possible
to combine the high-density integration of MOS logic
with the current-driving capabilities of bipolar
transistors. Another method which is much more
superior to the use of bulk silicon is to use an insulating
substrate. However, the latter method is costly than the
previous one.
Fig.1.1 Cross-Sectional view of BICMOS
IV. BICMOS Circuit Characteristics And
Advantages
o Improved speed over CMOS
o Flexible I/O (ECL, CMOS, or TTL)
o High performance analog
o Latch up immunity
o High impedance input (FET)
o High gain (BJT)
o Low 1/f noise
o >1 GHz toggle frequency
V. COMPARISON OF BICMOS AND
CMOS TECHNOLOGIES
The BICMOS gates perform in the same manner as
the CMOS inverter in terms of power consumption,
because both gates display almost no static power
consumption. When comparing BICMOS and CMOS in
driving small capacitive loads, their performance are
comparable, however, making BICMOS consume more
power than CMOS. On the other hand, driving larger
capacitive loads makes BICMOS in the advantage of
consuming less power than CMOS, because the
construction of CMOS inverter chains are needed to
drive large capacitance loads, which is not needed in
BICMOS. The BICMOS inverter exhibits a substantial
speed advantage over CMOS inverters, especially when
driving large capacitive loads. This is due to the bipolar
transistors capability of effectively multiplying its
current. For very low capacitive loads, the CMOS gate is
faster than its BICMOS counterpart due to small values
of Cint. This makes BICMOS ineffective when it comes to
the implementation of internal gates for logic structures
such as ALUs, where associated load capacitances are
small. BICMOS devices have speed degradation in the
low supply voltage region and also BICMOS is having
greater manufacturing complexity than.
VI.THE BICMOS INVERTER
Two additional enhancement-type nMOS devices have
been added (T5 and T6).
These transistors provide discharge paths for transistor
base currents during turn-off.
Without T5, the output low voltage cannot fall below the
base to emitter voltage VBE of T3.
Vin = 0:
T1 is off. Therefore T3 is non-conducting
T2 ON - supplies current to base of T4
T4 base voltage set to Vdd.
T5 is turned on & clamps base of T3 to GND. T3 is
turned off.
T4 conducts & acts as current source to charge load
CL towards Vdd.
Vout rises to Vdd Vbe (of T4) Vin = Vd :
T2 is off
T1 is on and supplies current to the base of T3
T6 is turned on and clamps the base of T4 to GND. T4 is
turned off.
T3 conducts & acts as a current sink to discharge load
CL towards 0V
Vout falls to 0V+ VCE SAT (of T3)
Again, this BICMOS gate does not swing rail to
rail. Hence some finite power is dissipated when driving
another CMOS or BICMOS gate. The leakage
component of power dissipation can be reduced by
varying the BICMOS device parameters
Fig: 1.2 The BICMOS INVERTER
VII. Properties of BICMOS Inverter
o Large driving capability of BICMOS inverter is
one of the most significant advantages over
conventional CMOS buffer circuits.
o BICMOS logic gate doesnt dissipates any
significant amount of static power during steady
state operation.
o BICMOS logic family has about same
power delay product as conventional CMOS
but the gate delay is smaller.
VIII. More Advanced BICMOS
Structures
Various types of BICMOS gates have been devised to
overcome the shortcomings of the conventional
BICMOS gate
BICMOS devices are available which provide the full
Vdd -> GND voltage swing
There is a common theme underlying all BICMOS gates:
all have a common basic structure of a MOSFET (p or n)
driving a bipolar and Transistor (NPN or PNP) which
drives the output
BICMOS can provide applications with CMOS power &
densities at speeds which were previously the exclusive
domain of bipolar. This has been demonstrated in
applications ranging from static RAMs to gate arrays to
u-processors.
BICMOS fills the market niche between
very high speed, but power hungry bipolar ECL
(Emitter Coupled Logic)
very high density, medium speed CMOS
When the power budget is unconstrained, a
bipolar technology optimized for speed will
almost always be faster than BICMOS and will
most likely be selected.
However, when a finite power budget exists, the
ability to focus power where it is required
usually allows BICMOS speed performance to
surpass that of bipolar
The concept of system on a chip becomes a
reality with BICMOS.
Most gates in ROM, ALU, register subsystems
etc. do not have to drive large capacitive loads.
 Hence the use of BICMOS technology would
give no speed advantage.
IX. BICMOS Fabrication
Theoretically there should be little difficulty in
extending CMOS fab processes to include bipolar as
well as MOS transistors. In fact, a problem of p-well
and n-well CMOS processing is that parasitic bipolar
transistors are inadvertently formed as part of the
outcome of fabrication (see section on CMOS latch up).
Production of NPN bipolar transistors with good
performance characteristics can be achieved, e.g., by
extending the standard n-well CMOS processing to
include further masks to add two additional layers; the
n+ sub collector and p+ base layers. The NPN transistor
is formed an n-well & the additional p + base region is
located in the well to form the p-base region of the
transistor. The second additional layer, the buried n+ sub
collector (BCCD) is added to reduce the n-well
(collector) resistance & thus improve the quality of the
bipolar transistor.
Fig: 1.3 Arrangement of BICMOS NPN Transistor
X. Disadvantages with BICMOS
Technology
Main disadvantage: greater process complexity
compared to CMOS results in a 1.25 -> 1.4 times
increase in die costs over conventional CMOS. Taking
into account packaging costs, the total manufacturing
costs of supplying a BICMOS chip ranges from 1.1->
1.3 times that of CMOS. However, as CMOS
complexity has increased, the percentage difference
between CMOS and BICMOS mask steps has decreased.
Therefore, just as power dissipation constraints
motivated the switch from nMOS to CMOS in the late
70s, performance requirements motivated a switch from
CMOS to BICMOS in the late 80s for VLSI products
requiring the highest speed levels. Capital costs of
investing in continually smaller (<1um) CMOS
technology rises exponentially, while the requirement of
low power supplies for sub-0.5um CMOS results in
degradation of performance. Since BICMOS does not
have to be scaled as aggressively as CMOS, existing
fabrications can be utilized resulting in lower capital
costs. Extra costs incurred in developing a BICMOS
technology is more than offset by the fact that the
enhanced chip performance obtained extends the
usefulness of manufacturing equipment & clean rooms
by at least one technology generation.
X. BICMOS Technology Present and
Future
An application of the technology so far described is
introduced by Agere systems, Orlando, Florida for a 10
GB/s 16:1 multiplexer and 10 GHz clock synthesizer.
The chip integrates 4,000 bipolar and 3,100 MOS
devices on a 5.5 X 5.5-mm die and is packaged in a 225-
pin ceramic ball grid array. The 10-GHz oscillator core
used MOM capacitors, pMOS varactors, base resistors,
and a chip inductor with a Q of 16 at 10 GHz. To extend
this BICMOS process in to next generation, Texas
instruments is tapping the benefit of complementary
SiGe bipolar transistor. TI has developed a third
generation of fully isolated complimentary SiGe
BICMOS for ultra-high speed precision analog and
mixed signal IC s. this process is expected to go into NITTTR Chandigarh, India Rajesh Mehra2 Associate
volume manufacturing by the end of this year. Professor (ECE) NITTTR, Chandigarh, India

XI. Conclusion

BICMOS technology significantly enhances speed

performance while incurring a negligible power and
penalty .Thus BICMOS can provide applications with
CMOS power and densities at speeds which were
previously the exclusive domain of bipolar .This has
been demonstrated in the applications ranging from
static RAMs to gate arrays to microprocessors .Thus the
concept of a system on a chip becomes reality with
BICMOS .The main disadvantage of BICMOS is greater
complexity, which results in a 1.25-1.4X increase in die
costs over CMOS .Taking into account packaging
costs ,the total manufacturing cost of supplying a
BICMOS chip ranges from 1.1-1.3X that of CMOS
.BICMOS is now being demonstrated at 0.5m.Thus
BICMOS will not necessarily displace CMOS at the
technology of the 1990s,it will have significant impact
on the Integrated Circuit Industry.

XII. Reference

Books

o Digital BICMOS Integrated Circuit Design by

Sherif H.K. Embabi, Abdell atif Bellaouar,
Mohamed I. Elmasry

o Microelectronics by Adel S. Sedra, Kenneth C.

Smith

o Chip Design for Submicron VLSI: CMOS

Layout and Simulation by John P. Uyemura

o VLSI DESIGN by M. Michael Vai

o Digital Integrated Circuits: A Design Perspective

by J.M. Rabaey

Journals

International Journal of Engineering Trends and

Technology (IJETT) Volume 35 Number 13 - May
2016 ISSN: 2231-5381 http://www.ijettjournal.org Page
605 Dynamic circuits for CMOS and BICMOS low
power VLSI Design Naveen Kumar1 ME Student (ECE)