Avionics Lab Record

SNS COLLEGE OF TECHNOLOGY
(An Autonomous Institution)

Sathy Main Road, Vazhiyampalayam Pirivu,
Coimbatore -35
DEPARTMENT OF AERONAUTICAL ENGINEERING
AE404 AVIONICS LAB RECORD
Name : ,
Reg. No : ,
Sem / Year : ........,
Course : ...,
ACADEMIC YEAR: 2017-2018

SNS COLLEGE OF TECHNOLOGY
(An Autonomous Institution)
BONAFIDE CERTIFICATE
Certified that this is the bonafide Record of work done by
_______________________________________________ student of the AE 404
AVIONICS LABORATORY during the year 2017 to 2018.
SIGNATURE OF LAB-IN-CHARGE HEAD OF THE DEPARTMENT
Submitted for the End Semester Practical Examination held on
INTERNAL EXAMINER EXTERNAL EXAMINER

INDEX
SL.NO DATE DESCRIPTIONS MARKS SIGNATURE
6
7
10
11
12
13
I. DIGITAL ELECTRONICS
Exp. No: 01
ADDITION/SUBTRACTION OF BINARY NUMBERS
(A) Addition of Binary Numbers

AIM:
To design and construct half adder and Full adder, circuit and verify the truth Table
using Logic gates.
APPARATUS REQUIRED:
SL.NO COMPONENT SPECIFICATION QUANTITY
1 IC trainer kit --- 1
2 AND GATE IC 7408 1
3 X-OR GATE IC 7486 1
4 NOT GATE IC 7404 1
5 OR GATE IC 7432 1
THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
the sum [S] and other from the carry [C] into the higher adder position.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input. It
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR gate, carry output
will be taken from OR gate.
PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
RESULT:
Thus the design and construction of adder and subtractor circuits and verification of
truth table has been successfully executed.
(B) Subtraction of Binary Numbers
AIM:
To design and construct Half subtractor and Full subtractor circuit and verify the
truth Table using Logic gates.
APPARATUS REQUIRED:
2 AND GATE IC 7408 1
3 X-OR GATE IC 7486 1
5 OR GATE IC 7432 1
THEORY:
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND gate. The half subtractor
has two inputs and two outputs. The outputs are Difference [Diff] and Borrow [Borr]. The
difference can be applied using X-OR gate borrow output can be implemented using an AND
gate and an Inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half subtractor
put together gives a full subtractor. The first half subtractor will be C and AB.
PROCEDURE:
RESULT:
Thus the design and construction of subtractor circuits and verification of truth
table has been successfully executed.
Exp. No: 02
MULTIPLEXER/DEMULTIPLEXER CIRCUITS.
Design and Implementation Of Multiplexer And Demultiplexer

AIM:
To design and construct the multiplexer and Demultiplexer circuit and verify the
truth Table using Logic gates.
APPARATUS REQUIRED:
2 3 INPUT AND GATE IC 7411 2
4 OR GATE IC 7432 1
THEORY:
MULTIPLEXER:
A multiplexer (or mux) is a device that selects one of several analog or

digital input signals and forwards the selected input into a single line.
A multiplexer of 2n inputs has n select lines, which are used to select which input
line to send to the output. Multiplexers are mainly used to increase the amount of
data that can be sent over the network within a certain amount of time and
bandwidth.[1] A multiplexer is also called a data selector.
DEMULTIPLEXER:
A Demultiplexer (or demux) is a device taking a single input signal and selecting
one of many data-output-lines, which is connected to the single input. A multiplexer is
often used with a complementary Demultiplexer on the receiving end. The Demultiplexer
also called as Data distributer.
An electronic multiplexer can be considered as a multiple-input, single-output

switch, and a Demultiplexer as a single-input, multiple-output switch. The schematic
symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing
the input pins and the short parallel side containing the output pin. The schematic on the
right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right.
PROCEDURE:
RESULT:
Thus the design and construction of multiplexer and demultiplexer circuits and
verification of truth table has been successfully executed.
Exp. No: 03
ENCODER/DECODER CIRCUITS.
Design and Implementation Of Encoder And Decoder
AIM:
To design and construct the Encoder and Decoder circuit and verify the truth Table
using Logic gates.
APPARATUS REQUIRED:
2 3 INPUT NAND GATE IC 7410 2
4 OR GATE IC 7432 3
THEORY:
ENCODER:
A encoder is a combinational logic circuit that converts a binary integer value to

an associated pattern of output bits. They are used in a wide variety of applications,
including data multiplexing, seven segment displays, and memory address decoding.
A encoder is an electronic circuit with multiple data inputs and multiple outputs
that converts every unique combination of data input states into a specific combination of
output states. Depending on its function, a binary encoder will convert binary information
from 2n input signals to as many as n unique output signals.
DECODER:
A binary decoder is a combinational logic circuit that converts a binary integer

value to an associated pattern of output bits. They are used in a wide variety of
applications, including data De-multiplexing, seven segment displays, and memory
address decoding.
Depending on its function, a binary decoder will convert binary information from
n input signals to as many as 2n unique output signals.
PROCEDURE:
RESULT:
Thus the design and construction of encoder and decoder circuits and verification
of truth table has been successfully executed.
II. MICROPROCESSORS
INTRODUCTION TO 8085 MICROPROCESSOR
INTEL 8085 is one of the most popular 8-bit microprocessor capable of

addressing 64 KB of memory and its architecture is simple. The device has 40 pins,
requires +5 V power supply and can operate with 3MHz single phase clock.
ALU (Arithmetic Logic Unit):
The 8085A has a simple 8-bit ALU and it works in coordination with the
accumulator, temporary registers, 5 flags and arithmetic and logic circuits. ALU has
the capability of performing several mathematical and logical operations. The
temporary registers are used to hold the data during an arithmetic and logic operation.
The result is stored in the accumulator and the flags are set or reset according to the
result of the operation. The flags are affected by the arithmetic and logic operation.
They are as follows:
Sign Flag
After the execution of the arithmetic - logic operation if the bit D7 of
the result is 1, the sign flag is set. This flag is used with signed numbe rs. If
it is 1, it is a negative number and if it is 0, it is a positive number.
Zero Flag
The zero flag is set if the ALU operation results in zero. This flag is
modified by the result in the accumulator as well as in other registers.
Auxillary Carry Flag

In an arithmetic operation when a carry is generated by digit D3 and
passed on to D4, the auxillary flag is set.
Parity Flag
After arithmetic logic operation, if the result has an even number
of 1s the flag is set. If it has odd number of 1s it is reset.
Carry Flag
If an arithmetic operation results in a carry, the carry flag is set. The carry
flag also serves as a borrow flag for subtraction.
Timing and Control Unit
This unit synchronizes all the microprocessor operation with a clock and generates the
control signals necessary for communication between the microprocessor and peripherals.
The control signals RD (read) and WR (write) indicate the availability of data on the data
bus.
Instruction Register and Decoder
The instruction register and decoder are part of the ALU. When an instruction is fetched
from memory it is loaded in the instruction register. The decoder decodes the instruction and
establishes the sequence of events to follow.
Register Array
The 8085 has six general purpose registers to store 8-bit data during program execution.
These registers are identified as B, C, D, E, H and L. they can be combined as BC, DE and
HL to perform 16-bit operation.
Accumulator
Accumulator is an 8-bit register that is part of the ALU. This register is used to store 8-bit
data and to perform arithmetic and logic operation. The result of an operation is stored in the
accumulator.
Program Counter
The program counter is a 16-bit register used to point to the memory address of the next
instruction to be executed.
Stack Pointer
It is a 16-bit register which points to the memory location in R/W memory, called the
Stack.
Communication Lines
8085 microprocessor performs data transfer operations using three communication lines
called buses. They are address bus, data bus and control bus.
Address bus it is a group of 16-bit lines generally identified as A0 A15. The

address bus is unidirectional i.e., the bits flow in one direction from
microprocessor to the peripheral devices. It is capable of addressing 2 16 memory
locations.
Data bus it is a group of 8 lines used for data flow and it is bidirectional. The
data ranges from 00 FF.
Control bus it consist of various single lines that carry synchronizing signals.
The microprocessor uses such signals for timing purpose.
Exp. No: 04
ADDITION AND SUBTRACTION OF 8-BIT AND 16-BIT NUMBERS.
(A) 8 BIT DATA ADDITION
AIM:
To add two 8 bit numbers stored at consecutive memory locations.
ALGORITHM:
1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.
3. Get the second number and add it to the accumulator.
4. Store the answer at another memory location.
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

START MVI C, 00 Clear C reg.
Initialize HL reg. to
LXI H, 5100
4500
Transfer first data to
MOV A, M
accumulator
Increment HL reg. to
INX H point next memory
Location.
Add first number to
ADD M
acc. Content.
Jump to location if
JNC L1 result does not yield
carry.
INR C Increment C reg.
L1 INX H point next memory
Location.
Transfer the result from
MOV M, A
acc. to memory.
INX H point next memory
Location.
MOV M, C Move carry to memory
HLT Stop the program
OBSERVATION:
INPUT OUTPUT
MEMORY DATA MEMORY DATA
RESULT:
Thus the 8 bit numbers stored at _____________ and ______________ are added and the
result stored at _____________ & _____________.

(B) 16 BIT DATA ADDITION
AIM:
To add two 16-bit numbers stored at consecutive memory locations.
ALGORITHM:

2. Get the first number from memory and store in Register pair.
3. Get the second number in memory and add it to the Register pair.
4. Store the sum & carry in separate memory locations.
PROGRAM:
START LHLD 5100H Load the augend in DE

pair through HL pair.
XCHG
LHLD 5102H Load the addend in HL

pair.
MVI A, 00H Initialize reg. A for carry
DAD D Add the contents of HL
Pair with that of DE pair.
JNC LOOP If there is no carry, go to

the instruction labeled
LOOP.
INR A Otherwise increment

reg. A
LOOP SHLD 5104H Store the content of HL

Pair in 4054H(LSB of
sum)
STA 5016H Store the carry in 4056H

through Acc.
(MSB of sum).
HLT Stop the program.

OBSERVATION:
INPUT OUTPUT
RESULT:
Thus an Arithmetic Logic Program for 16-bit addition was written and executed in
8085 kit.
(C). 8 BIT DATA SUBTRACTION
AIM:
To subtract two 8 bit numbers stored at consecutive memory locations.
ALGORITHM:

3. Get the second number and subtract from the accumulator.
4. If the result yields a borrow, the content of the acc. is complemented and 01H is
added to it (2s complement). A register is cleared and the content of that reg. is
incremented in case there is a borrow. If there is no borrow the content of the acc.
is directly taken as the result.
5. Store the answer at next memory location.
PROGRAM:
LXI H, 5100 Initialize HL reg. to

4500
MOV A, M Transfer first data to
accumulator
INX H Increment HL reg. to
point next mem.
Location.
SUB M Subtract first number
from acc. Content.
JNC L1 Jump to location if result
does not yield borrow.
CMA Complement the Acc.

content
ADI 01H Add 01H to content of
acc.
L1
point next mem.
Location.
MOV M, A Transfer the result from
acc. to memory.
point next mem.
Location.
MOV M, C Move carry to mem.
OBSERVATION:
INPUT OUTPUT
RESULT:
Thus the 8 bit numbers stored at _____________ and ______________ are
subtracted and the result stored at _____________ & _____________.

(D). 16 BIT DATA SUBTRACTION
AIM:
To subtract two 16-bit numbers stored at consecutive memory locations.
ALGORITHM:

2. Get the subtrahend from memory and transfer it to register pair.
3. Get the minuend from memory and store it in another register pair.
4. Subtract subtrahend from minuend.
5. Store the difference and borrow in different memory locations.
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

START MVI C, 00 Initialize C reg.
LHLD 5100H Load the subtrahend in DE
reg. Pair through HL reg.
XCHG pair.
LHLD 5102H Load the minuend in HL reg.
Pair.
MOV A, L Move the content of reg. L to
Acc.
SUB E Subtract the content of reg. E

from that of acc.
MOV L, A Move the content of Acc. to

reg. L
MOV A, H Move the content of reg. H to
Acc.
SBB D Subtract content of reg. D
with that of Acc.
MOV H, A Transfer content of acc. to

reg. H
SHLD 5104H Store the content of HL pair

in memory location 8504H.
JNC LOOP If there is borrow, go to the

instruction labeled NEXT.
INR C Increment reg. C
LOOP MOV A, C Transfer the content of reg. C

to Acc.
STA 5106H Store the content of acc. to
the memory location 4506H
HLT Stop the program execution.

OBSERVATION:
INPUT OUTPUT
RESULT:
Thus an Arithmetic Logic Program for 16-bit Subtraction was written and
executed in 8085p.
Exp. No: 05
SORTING OF DATA IN ASCENDING & DESCENDING ORDER.
(A).ASCENDING ORDER
AIM:
To sort the given number in the ascending order using 8085 microprocessor.
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is larger than second then
interchange the number.
3. If the first number is smaller, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order

PROGRAM:
MVI B,04 Initialize B reg with number

of comparisons (n-1)
LOOP 3 LXI H,5100 Initialize HL reg. to
4100H
MVI C,04 Initialize C reg with no. of
comparisons(n-1)
LOOP2 MOV A,M Transfer first data to acc.
INX H Increment HL reg. to point
next memory location
CMP M Compare M & A
JC LOOP1 If A is less than M then go to
loop1
MOV D,M Transfer data from M to D
reg
MOV M,A Transfer data from acc to M
DCX H Decrement HL pair
MOV M,D Transfer data from D to M
INX H Increment HL pair
LOOP1 DCR C Decrement C reg
JNZ LOOP2 If C is not zero go to loop2
DCR B Decrement B reg
JNZ LOOP3 If B is not Zero go to loop3

OBSERVATION:
INPUT OUTPUT
RESULT:
Thus the ascending order program is executed and thus the numbers are arranged
in ascending order.
(B). DESCENDING ORDER
AIM:
To sort the given number in the descending order using 8085 microprocessor.
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is smaller than second
then interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order

PROGRAM:

MVI B,04 Initialize B reg with number
of comparisons (n-1)
LOOP 3 LXI H,4100 Initialize HL reg. to

4100H
MVI C,04 Initialize C reg with no. of
comparisons(n-1)
LOOP2 MOV A,M Transfer first data to acc.
INX H Increment HL reg. to point

next memory location
CMP M Compare M & A
JNC LOOP1 If A is greater than M then

go to loop1
MOV D,M Transfer data from M to D
reg
MOV M,A Transfer data from acc to M
DCX H Decrement HL pair
MOV M,D Transfer data from D to M
INX H Increment HL pair
LOOP1 DCR C Decrement C reg
JNZ LOOP2 If C is not zero go to loop2
JNZ LOOP3 If B is not Zero go to loop3

OBSERVATION:
INPUT OUTPUT
RESULT:
Thus the descending order program is executed and thus the numbers are arranged
in descending order.
Exp. No: 06
SUM OF GIVEN SERIES WITH/WITHOUT CARRY
(A) SUM OF GIVEN SERIES OF NUMBER WITH CARRY
AIM:
To write an assembly language program to find the sum of series of data

with carry.
APPARATUS REQUIRED:
Microprocessor 8085 kit,
power supply.
ALGORITHM:
1. Initialize HL (M) pair as memory pointer
2. Get the count at 5100 into B register.
3. Move the 00 data into D register.
4. Decrement value of B register.
5. Increment the HL (M) register pair value.
6. Move data from present memory (M) to Accumulator (A).
8. ADD the memory content and accumulator with carry.
9. ADD the accumulator content and D register content.
11. Jump on NO carry upto all data are added.
12. Store the data in another memory and End the program.
PROGRAM:

MVI C, 00 To make Accumulator
zero
XRA A Decrement B reg
LXI H, 5100 Initialize HL pair
MOV B, M Move Mem into B
Loop 1 INX H Increment HL
MOV A, M Move Mem into Acc
INX H Increment HL
ADD M Add Present memory

data with Acc
JNC Loop 2 If Data with carry
means goto loop 2
INR C Increment C
Loop 2 DCR B Decrement B reg
JNZ Loop1 Jump on no zero to

loop1
STA 5120 Store the data in 5120
MOV A, C Move data from

present memory
HLT Halt the program
OBSERVATION:
INPUT OUTPUT
RESULT:
Thus the program for sum of given series of number was written and executed in
8085 kit.
(B) SUM OF GIVEN SERIES OF NUMBER WITHOUT CARRY
AIM:
To write an assembly language program to find the sum of series of data

without carry.
APPARATUS REQUIRED:
Microprocessor 8085 kit,
power supply.
ALGORITHM:
1. Initialize HL (M) pair as memory pointer
2. Get the count at 5100 into B register.
3. Move the 00 data into D register.
6. Move data from present memory (M) to Accumulator (A).
8. ADD the memory content and accumulator without carry.
9. ADD the accumulator content and D register content.
11. Jump on NO carry upto all data are added.
12. Store the data in another memory and End the program.
PROGRAM:

XRA A Decrement B reg
LXI H, 5100 Initialize HL pair
MOV B, M Move Mem into B
Loop 1 INX H Increment HL
MOV A, M Move Mem into Acc
INX H Increment HL
ADD M Add Present memory

data with Acc
Loop 2 DCR B Decrement B reg
JNZ Loop1 Jump on no zero to

loop1
MOV A, C Move data from

present memory
HLT Halt the program

OBSERVATION:
INPUT OUTPUT
RESULT:
Thus the program for sum of given series of number was written and executed in
8085 kit.
Exp. No: 07
GREATEST IN A GIVEN SERIES & MULTI-BYTE ADDITION
IN BCD MODE.
AIM:
To add two 8 bit BCD numbers stored at consecutive memory locations.
ALGORITHM:

3. Get the second number and add it to the accumulator
4. Adjust the accumulator value to the proper BCD value using DAA instruction.
5. Store the answer at another memory location.
PROGRAM:

LXI H, 5100 Initialize HL reg. to
5100
MOV A, M Transfer first data to
accumulator
point next memory
Location.
ADD M Add first number to
acc. Content.
DAA Decimal adjust
accumulator
JNC Loop1 Jump to location if
result does not yield
carry.
Loop1 INX H Increment HL reg. to
point next memory
Location.
MOV M, A Transfer the result from
acc. to memory.
point next memory
Location.
MOV M, C Move carry to memory

OBSERVATION:
INPUT OUTPUT
RESULT:
Thus the 8 bit BCD numbers stored at _______&_______are added and the result
stored at ______ & _________ .
INTERFACING PROGRAM WITH 7 SEGMENT DISPLAYS
Exp. No: 08
AND SWITCHES LEDs
AIM:
To displays the character in 7 segment display.
APPARATUS REQUIRED:
1. 8085 microprocessor kit.
2. 7 Segment display.
3. Bus chord.
THEORY:
The seven segment displays as the name implies consists of 7 LEDs arranged in a pattern
of 8 to display the construction of a typical 7 segment display is shown in figure. Each
straighten strip in and LED is called as a segment and the segments are identified as a log.
The corresponding data bus and segment enabled as follows:
DATA BUS D7 D6 D5 D4 D3 D2 D1 D0
SEGMENTS h g f e d c b a
Example:
To Display AERO
For A:
h g f e d c b a
1 0 0 0 1 0 0 0
For E:
h g f e d c b a
1 0 0 0 0 1 1 0
For R:
h g f e d c b a
1 0 0 0 1 1 1 1
For 0:
h g f e d c b a
1 1 0 0 0 0 0 0
ALGORITHM:
1. Load the HL pair with data.
2. Move memory content to accumulator.
3. Display output through input/output port.
4. Increment the content of HL pair to get another data.

PROGRAM:

START LXI H,8200 Initialize the HL pair reg.
MOV A,M Move memory to Acc
OUT C0 Output to 1st display
Increment the memory by
INX H
one
OUT C2 Output to 2nd display
INX H
one
OUT C4 Output to 3rd display
INX H
one
OUT C6 Output to 4th display
INX H
one
OUT C8 Output to 5th display
INX H
one
OUT CA Output to 6th display
INX H
one
OUT CC Output to 7th display
INX H
one
OUT CE Output to 8th display
OBSERVATION:
INPUT:
ADDRESS DATA COMMANDS
OUTPUT:
RESULT:
Thus the design and implementation of interfacing program with 7 segment

displays has executed successfully.
Exp. No: 09
16 CHANNEL ANALOGY TO DIGITAL CONVERTER &
GENERATION OF RAMP, SQUARE, TRIANGULAR WAVE BY
DIGITAL TO ANALOG CONVERTER
(A) SQUARE WAVE GENERATOR

AIM:
To write a program and to generate square generator using DAC.
APPARATUS REQUIRED:
8085 microprocessor kit

(0-5V) power supply
ALGORITHM:
1. Initialize A as 00 and take data pointer to port C8
2. Call delay
3. Move FF to A and take port C8
4 . Call delay
5 . Go to step 1
Delay Subroutine
1. Counter 1 = 05
2 . Counter 2 = FF
3 . Decrement counter 2
4 . Check if c= 0, if no jump to step 3
5 . Decrement counter 1
6 . Check if B = 0, if no jump to step 2
7 . Return to main program
PROGRAM:

Start MVI A,00 Intialise A with 00
OUT C8 Load the control words
CALL Delay Call delay sutroutine
MVI A,FF Intialise A with FF
OUT C8 A -> C8
CALL Delay Call delay subroutine
JMP Start Jump to start
Delay MVI B,05 B -> 05
Loop 1 MVI C,FF [C] => FF
Loop 2 DCR C Decrement C register
JNZ Loop 2 Jump on no zero
DCR B Decrement B register
JNZ Loop 1 Jump on n zero
RESULT:
Thus the square wave was generated using 8085 microprocessor kit.
(B) TRIANGULAR WAVE GENERATOR
AIM:
To write an assembly language program for generating triangular wave using

DAC.
APPARATUS REQUIRED:
8085 micro processor kit

(0-5V) DC battery
ALGORITHM:
1 . Move content of C to A where L is initialize to 00

2 . Output content of C8
3 . Increment L till zf = 0
4 . Initialize L register with FF
5 . Move content of L to accumulator and output to port
6 . Decrement L if not equal to zero jump else go to next step
7 . Jump on next step
PROGRAM:
Start MVI L,00 Initialize L as 00
Loop 1 MOV A,L [L] -> [A]
OUT C8 Load the control words
INR L Increment register L
JNZ Loop 1 Jump on no zero to

loop1
MVI L,FF L = FF
Loop 2 MOV A,L L -> A
OUT C8 [C8] -> [A]
DCR L Decrement L by one
JNZ Loop 2 Jump on no zero to

430B
JMP Start Repeat process
RESULT:
Thus the Triangular wave was generated using 8085 microprocessor kit.
(C) SAWTOOTH WAVE GENERATOR
AIM:
To write an assembly language program for generating Saw tooth waveform by
using microprocessor 8085.
APPARATUS REQUIRED:
8085 microprocessor kit

(0-5V) power supply
ALGORITHM:
1 . Initialize accumulator with 00
2 . Output current address specified
3 . Increment accumulator by one
4 . Jump to step one
PROGRAM:

Start MVI A,00 Initialize A as 00
Loop 1 OUT C8 A = [C8]
INR A Increment A by one
JMP Loop 1 Jump to loop one
RESULT:
Thus the Saw tooth wave was generated using 8085 microprocessor kit.
III. AVIONICS DATA BUSES
Exp. No: 10
STUDY OF DIFFERENT AVIONICS DATA BUSES
AIM:
To study about different avionics data buses like MIL-STD-1553B, ARINC 429
and ARINC 629 architecture and word formats.
THEORY:
There are two types of data-bus systemselectrical bus systems, in which the data
are transmitted as electrical pulses by wires, and optical data-bus systems, in which the
data are transmitted as light pulses by optical fibers. More famous electrical data buses are
the MIL standard 1553B, which are widely used in most military aircraft, and the ARINC
429 and the ARNIC 629, which are used in civil aircraft.
MIL-STD-1553B
MIL-STD-1553B, "Aircraft Internal Time-Division Command/Response
Multiplex Data Bus," has been in use since 1973 and is widely applied. MIL-STD-1553
is referred to as "1553" with the appropriate revision letter (A or B) as a suffix. The basic
difference between the 1553A and the 1553B is that in the 1553B, the options are defined
rather than being left for the user to define as required. It was found that when the
standard did not define an item, there was no coordination in its use.
Hardware and software had to be redesigned for each new application. The
primary goal of the 1553B was to provide flexibility without creating new designs for
each new user. This was accomplished by specifying the electrical interfaces explicitly so
that compatibility between designs by different manufacturers could be electrically
interchangeable.
BUS
The bus is made up of twisted-shielded pairs of wires to maintain message
integrity. MIL-STD-1553 specifies that all devices in the system will connect to a
redundant pair of buses. This provides a second path for bus traffic should one of the
buses be damaged. Signals are only allowed to appear on one of the two buses at a time.
If a message cannot be completed on one bus, the bus controller may switch to the other
bus. In some applications more than one 1553 bus may be implemented on a given
vehicle. Some terminals on the bus may actually connect to both buses.
BUS COMPONENTS
There are only three functional modes of terminals allowed on the data bus:
the bus controller, the bus monitor, and the remote terminal. Devices may be capable of
more than one function. Figure 1 illustrates a typical bus configuration.
Bus Controller - The bus controller (BC) is the terminal that initiates information
transfers on the data bus. It sends commands to the remote terminals which reply with a
response. The bus will support multiple controllers, but only one may be active at a time.
Other requirements, according to 1553, are:
(1) it is "the key part of the data bus system," and

(2) "the sole control of information transmission on the bus shall reside with the
bus controller."
Bus Monitor - 1553 defines the bus monitor as "the terminal assigned the task of
receiving bus traffic and extracting selected information to be used at a later time." Bus
monitors are frequently used for instrumentation.
Remote Terminal - Any terminal not operating in either the bus controller or bus
monitor mode is operating in the remote terminal (RT) mode. Remote terminals are the
largest group of bus components.
ARINC 429
ARINC 429 is a data format for aircraft avionics. It provides the basic description
of the functions and the supporting physical and electrical interfaces for the digital
information system on an airplane. ARINC 429 is the predominant avionics data bus for
most higher-end aircraft today.
ARINC 429 is the technical standard for the predominant avionics data bus used on
most higher-end commercial and transport aircraft. It defines the physical and electrical
interfaces of a two-wire data bus and a data protocol to support an aircraft's avionics local
area network.
TECHNICAL DESCRIPTION
ARINC 429 is a two-wire data bus that is application-specific for commercial and
transport aircraft. The connection wires are twisted pairs. Words are 32 bits in length and
most messages consist of a single data word. The specification defines the electrical and
data characteristics and protocols.
Messages are transmitted at either 12.5 or 100 kbit/s to other system elements that
are monitoring the bus messages. The transmitter is always transmitting either 32-bit
data words or the NULL state. No more than 20 receivers can be connected to a single
bus (wire pair) and no less than one receiver, though there will normally be more.
ARINC 629
ARINC 629 is a multi-transmitter protocol where many units share the same bus.
It was a further development of ARINC 429 especially designed for the Boeing 777. It is
a new digital data bus format that offers more flexibility and greater speed than the 429
system. ARINC 629 has two major improvement over the 429 system.
First, there is a substantial weight saving. Second, the 629 bus operates at speeds
up to 2 Mbits/s; the 429 is capable of only 100 Kbits/s.
The ARINC 629 bus is a true data bus in that the bus operates as a multiple-
source, multiple sink system as shown in below figure. That is, each terminal can
transmit data to, and receive data from, every other terminal on the data bus. This allows
much more freedom in the exchange of data between units in the avionics system. The
true data bus topology is much more flexible in that additional units can be fairly readily
accepted physically on the data bus.
The protocol utilized by ARINC 629 is a time based, collision-avoidance concept
in which each terminal is allocated a particular time slot to access the bus and transmit
data on to the bus. Each terminal will autonomously decide when the appropriate time slot
is available through the use of several control timers embedded in the bus interfaces and
transmit the necessary data. Below figure shows the typical ARINC 629 20 bit data word
format which is very similar to MILSTD- 1553B.
COMPARISON OF DATA BUSES:
SL.NO DESCRIPTIONS MIL-STD-1553 ARINC 429 ARINC 629
1 Bus Architecture Time Division Simplex point- Time Division

Multiplex to-point Multiplex
2 Encoding Bipolar Manchester II Bipolar return to Bipolar doublets

zero Manchester
3 Transmission mode & Voltage, Direct or Voltage direct Current Coupling

coupling Transformer connection
4 Media Shielded Twisted wire Pair
5 Data Bit Rate 1 MBPS 12-14 kBPS, 2 MBPS
100 KBPS
6 Effective Data Rate 800 KBPS 53 KBPS 1.6 MBPS
7 Terminals BC-1,RT- 32, BM-1 1 TX, 20 RX Multi TX and RX
RESULT:
Thus the different avionics data buses like MIL-STD-1553, ARINC 429 and
ARINC 629 was studied successfully.
Exp. No: 11
STUDY OF MIL-STD 1553 DATA BUSES CONFIGURATION
WITH MESSAGE TRANSFER.
AIM:
To study about MIL-STD-1553 data bus Buses Configuration with message

transfer.
THEORY:
A data bus is used to provide a medium for the exchange of data and
information between various systems.
MIL-STD-1553B
MIL-STD-1553 is a military standard that defines the electrical and protocol
characteristics for a data bus. MIL-STD-1553B defines the term Time Division
Multiplexing (TDM) as the transmission of information from several signal
sources through one communications system with different signal samples
staggered in time to form a composite pulse train.
Hardware Elements
MIL-STD-1553B has four hardware elements. These are:
1. The transmission media.

2. Remote terminals.
3. Bus controllers.
4. Bus monitors.
Transmission Media
The transmission media, or data bus, is defined as a twisted shielded pair

transmission line consisting of the main bus and a number of stubs. There is one
stub for each terminal connected to the bus.
Remote Terminals
Remote terminals are defined within the standard as All terminals not
operating as the bus controller or as a bus monitor. Therefore if it is not a
controller, monitor, or the main bus or stub, it must be a remote terminal. The
remote terminal comprises the electronics necessary to transfer data between the data
bus and the subsystem.
A remote terminal typically consists of a transceiver, an encoder/decoder, a

protocol controller, a buffer or memory, and a subsystem interface.
A remote terminal must follow the protocol defined by the standard. It can
only respond to commands received from the bus controller (i.e., it speaks only
when spoken to). When it receives a valid command, it must respond within a very
small, closely defined amount of time. If a message doesnt meet the validity
requirements defined, then the remote terminal must invalidate the message and
discard the data (not allow it to be used by the subsystem).
Fig: MIL-STD-1553B Hardware components

Bus Controller
The bus controller is responsible for directing the flow of data on the data
bus. While several terminals may be capable of performing as the bus controller,
only one bus controller may be active at a time. The bus controller is the only one
allowed to issue commands onto the data bus.
The commands may be for the transfer of data or the control and
management of the bus (referred to as mode commands).
There are three types of bus controller architectures:
1. A word controller.
2. A message controller.
3. A frame controller.
Word Controller
A word controller, the terminal electronics transfers one word at a time to the
subsystem. Message buffering and validation must be performed by the subsystem.
Message Controller
These controllers output a single message at a time, interfacing with the

computer only at the end of the message or perhaps when an error occurs. Some
message controllers are capable of performing minor error processing.
Frame Controller
A frame controller is capable of processing multiple messages in a sequence

defined by the host computer. The frame controller is typically capable of
performing some error processing as defined by the message control word.
Bus Monitor
A bus monitor is a terminal that listens (monitors) to the exchange of

information on the data bus.
A monitor may collect all the data from the bus or may collect selected data.
Bus monitors fall into two categories:
1. A recorder for testing.
2. A terminal functioning as a back-up bus controller.
In collecting data, a monitor must perform the same message validation

functions as the remote terminal and if an error is detected, inform the subsystem of
the error.
As recorders for testing, the subsystem is typically a recording device such as

a magnetic tape or disk, or a telemetry transmitter.
Word Types
Three distinct word types are defined by the standard. These are:
1. Command words.
2. Data words.
3. Status words.
Each word type has a unique format, yet all three maintain a common
structure. Each word is twenty bits in length.
The first three bits are used as a synchronization field, thereby allowing the
decode clock to re-sync at the beginning of each new word.
The next sixteen bits are the information field and are different between the
three word types.
The last bit is the parity bit. Parity is based on odd parity for the single word.
Sync Fields
The first three bit times of all word types is called the sync field.
Two distinct sync patterns are used:
1. The command/status sync, and

2. The data sync.
The command/status sync has a positive voltage level for the first one and a
half bit times and then transitions to a negative voltage level for the second one and
a half bit times.
The data sync is the opposite, a negative voltage level for the first one and a
half bit times, and then a positive voltage level for the second one and a half bit
times.
Fig: Mil-Std-1553B Word Format
Command Words
The Command Word (CW) specifies the function that a remote terminal is to
perform. Only the active bus controller transmits this word.
The word begins with command sync in the first three bit times.
The next five bit positions are defined as Terminal Address (TA) field (bit
times 4-8) states to which unique remote terminal the command is intended. (no
two terminals may have the same address).
The next bit (bit time 9) makes up the Transmit/Receive (T/R) bit. This
defines the direction of information flow and is always from the point of view of the
remote terminal. A transmit command (logic 1) indicates that the remote terminal is
to transmit data, while a receive command (logic 0) indicates that the remote
terminal is going to receive data. The only exceptions to this rule are associated with
mode commands.
The next five bits (bit times 10-14) make up the Sub address (SA)/Mode
Command bits.
The next five bit positions (bit times 15-19) define the Word Count (WC) or
Mode Code to be performed.
The last bit (bit time 20) is the word parity bit. Only odd parity is used.
Data Word
The Data Word (DW) contains the actual information that is being transferred
within a message.
The first three-bit time contains data sync. This sync pattern is the opposite of
that used for command and status words and therefore is unique to the word type.
Data words can be transmitted by either a remote terminal (transit command) or a
bus controller (receive command). Transmit and Receive, by convention, references
the remote terminal.
The next sixteen bits of information are left to the designer to define. The only
standard requirement is that the most significant bit (MSB) of the data be
transmitted first.
Status Word
A remote terminal in response to a valid message transmits only the status

word (SW). The status word is used to convey to the bus controller whether a
message was properly received or to convey the state of the remote terminal (i.e.,
service request, busy, etc.).
The (bit times 4-8) bits are the information of Terminal Address (TA). These
five bits should match the corresponding field within the command word that the
terminal received.
The next bit (bit time 9) is the Message Error (ME) bit. This bit is set by the
remote terminal upon detection of an error in the message or upon detection of an
invalid message (i.e. Illegal Command) to the terminal.
The Instrumentation bit (bit time 10) is provided to differentiate between a

command word and a status word (remember they both have the same sync
pattern).
The Service Request bit (bit time 11) is provided so that the remote terminal
can inform the bus controller that it needs to be serviced. This bit is set to a logic 1
by the subsystem to indicate that servicing is needed.
Bit times 12-14 are reserved for future growth of the standard and must be
set to logic 0. The bus controller should declare a message in error if the remote
terminal responds with any of these bits set in its status word.
The Broadcast Command Received bit (bit time 15) indicates that the remote
terminal received a valid broadcast command. On receiving a valid broadcast
command, the remote terminal sets this bit to logic 1 and suppresses the
transmission of its status words.
The Busy bit (bit time 16) is provided as a feedback to the bus controller as to
when the remote terminal is unable to move data between the remote terminal
electronics and the subsystem in compliance to a command from the bus controller.
The Subsystem Flag bit (bit time 17) is used to provide health data
regarding the subsystems to which the remote terminal is connected.
The Dynamic Bus Control Acceptance bit (bit time 18) informs the bus
controller that the remote terminal has received the Dynamic Bus Control Mode
Code and has accepted control of the bus.
The Terminal Flag bit (bit time 19) informs the bus controller of a fault or
failure within the remote terminal circuitry (only the remote terminal). Logic 1
shall indicate a fault condition.
INFORMATION TRANSFERS
Three basic types of information transfers are defined by 1553:

1. Bus Controller to Remote Terminal transfers
2. Remote Terminal to Bus Controller transfers
3. Remote Terminal to Remote Terminal transfers
These transfers are related to the data flow and are referred to as messages.
The basic formats of these messages are shown in Figure
RESULT:
Thus the different Study about MIL-STD-1553 data bus Buses Configuration with
message transfer Studied successfully.
Exp. No: 12
STUDY OF MIL-STD 1553 DATA BUSES CONFIGURATION
WITH MESSAGE TRANSFER
AIM:
To study about MIL-STD-1553 data bus architecture and word formats with
message transfer.
THEORY:
MIL-STD-1553B defines the term Time Division Multiplexing (TDM) as the

transmission of information from several signal sources through one communications
system with different signal samples staggered in time to form a composite pulse train.
For our example in Figure 1b, this means that data can be transferred between multiple
avionics units over a single transmission media, with the communications between the
different avionics boxes taking place at different moments in time, hence time division.
MIL-STD-1553 defines certain aspects regarding the design of the data bus system
and the black boxes to which the data bus is connected. The standard defines four
hardware elements. These are:
1. The transmission media.
2. Remote terminals.
3. Bus controllers.
4. Bus monitors.
1. Transmission Media
The transmission media, or data bus, is defined as a twisted shielded pair
transmission line consisting of the main bus and a number of stubs. There is one stub for
each terminal connected to the bus. The main data bus is terminated at each end with a
resistance equal to the cable's characteristic impedance (plus or minus two percent). This
termination makes the data bus behave electrically like an infinite transmission line.
2. Remote Terminals:
Remote terminals are defined within the standard as All terminals not operating
as the bus controller or as a bus monitor. Therefore if it is not a controller, monitor, or
the main bus or stub, it must be a remote terminal.
The remote terminal comprises the electronics necessary to transfer data between
the data bus and the subsystem. So what is a subsystem? For 1553 applications, the
subsystem is the sender or user of the data being transferred.
A remote terminal typically consists of a transceiver, an encoder/decoder, a
protocol controller, a buffer or memory, and a subsystem interface. In a modern black
box containing a computer or processor, the subsystem interface may consist of the
buffers and logic necessary to interface to the computer's address, data, and control buses.
Bus Controller:
The bus controller is responsible for directing the flow of data on the data bus.
While several terminals may be capable of performing as the bus controller, only one bus
controller may be active at a time. The bus controller is the only one allowed to issue
commands onto the data bus. The commands may be for the transfer of data or the
control and management of the bus (referred to as mode commands).
Typically, the bus controller is a function that is contained within some other
computer, such as a mission computer, a display processor, or a fire control computer.
The complexity of the electronics associated with the bus controller is a function of the
subsystem interface (the interface to the computer), the amount of error management and
processing to be performed, and the architecture of the bus controller.
There are three types of bus controller architectures:

1. A word controller.
2. A message controller.
3. A frame controller.
Word Types:
Three distinct word types are defined by the standard. These are:
1. Command words.
2. Data words.
3. Status words.
The multiplex data bus system in its most elemental configuration shall be as
shown in above figure. The multiplex data bus system shall function a synchronously in a
command / response mode, and transmission shall occur in a half duplex manner. Sole
control of information transmission on the bus shall reside with the bus controller, which
shall initiate all transmissions. The information flow on this data bus shall be comprised
of messages which are, in turn, formed by three types of words (command, data and
status).
(a) COMMAND WORD:

A command word shall be comprised of a sync wave form, remote terminal
address field, transmit / receive (T/R) bit, sub address /mode field,word count / mo de
code field, and a parity (P) bit as shown in the figure.
i) Sync:
The command sync wave form shall be an invalid Manchester wave form as
shown in below figure. The width shall be three bit times, with the sync wave form being
positive for the first one and one half bit times, and then negative for the following one
and one half bit times. If the next bit following the sync wave form is a logic zero, then
the last half of the sync wave form will have an apparent width of two clock periods due
to the Manchester encoding.
ii) Remote terminal address:
The next five bits following the sync shall be the RT address. Each RT shall be
assigned a unique address. Decimal address 31 (11111) shall not be assigned as a unique
address. In addition to its unique address, a RT shall be assigned decimal address 31
(11111) as the common address, if the broad cast option is used.
iii) Transmit / receive:
The next bit following the remote terminal address shall be the T/R bit, which
shall indicate the action required of the RT. A logic zero shall indicate the RT is to
receive, and a logic one shall indicate the RT is to transmit.
iv) Sub address / mode:
The five bits following the R/T bit shall be utilized to indicate an RT sub address
or use of mode control, as is dictated by the individual terminal requirements. The sub
address / mode values of 00000 and 11111 are reserved for special purposes, and shall
not be utilized for any other function.
v) Data word count / mode code:
The next five bits following the sub addresses / mode field shall be the quantity of
data words to be either sent out or received by the RT. A maximum of 32 data words may
be transmitted or received in any one message block. All 1s shall indicate a decimal
count of 31, and all 0s shall indicate a decimal count of 32.
vi) Parity:
The last bit in the word shall be used for parity over the preceding 16 bits. Odd
parity shall be utilized.
(b) DATA WORD
A data word shall be comprised of a sync wave form, data bits, and a parity bit.
i) Sync:
The data sync wave form shall be an invalid Manchester wave form as shown in
below figure. The width shall be three bit times, with the wave form being negative for
the first one and one half bit times, and then positive for the following one and one half
bit times. Note that if the bits preceding and following the sync are logic ones, then the
apparent width of the sync wavw form will be increased to four bit times.
ii) Data:
The sixteen bit following the sine shall be utilized for data transmission.
iii) Parity:
The last bit in the word shall be used for parity over the proceding 16 bits. Odd
parity shall be utilized.
(c) STATUS WORD
A status word shall be comprised of a sync wave form, RT address, message error
bit, instrumentation bit, service request bit, three reserved bits, broadcast command
received bit, busy bit, sub system flag bit, dynamic bus control acceptance bit, terminal
flag bit and a parity bit.
i) RT address:
The next five bits following the sync shall contain the address of the RT which is
transmitting the status word. (also explained above)
ii) Message error bit:
The status word bit at bit time nine shall be utilized to indicate that one or more of
the data words associated with the proceeding receive command word from the bus
controller has failed to pass the RTs validity tests. A logic one shall indicate the presence
of a message error, and a logic zero shall show its absence. All RTs shall implement the
message error bit.
iii) Instrumentation bit:
The status word at bit time ten shall be reserved for the instrumentation bit and
shall always be a logic zero. This bit is intended to be used in conjunction with a logic
one in bit time ten of the command word to distinguish between a command word and a
status word. The use of the instrumentation bit is optional.
iv) Service request bit:
The status word bit at bit time eleven shall be reserved for the service request bit.
The use of this bit is optional. This bit when used, shall indicate the need for the bus
controller to take specific pre-defined actions relative to either the RT or associated
subsystem. Multiple subsystems, interfaced to a single RT, which individually require a
service request signal shall logically or their individual signals into the single status word
bit.
v) Reserved status bits:
The status word bits at bit times twelve through fourteen are reserved for future
use and shall not be used. These bits shall be set to a logic zero.
vi) Broad cost command received bit:
The status word at bit time fifteen shall be set to a logic one to indicate that the
preceding valid command word was a broad cast command and a logic zero shall show it
was not a broad cast command. If the broad cast command option is not used, this bit
shall be set to a logic zero.
vii) Busy bit:
The status word bit at time sixteen shall be reserved for the busy bit. The use of
this bit is optional. This bit, when used, shall indicate that the RT or subsystem is unable
to move data to or from the subsystem in compliance with the bus controllers command.
A logic one shall indicate the presence of a busy condition, and logic zeros its absence. In
the event the busy bit is set in response to a transmit command, then the RT shall transmit
its status word only. If this function is not implemented, the bit shall be set to logic zero.
viii) Sub system flag bit:
The status word bit at bit time seventeen shall be reserved for the subsystem flag
bit. The use of this bit is optional. This bit when used, shall flag a subsystem fault
condition, and alert the bus controller to potentially invalid data.
Multiple subsystems, interfaced to a single RT, which individually require a
subsystem flag bit signal shall logically or their individual signals into the single status
word bit. In the event this logical OR is performed, then the designer must make
provisions in a separate data word to identify the specific reporting sub system. A logic
one shall indicate the presence of the flag, and a logic zero its absence. If not used, this
bit shall be set to logic zero.
ix) Dynamic bus control acceptance bit:
The status word bit at bit time eighteen shall be reserved for the acceptance of
dynamic bus control. This bit shall be used if the RT implements the optional dynamic
bus control function.
This bit, when used, shall indicate acceptance or rejection of a dynamic bus
control offer. A logic one shall indicate acceptance of control, and a logic zero shall
indicate rejection of control. If then function is not used, this bit shall be set to logic zero.
x) Terminal flag bit:
The status word bit at bit time nineteen shall be reserved for the terminal flag
function. The use of this bus is optional. This bit, when used, shall flag a RT fault
condition. A logic one shall indicate the presence of the flag, and a logic zer o, its
absence. If not used, this bit shall be set to logic zero.
xi) Parity:
The least significant bit in the status word shall be utilized for parity.
RESULT:
Thus the different Study MIL-STD 1553 Remote Terminal Configuration. is

studied successfully.

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SNS COLLEGE OF TECHNOLOGY

(An Autonomous Institution)

DEPARTMENT OF AERONAUTICAL ENGINEERING

AE404 AVIONICS LAB RECORD

Sem / Year : ........,

ACADEMIC YEAR: 2017-2018

Certified that this is the bonafide Record of work done by

_______________________________________________ student of the AE 404

AVIONICS LABORATORY during the year 2017 to 2018.

SIGNATURE OF LAB-IN-CHARGE HEAD OF THE DEPARTMENT

Submitted for the End Semester Practical Examination held on

INTERNAL EXAMINER EXTERNAL EXAMINER

SL.NO DATE DESCRIPTIONS MARKS SIGNATURE

(A) Addition of Binary Numbers

SL.NO COMPONENT SPECIFICATION QUANTITY

1 IC trainer kit --- 1

2 AND GATE IC 7408 1

3 X-OR GATE IC 7486 1

4 NOT GATE IC 7404 1

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

SL.NO COMPONENT SPECIFICATION QUANTITY

1 IC trainer kit --- 1

2 AND GATE IC 7408 1

3 X-OR GATE IC 7486 1

4 NOT GATE IC 7404 1

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Design and Implementation Of Multiplexer And Demultiplexer

SL.NO COMPONENT SPECIFICATION QUANTITY

1 IC trainer kit --- 1

2 3 INPUT AND GATE IC 7411 2

3 NOT GATE IC 7404 1

A multiplexer (or mux) is a device that selects one of several analog or

An electronic multiplexer can be considered as a multiple-input, single-output

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Design and Implementation Of Encoder And Decoder

SL.NO COMPONENT SPECIFICATION QUANTITY

1 IC trainer kit --- 1

2 3 INPUT NAND GATE IC 7410 2

3 NOT GATE IC 7404 1

A encoder is a combinational logic circuit that converts a binary integer value to

A binary decoder is a combinational logic circuit that converts a binary integer

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

INTEL 8085 is one of the most popular 8-bit microprocessor capable of

ALU (Arithmetic Logic Unit):

Auxillary Carry Flag

Timing and Control Unit

Instruction Register and Decoder

Address bus it is a group of 16-bit lines generally identified as A0 A15. The

(A) 8 BIT DATA ADDITION

To add two 8 bit numbers stored at consecutive memory locations.

1. Initialize memory pointer to data location.

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

MEMORY DATA MEMORY DATA

result stored at _____________ & _____________.

To add two 16-bit numbers stored at consecutive memory locations.

result stored at _ & _.

Thus the 8 bit numbers stored at _ and __ are

subtracted and the result stored at _ & _.