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TPIC74101-Q1
SLIS140A OCTOBER 2011 REVISED DECEMBER 2014
Vlogic RESET
470 nF
Optional 5 kW
Connection AOUT
5Vg_ENABLE
REST SCR1
2.2 nF150 nF
CLP
SCR0
Rmod
12 kW PGND
GND
S0183-01
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC74101-Q1
SLIS140A OCTOBER 2011 REVISED DECEMBER 2014 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.2 Functional Block Diagram ....................................... 10
2 Applications ........................................................... 1 7.3 Feature Description................................................. 11
3 Description ............................................................. 1 7.4 Device Functional Modes........................................ 14
4 Revision History..................................................... 2 8 Application and Implementation ........................ 17
8.1 Application Information............................................ 17
5 Pin Configuration and Functions ......................... 3
8.2 Typical Application ................................................. 17
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 9 Power Supply Recommendations...................... 20
6.2 ESD Ratings ............................................................ 4 10 Layout................................................................... 20
6.3 Recommended Operating Conditions....................... 4 10.1 Layout Guidelines ................................................. 20
6.4 Thermal Information .................................................. 5 10.2 Layout Example .................................................... 23
6.5 Dissipation Rating ..................................................... 5 11 Device and Documentation Support ................. 25
6.6 Electrical Characteristics........................................... 5 11.1 Trademarks ........................................................... 25
6.7 Typical Characteristics .............................................. 7 11.2 Electrostatic Discharge Caution ............................ 25
7 Detailed Description ............................................ 10 11.3 Glossary ................................................................ 25
7.1 Overview ................................................................. 10 12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Original (October 2011) to Revision A Page
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
20-PINS
PWP HTSSOP PACKAGE
(TOP VIEW)
SCR1 1 20 SCR0
Cboot2 2 19 5Vg_ENABLE
Cboot1 3 18 ENABLE
Vdriver 4 17 Vlogic
L1 5 16 GND
PGND 6 15 Rmod
L2 7 14 REST
VOUT 8 13 AOUT
5Vg 9 12 RESET
AIN 10 11 CLP
P0021-02
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
SCR1 1 I Programmable slew-rate control
Cboot2 2 I External bootstrap capacitor
Cboot1 3 I External bootstrap capacitor
Vdriver 4 I Input voltage source
L1 5 I Inductor input (an external Schottky diode (1) to GND must be connected to L1)
PGND 6 I Power ground
L2 7 I Inductor output
VOUT 8 O 5-V regulated output
5Vg 9 O Switched 5-V supply
AIN 10 I Programmable alarm setting
CLP 11 I/O Low-power operation mode (digital input)
RESET 12 O Reset function (open drain)
AOUT 13 O Alarm output (open drain)
REST 14 O Programmable reset timer delay
Rmod 15 I Main switching frequency modulation setting to minimize EMI
GND 16 I Ground
Vlogic 17 O Supply decoupling output (may be used as a 5-V supply for logic-level inputs)
ENABLE 18 I Switch-mode regulator enable/disable
5Vg_ENABLE 19 I Switched 5-V voltage regulator output enable/disable
SCR0 20 I Programmable slew-rate control
Exposed thermal pad of the package should be connected to GND or left floating.
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
(2)
Unregulated input voltage, V(driver) 0.5 40 V
(2)
Unregulated inputs, V(AIN), V(ENABLE) 0.5 40 V
Bootstrap V(Cboot1) 52 V
voltages
V(Cboot2) 14 V
Switch mode V(L1) 1 40 V
voltages
V(L2) 1 7 V
(2)
Logic input voltages, V(Rmod),V(SCR0),V(SCR1),V(CLP), and V(5Vg_ENABLE) 0.5 7 V
(2)
Low output voltages, V(RESET),V(AOUT),V(logic), and V(REST) 0.5 7 V
Continuous power dissipation, PD See Dissipation Rating
Operating virtual junction temperature range, TJ 40 150 C
Operating ambient temperature range, TA 40 125 C
Lead temperature (soldering, 10 s), T(LEAD) 260 C
Storage temperature, Tstg 65 125 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The thermal data is based on using 2-oz copper trace with at least four square inches of copper footprint for heat dissipation. The
copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.
(3) The thermal data is based on using 1-oz copper trace with at least four square inches of copper footprint for heat dissipation. The
copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.
6 1.0
V(driver) = 11 V
V(driver) = 11 V 0.9
5
0.8
II Input Current mA
0.7
II Input Current mA
4
Maximum 0.6
Maximum
3 0.5
TA = 125
TA = 125
TA = 25 0.4
2 TA = 25
0.3
0.2
1
0.1
0 0.0
0 1 2 3 4 5 6 7 8 9 10 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IO Output Current mA IO Output Current mA
G001 G002
1000
900 TA = 25
800
IO Output Current mA
V(L1)
700
600 TA = 125
500
200
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VI Input Voltage V
G003
G005
(1) Typical representation of input voltage vs output load current at
TA = 25C and 125C, after the correct power-up sequence is \
invoked. SCR0 = 0, SCR1 = 0, Input-Current Slew Rate = 2.8 A/s,
(2) The dip in the output current at 5.8 V is caused by the IL = 500 mA, V(driver) = 15 V
buck/boost transition of the IC.
(3) The output current is clipped to 1 A by the measurement setup.
Figure 3. Typical Input Voltage (V(driver)) vs Figure 4. Input Current With Slope Control
Maximum Output Load Current (IO)
G010 G011
SCR1 = 0, SCR0 = 1, Input-Current Slew Rate = 6.25 A/s, SCR1 = 1, SCR0 = 0, Input-Current Slew Rate = 9.4 A/s,
IL = 500 mA, V(driver) = 15 V IL = 500 mA, V(driver) = 15 V
Figure 5. Input Current With Slope Control Figure 6. Input Current With Slope Control
G008 G009
G012 G013
Figure 9. Nominal Switching Frequency of Q1 Switch Figure 10. Minimum Switching Frequency (333 kHz)
(446 kHz) with Modulation Function Disabled With Modulation Enabled
G006 G007
Rmod = 12 k, IL = 200 mA
Figure 11. Maximum Switching Frequency (555 kHz) Figure 12. Modulation Frequency (Full Span) of 28 kHz
with Modulation Enabled
VO
11 V, IL = 700 mA
V(driver)
5V, IL = 700 mA
2V, IL = 225 mA
G014 G015
IL = 400 mA
Figure 13. Input Voltage Excursions (Similar to Low-Crank Figure 14. Switch-Mode Regulator Transition From Buck
Conditions) Mode to Boost Mode
Modulation Off
LO G 10 dB /div Modulation = 28 kHz
G017
G016
IL = 400 mA .
These values represent conducted EMI results of a test board for
display purposes only. Actual results may vary greatly depending
on board layout and external components and must be verified in
actual application
Figure 15. Switch-Mode Regulator Transition From Boost Figure 16. Conducted Emissions on Test Board Showing
Mode to Buck Mode Effects of Switching-Frequency Modulation
LO G 10 dB /div
Slew Rate = 11
Slew Rate = 00
G018
These values represent conducted EMI results of a test board for display purposes only. Actual results may vary greatly depending on
board layout and external components and must be verified in actual application.
Figure 17. Conducted Emissions on Test Board Showing Effects of Minimum and Maximum Slew Rate Settings
7 Detailed Description
7.1 Overview
The TPIC74101-Q1 is a buck/boost switch-mode regulator that operates in a power-supply concept to ensure a
stable output voltage with input voltage excursions and specified load range.
The device provides an alarm indicator and reset output to interface with systems that require supervisory
function.
The switching regulator offers a clock modulator and a current-mode slew-rate control for the internal switching
transistor (Q1) to minimize EMI.
An internal low-rDS(on) switch has a current-limit feature to prevent inadvertent reset when turning on the 5Vg
output.
R1 Rmod -
Clock PGND 22 F470 F
Modulator
+ Vref Charge
Pump
12 kW - Inrush
+ Current Limit
5Vg_ENABLE
5Vg
+ 5Vg_Supply
- 1 F100 F
SCR0 AOUT
Slew Rate Shutdown
Control Regulator Temp 5 kW
SCR1
Monitor
CLP Low-Power
Low-Power Mode Mode Bandgap POR With
Delay Timer 5 kW
Digital Signal Control Ref
GND RESET
REST
2.2 nF150 nF
B0130-01
Upper:
R1 + R2
V(driver) = 2.5 V
R1
Lower:
R1 + R2
V(driver) = 2.3 V
R1 (1)
Vdriver
Q1
Gate Driver
Q3 47 F
Q2
Gate
Driver
5Vg
VOUT
5Vg
Charge Pump
typ ~VOUT 100 mV
100 F
RESET
VOUT
typ 4.65 V
RESET Deglitch
RESET 5Vg_ENABLE
S0174-01
See the converter efficiency plots in the Typical Characteristics section to determine power dissipation.
Input Vdriver
Voltage
SMPS
Q1
Current
Control
L1
Q2
Switch 33 H
Control
L2
Q4
VOUT
Q3
22 F470 F
FB
S0182-01
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
22 H100 H
4.7 nF 4.7 nF
L1 L2
Cboot1
VOUT 5V
22 F470 F
Cboot2
L
Vbattery Vdriver
R2 5Vg 5V
C
AIN
1 F100 F
R1
TPIC74101-Q1 5V
ENABLE
5 kW
Vlogic RESET
470 nF
Optional 5 kW
Connection AOUT
5Vg_ENABLE
REST SCR1
2.2 nF150 nF
CLP
SCR0
Rmod
12 kW PGND
GND
S0183-01
A. To minimize voltage ripple on the output due to transients, it is recommended to use a low-ESR capacitor on the VOUT
line.
B. The L and C component values are system application dependent for EMI consideration.
DV OUT + DI L ESR ) 8 f SW
1
COUT
(V (pp))
(5)
Usually, the first term is dominant.
I pk(t on ) t off)
C OUT + (F)
8 Vripple (6)
75
Efficiency %
70
65
SCR: 00, V(driver) = 17 V
SCR: 10, V(driver) = 17 V
SCR: 10, V(driver) = 11 V
60 SCR: 01, V(driver) = 17 V
SCR: 01, V(driver) = 11 V
SCR: 00, V(driver) = 11 V
55 SCR: 11, V(driver) = 17 V
50
100 150 200 250 300 350 400 450 500 550 600
IO Output Current mA
G004
NOTE: The average converter efficiency with four different slew rate controls (SCRx) on the Q1 switching FET with input
voltage V(driver) = 11 V and 17 V, TA = 125C.
10 Layout
10.1.1.1 Inductor
Use a low-EMI inductor with a ferrite-type closed core. Other types of inductors may be used; however, they
must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.
Thermal Vias
Package Outline
M0026-01
Figure 22. Package and PCB Land Configuration for a Multilayer PCB
1,5038-mm1,5748-mm
Component Trace
(2-oz. Cu)
2 Plane
1,0142-mm1,0502-mm
Ground Plane
Thermal Via (1-oz. Cu)
4 Plane 1,5748 mm
0,5246-mm0,5606-mm
Power Plane
Thermal Isolation (1-oz. Cu)
Power Plane Only
0-mm0,071-mm Board
Base and Bottom Pad
Package Outline
M0028-01
When this attachment method is not implemented correctly, this product may operate inefficiently. Power dissipation capability
may be adversely affected when the device is incorrectly mounted onto the circuit board.
Multiple vias connect the input, output, and package pad to the ground plane
11.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 4-Nov-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPIC74101QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 T74101D5
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 4-Nov-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2016
Pack Materials-Page 2
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