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How to draw timing diagram? Discuss the various steps.

You first need to understand the machine cycles Now, to draw the timing diagram for any
of 8085 instruction you need to understand what exactly
The status signals are as follows the instruction does. I will explain a few. If you
IO/M(bar) :--- 1 IO 0 Memory need a specific instruction, msg me.
S1 | S0 | Process A) MOV A,B
0 |0 | Halt Draw only opcode fetch as no further memory acces is
0 |1 | Write required as operands specified in registers only
1 |0 | Read B) MVI A,32H
1 |1 | Opcode fetch Draw opcode fetch and memory read as operand(1
1)Opcode fetch ( Compulsory Machine cycle) byte) has to be fetched from memory
This cycle requires 4 T-states. C) LXI H, 2000H
1st T state ALE is high and lower byte of address from Draw Opcode Fetch and two memory Reads as two
PC(Program Counter) is placed on the multiplexed bytes, 00H and 20H, (lower byte fetched first) have to
data/address bus. be read from memory.
In the second T-state, after checking the status of D) STA 2000H
READY pin, RD(bar) goes low the opcode is placed on This instruction stores the value of accumulator(8 bit)
the data bus, This state continues in the 3rd T-State. at the location specified.
The fourth T-state is used by the uP to decode the Opcode fetch + Memory read * 2 (byte address) +
instruction and to generate the relevant control signals. Memory write * 1(1 byte)
The state of the address bus is unspecified( This T- i.e 13 T-states 4+3+3+3
state is used by some DMA controllers to transfer data During the memory write the address bus contains the
in hidden/transperant mode) address fetched by the memory read cycle earlier
IO/M_ = 0 S1=1 S0=1 E) CALL addresss(can be specifed in terms of a
2)Memory read(for 1 byte) label)
Three T states, similar to the first 3 T states of opcode During a call instruction the uP pushes the current
fetch( as first 3 states of opcode fetch is effectively value of program counter(16 bit ie 2 byte) to the stack
memory read) and then copies the new value from the
IO/M_ 0 S1 = 1 S0 = 0 memory(specified in the instruction)
3) Memory Write(for 1 byte) 6 T state Opcode fetch
Similar to Write but instead of RD bar WR bar is used. + Memory write * 2 (PC pushed to stack)
Also the data stays on the bus a little longer than + Memory read * 2 (New value of PC fetched from
READ*. memory)
IO/M_ 0 S1 = 0 S0 = 1 ie 6 + 3 + 3 + 3 + 3 = 18 T-states
4) & 5) IO write and read Note that during the memory write cycle the address
Simlar to the above two, only IO/M_ = 1 bus contains the address of the top of the stack(Stack
These are the basic machine cycles you will require to Pointer)
draw timing diagrams for most instructions. There are F)JMP 16-bit address
additional cycles such as INTA bar and Bus idle. If 3 Cycles as Follows
anyone requires diagrams for these cycles, message 4 T-State Opcode Fetch
me and i will explain them later. + 2 * Memory Read ( 16 bit = 2 bytes)
Also some instructions like CALL require 6 T-state ie 4 + 3 + 3 = 10 T-states.
Opcode fetch. For this you can draw the 4 T state Note that separate cycle is not required for loading the
Opcode fetch but 4th T state extended to the fifth and address into the PC as PC is a register.
sixth T state.

Opcode fetch machine cycle of 8085 :

Each instruction of the processor has one byte opcode.

The opcodes are stored in memory. So, the processor executes the opcode fetch
machine cycle to fetch the opcode from memory.
Hence, every instruction starts with opcode fetch machine cycle.
The time taken by the processor to execute the opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching the opcode from memory
and the remaining T-states are used for internal operations by the processor.

Fig - Timing Diagram for Opcode Fetch Machine Cycle

Memory Read Machine Cycle of 8085:

The memory read machine cycle is executed by the processor to read a data byte
from memory.
The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word size will use the machine
cycle after the opcode fetch machine cycle.

Fig - Timing Diagram for Memory Read Machine Cycle

Timing diagram for STA 526AH.

STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
The opcode of the STA instruction is said to be 32H. It is fetched from the
memory 41FFH(see fig). -OF machine cycle
Then the lower order memory address is read(6A). - Memory Read Machine Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.

Timing diagram for INR M

Fetching the Opcode 34H from the memory 4105H. (OF cycle)
Let the memory address (M) be 4250H. (MR cycle -To read Memory address
and data)
Let the content of that memory is 12H.
Increment the memory content from 12H to 13H. (MW machine cycle)

Timing diagram for MVI B, 43H.

Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
Read (move) the data 43H from memory 2001H. (memory read)