Hiertest RAK Lab 16.1

HANDS-ON LABS
MODUS and GENUS: Integration of Hierarchical

Test
Lab Instructions
1 Introduction | Cadence Design System, Inc.

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Contents
Introduction ..................................................................................................................................... 4
How to get the RAK Testcase Database ..................................................................................... 4
RAK Directory Structure ............................................................................................................ 4
Tool Versions .............................................................................................................................. 5
Running the Lab .......................................................................................................................... 5
Frequently Used Terms ............................................................................................................... 5
Lab Flow ..................................................................................................................................... 6
Lab 1a: Inserting Core Level XOR Compression and 1500/WIR structures.................................. 7
Lab 1b: Core Level ATPG Generation and Verification .............................................................. 22
Lab 2a: Inserting SOC Level XOR Compression, 1500 WIR/JTAG and SOC integration ......... 27
Lab 2b: SOC Level ATPG Generation and Verification .............................................................. 35

Introduction
In the following labs you will learn how to:
Process a chip with Hierarchical test methods including but not limited to:
- Core level 1500 wrapping

- Core level WIR insertion
- Core level Compression insertion
- Core level Pattern Migration
- Chip level wrapped core integration
- Chip level WIR insertion
- Chip level Compression insertion
- Chip level core pattern verification
- Chip level pattern verification
Note: Review the presentation document and the following lab instructions before starting the
labs, and use them as a reference throughout the labs.
How to get the RAK Testcase Database

RAK Testcase database, scripts and references can be found at Attachments and Related
Solutions section below the PDF. The PDF can be searched with the document Title on
https://support.cadence.com
RAK Directory Structure

This RAK contains the following files and directories:
RTL // Contains design RTL files
SCRIPTS // Contains the scripts for running GENUS
o run_dft_CoreA/B.tcl // Run script for core processing
o setup_core.tcl // Global setup script for core processing
o load_core.tcl // RTL load files for core processing
o dft_setup_core.tcl // dft setup script for core processing
o dft_scan_core_comp.tcl // dft insertion flow for core compression/1500/WIR
o run_dft_chip.tcl // Run script for chip level processing
o setup_chip.tcl // Global setup script for chip level processing
o load_chip.tcl // RTL load files for chip level processing
o dft_setup_chip.tcl // dft setup script for chip level processing

o dft_scan_chip_comp.tcl // dft insertion flow for chip compression and
integration
LIBS // Contains .lib and verilog libraries
o /timing // Contains the .lib files for synthesis
o /verilog // Contains the structural verilog libraries for simulation
o /atpg // Contains the verilog libraries for ATPG
SOURCEFILES // Contains files for synthesis and ATPG
o *.sdc // sdc files needed for synthesis
o OSC_mode.int // ATPG mode initialization file for OPCG logic
CHIP_SCRIPTS // Contain chip level custom scripts
o *.pinassign // Pinassign files for chip level flow
o TBDseqPatt.* // Testmode setup files for chip level flow
o runmodus.HIER_CORE_MIGRATION_CHIP.tcl // Core pattern migration script
o runmodus.CHIP.atpg.tcl // Chip level atpg flow
o run_*_sim // Chip level iRun verification scripts
DOCS // Contains .pdf files for the documentation of this RAK
o Hiertest_RAK_lab_16.2.pdf // The lab notes (this document)
o Hiertest_Overview_16.2.pdf // The presentation slides for this RAK
Tool Versions
The labs have been verified with the following software versions. Some of the messages and
log lines explained in the instructions may not appear with other versions.
GENUS Synthesis 16.11-s015 or greater
MODUS Test 16.10 or greater (should be last in your $path variable)
Incisive NC-Verilog simulator 15.10 (earlier versions should work)
Running the Lab

To run the lab:
Unzip and untar MODUS-GENUS-Hiertest-16.2.tgz

cd to Hiertest-DFT_RAK_16.2
Frequently Used Terms

Rapid Adoption Kit (RAK)
MODUS Test (MODUS)

GENUS Synthesis (GENUS)
Incisive Unified Simulator (IUS)
Design for Test (DFT)
Lab Flow
The following figure represents the design and test structure of the DTMF chip that is used for
all the labs in this RAK. DTMF_INST0/1 are identical. DTMF_INST2/3 are identical.
Figure 1-1: Design and test structure of the DTMF chip

Lab 1a: Inserting Core Level XOR Compression
and 1500/WIR structures
Goal
This lab discusses the flow and scripting required to run specific aspects of DFT in the GENUS
and MODUS environment. We will:
Run scripts and look into log files to understand the GENUS/MODUS integration.
Insert DFT structures that increase testability in the design.
Insert shadow logic around memories
Define and insert 1500 Wrapper Instruction Registers (WIR)
Insert 1500 Wrapper cells on the Core boundary
Create wrapper and scan channels
Insert XOR compression and the Test Interconnect Macro (TIM)
Understand how to drive GENUS Synthesis and MODUS Test flows.
For this lab we will run the main script run_dft_CoreA.tcl.
Technical Overview
The focus of this lab is to process a Core module for use in a Hierarchical Test methodology.
GENUS and MODUS both support the IEEE 1500 standard for core testing, which is what we will
be using. XOR compression will be used to reduce channel length of the scan chains in the core
module thus reducing data volume and test time. A bit-sliced WIR will be inserted to control
test signals needed by the core and to reduce the required dft pin count. 1500 core wrapping
on the I/O pins of the core will then be inserted to create an isolatable test structure. The core
test information and patterns will then be migrated for use in a chip level parent module. This
lab will also show the GENUS to MODUS integration and full ATPG generation and verification.
7 Lab 1a: Inserting Core Level XOR Compression and 1500/WIR structures | Cadence
Design System, Inc.
Lab Files
This lab uses the following files in the ./SCRIPTS directory.
run_dft_CoreA.tcl
setup_core.tcl
load_core.tcl
dft_setup_core.tcl
dft_scan_core_comp.tcl
Running the Lab

Run the following script from the Hiertest-DFT_RAK_16.2 directory:
./SCRIPTS/run_dft_CoreA.tcl
Run the script as follows: genus -f ./SCRIPTS/run_dft_CoreA.tcl
Understanding the Flow

1. Let us look at the files we are working with in this lab. Change directory to ./SCRIPTS
and locate the setup_core.tcl file. The main purpose of this script is to set up the
variables and libraries that will be used in the labs. Note that a separate RESULTS
directory and ATPG directory will be create for each Core as it will ensure that different
module labs wont overwrite each other.
2. Now let us look at the content of the main run script that is running. Here is a
breakdown of the script flow for clarity:
Load all the design files and elaborate

Read sdc (in SOURCEFILES dir) and define cost groups
Read in DFT setup (dft_setup_core.tcl)
Synthesize to GENERIC (syn_gen)
Synthesize to MAPPED (syn_map)
Connect Clock Gating
Run DFT flow script (dft_scan_core_comp.tcl)
Incremental synthesis
Write results and database to RESULTS_dft_CoreA_Hiertest directory
Write MODUS files and ATPG flow
Design System, Inc.
3. Let us look at the dft_setup_core.tcl file and review the special setup that we are doing
for DFT. As you can see in the previous step, we have not yet mapped the design. This
is not required in this case as we are just defining signals
As per Figure 1-1, we are specifying the scan related pins for GENUS. This is done with,
but not limited to, the following commands:
define_shift_enable (pins that are set to a value during the scan shift phase)
define_test_mode (pins that are set to a value during the entire test)
define_test_clock (pins that clock during shift and/or capture phases)
define_scan_chain (pins that are used as scan input/output channels)
define_test_signal (defines a test bus port for use in the Hierarchical Flow )
4. Let us take a closer look at the define_test_signal definitions in this file.
This definition type is specifically used to describe signals that are to be used for
connection to the Compression macro, TIM, 1500 wrapper cells and WIR register. To
facilitate this a -function switch is used to delineate each signals function.
## Bit 0
define_test_signal -function wint -name WINT -wir_signal
## Bit 1
define_test_signal -function wext -name WEXT -wir_signal
Notice the -wir_signal aspect to the above definitions. This tells the tool to create a WIR
register bit to control this function.
The next definitions create the SI/SO ports that will be used to connect to the TIM
module and drive the compression structure and the FULLSCAN chains.
define_test_signal -create_port -function compress_sdi SI[0] -index 0

define_test_signal -create_port -function compress_sdo SO[0] -index 0
The next definitions describe the 1500 interface signals that will eventually be
connected up to the JTAG module at the chip level.
Design System, Inc.
define_test_signal -create_port -name WSI -function serial_sdi WSI
define_test_signal -create_port -name WSO -function serial_sdo WSO
define_test_signal -create_port -name serial_WRCK -function serial_wrck serial_WRCK
define_test_signal -create_port -name WRSTN -function wrapper_reset WRSTN
define_test_signal -create_port -name WRAPCK -function wrapper_clock WRAPCK
define_test_signal -create_port -name COMPCK -function compression_clock COMPCK
define_test_signal -create_port -name SelectWR -function select_wir SelectWR
define_test_signal -create_port -name ShiftWR -function shift_wr ShiftWR
define_test_signal -create_port -name UpdateWR -function update_wr UpdateWR
## The following command will add WINT/WEXT and create the logic for
## shift enable signals and clock gating control based on INTEST/EXTEST modes of 1500
add_wir_signal_bits -create_wrapper_shift_enables_for_delay_test scan_en

-create_cgic_enable_for_wrap scan_en
The -create_wrapper_shift_enables_for_delay_test switch will create separate shift

enable signal logic for INTEST and EXTEST mode. The -create_cgic_enable_for_wrap will
create additional signals named DFTWSEI and DFTWSEO, which are the independent
shift enable signals for the input and output wrapper cells that drives the added logic
and is gated with INTEST and EXTEST mode. The purpose of these switches is to control
power to the chip. So during EXTEST mode the internal clock gating and shifting will be
blocked.
Function Purpose
async_set_reset Testmode signal that controls the asynchronous set/reset pin of a flop
broadcast_enable Enable of the broadcast-based decompression logic
capture_wr WIR capture control
compress_sdi Common scan data input (broadcast to multiple cores)
compress_sdo Common scan data output
compression_clock Test clock used for compression mask (and MISR if present)
compression_enable Control to enable compression mode
custom User specified control signal
mask_enable Data input to enable channel masking
mask_load Control to enable mask loading mode
misr_reset_enable Control signal to reset the MISR (misr compression only)
pipe_sen Control pin that enables the pipeline flops. It is usually a shift enable pin.
select_bypass Select 1500 bypass mode
select_serial Select 1500 serial mode
Design System, Inc.
select_wir Select Wrapper Instruction Register (WIR) access control signal
serial_sdi 1500 Wrapper Serial Input
serial_sdo 1500 Wrapper Serial Output
serial_wrck 1500 clock for shifting the WIR and bypass registers
shift_enable Test signal that controls the shifting of data in a scan chain
shift_wr WIR shift control
spread_enable Control to enable the xor decompressor
test_mode Test signal that controls the design in test mode
update_wr WIR update control
wext Wrapper Extest control signal
wint Wrapper Intest control signal
wir_test Test-mode signal to put the WIR in its ATPG-test mode
wrapper_and_compression_clock Shared compression and wrapper clock
wrapper_clock Wrapper instruction and dedicated wrapper cell clock
wrapper_reset Wrapper instruction register reset control
5. Now let us look at the main content of the DFT flow. Open the file
dft_scan_core_comp.tcl. The first thing you should notice is that we are checking DFT
rules. It is recommended you check DFT rules multiple times during a DFT flow. By now
your script should be past DFT rule checking. Look at the following files in the results
directory ./RESULTS_dft_CoreA_Hiertest:
dtmf_large_recvr_CoreA-tdrcs (initial DFT rule checking)

dtmf_large_recvr_CoreA-tdrcs_postfix (Rule checking after any DRC fixing)
This information is very important in understanding how DFT friendly your design is.
Information on how many FFs pass DFT rules, what kind of violations you may have
preventing FFs from passing checks, etc. You should see a log something similar to this:
Summary of check_dft_rules
**************************
Number of usable scan cells: 44
Clock Rule Violations:
---------------------
Internally driven clock net: 0
Tied constant clock net: 0
Undriven clock net: 0
Conflicting async & clock net: 0
Misc. clock net: 0
Design System, Inc.
Async. set/reset Rule Violations:
--------------------------------
Internally driven async net: 0
Tied active async net: 0
Undriven async net: 0
Misc. async net: 0
Advanced DFT Rule Violations:

----------------------------------
Tristate net contention violation: 0
Potential race condition violation: 0
X-source violation: 0
Warning: There are a total of 7 undriven pins which may act as x-source generators. For
the list of pins, use the command 'check_design -undriven -report_scan_pins'.
Total number of DFT violations: 0
Total number of Test Clock Domains: 1

DFT Test Clock Domain: clk
Test Clock 'clk' (Positive edge) has 485 registers
Test Clock 'clk' (Negative edge) has 16 registers
Number of user specified non-Scan registers: 6
Number of registers that fail DFT rules: 0
Number of registers that pass DFT rules: 501
Percentage of total registers that are scannable: 98.8%
As you can see, there are zero registers that Fail DFT rules. This means we are set to
move forward with replacing FFs with scan flops and inserting compression. One thing
that should be checked is the 7 undriven pins message. This could possibly effect
compression efficiency. In our particular case, the undriven signals are scan related pins
that have been created but not connected yet. See the following:
check_design -undriven -report_scan_pins
Checking the design.
Check Design Report

--------------------
Undriven Port(s)/Pin(s)
------------------------
Design System, Inc.
No undriven combinational pin in 'dtmf_large_recvr_CoreA'
No undriven sequential pin in 'dtmf_large_recvr_CoreA'
The following hierarchical pin(s) in design 'dtmf_large_recvr_CoreA' are undriven

hpin:dtmf_large_recvr_CoreA/wir_instance/WIR_SI (fanout : 1)
hpin:dtmf_large_recvr_CoreA/wir_instance/wir_testpoint/Bypass (fanout : 1)
hpin:dtmf_large_recvr_CoreA/wir_instance/wir_testpoint/Serial (fanout : 1)
Total number of hierarchical undriven pins in design 'dtmf_large_recvr_CoreA' : 3
The following port(s) in design 'dtmf_large_recvr_CoreA' are undriven

port:dtmf_large_recvr_CoreA/SO[0]
port:dtmf_large_recvr_CoreA/WSO
Total number of undriven port(s) in design 'dtmf_large_recvr_CoreA' : 4
6. The script now inserts Shadow Logic around possible untestable logic. In this design, we
will put logic around all of the memories in the design so that the surrounding logic is
more testable.
We will use this technique on the following memories:
dtmf_large_recvr_CoreA/DTMF_INST0/RAM_128x16_TEST_INST
dtmf_large_recvr_CoreA/DTMF_INST0/ROM_512x16_0_INST
add_shadow_logic -mode share -test_control test_mode -exclude CLOCK \

-balance -test_clock_pin clk \
-around "inst:dtmf_large_recvr_${CoreName}/RAM_128x16_TEST_INST_RAM_128x16_INST \
Design System, Inc.
inst:dtmf_large_recvr_${CoreName}/RAM_256x16_TEST_INST_RAM_256x16_INST"
add_shadow_logic -mode share -test_control test_mode -exclude CLOCK \

-balance -test_clock_pin clk \
-around "inst:dtmf_large_recvr_${CoreName}/ROM_512x16_0_INST"
7. The script now replaces any non-scan flops in the design that pass DFT rules with an
equivalent scan flop using the GENUS command convert_to_scan. The possible
replacement scan flops are derived from the .lib files.
8. The next step is to define additional signals for 1500 wrapper control and insertion. If
you recall we already defined WINT and WEXT. Those are shown below in the code as
comments.
##################################################
# Define and Insert Additional WIR registers
##################################################
## Bit 0
#define_test_signal -function wint -name WINT -wir_signal
## Bit 1
#define_test_signal -function wext -name WEXT -wir_signal
## Bit 2
define_test_signal -function compression_enable -name SCOMP -wir_signal
## Bit 3
define_test_signal -function spread_enable -name SPREAD -wir_signal
## Bit 4
define_test_signal -function select_serial -name SERIAL -wir_signal
## Bit 5
define_test_signal -function select_bypass -name BYPASS -wir_signal
## Bit 6
define_test_signal -function broadcast_enable -name BCAST_EN -wir_signal
These signals will be individual registers created in the WIR to control test operation on
this core. They will be loaded through the serial chain interface on the WIR during a
Design System, Inc.
mode init sequence. For instance loading a 1001101 (MSB->LSB) would put us in
COMPRESSION_INTEST mode with the Spreader network active.
9. Once we have defined the signals we want to add them to the WIR register. This is very
simply done by executing add_wir_signal_bits. This will synthesize the register bits and
connect them to the previous bits that were added in and incremental fashion. The
hardware structure will look something like the following picture.
10. Next step in the flow is to insert the actual 1500 Wrapper cells around the core via the
add_core_wrapper_cell command. In order to optimize the insertion, the end user
needs to understand whether they want a fully dedicated cells (an additional FF for each
IO port of the core) or shared cells. The shared cell approach is the one we are going to
discuss her since it is the more optimal in area/timing and used by most.
## Find pins in the design associated with 1500 mode and shift enable control
set corewint [get_db hpins *WINT]
set corewext [get_db hpins *WEXT]
set corewsen_in [get_db hpins *wir_instance/DFTWSEI]
set corewsen_out [get_db hpins *wir_instance/DFTWSEO]
Design System, Inc.
The above GENUS commands use the get_db command to find the signals that were
created when we inserted the WIR register bits. These signals were created back in Step 4.
## Getting a list of input ports and output ports

##
set inportlist [get_ports -filter "direction==in"]
set outportlist [get_ports -filter "direction==out"]
## Add 1500 Wrapper on Input Ports

##
set wrappedInputList [ add_core_wrapper_cell \
-skipped_locations_variable skipped_in -location $inportlist \
-exclude spi_data spi_clk reset tdsp_pso \
-wsen_in $corewsen_in \
-wsen_out $corewsen_out \
-wck WRAPCK \
-wext $corewint \
-wint $corewext \
-name wrap_in -shared_through buffer]
## Add 1500 Wrapper on Output Ports

##
set wrappedOutputList [ add_core_wrapper_cell \

-skipped_locations_variable skipped_out -location $outportlist \
-wsen_in $corewsen_in \
-wsen_out $corewsen_out \
-wck WRAPCK \
-wext $corewint \
-wint $corewext \
-guard 0 \
-wog $corewint \
-name wrap_out -shared_through buffer ]
The switch -shared_through determines how GENUS decides what internal FF is used as the
sharing flop or whether a dedicated cell is needed instead. Below is an excerpt from the
documentation on the rules GENUS uses to determine if a functional flop is shareable.
-shared_through {buffer|inverters_and_buffers|combinational}
Design System, Inc.
Specifies whether the functional flop in the wrapper cell must be shared. If a shared cell is
inserted, the command traces through the logic to identify a shareable functional flop (or
flops).
A functional flop in a wrapper cell can be shared if:

1. It is directly connected to the core pin through
- a series of buffers (buffer)
- a series of inverters and buffers
- complex combination logic (combinational)
2. It is mapped to a scan flip-flop for DFT purposes.
3. The clock pin to the flop is controllable; that is, the flip-flop must pass the DFT
rules.
4. The flop has no connected enable pin.
5. The functional flop is not already shared with another wrapper cell.
Note: If you use this option and the functional flop cannot be
shared, the Genus-DFT engine issues a message and inserts a
dedicated cell if you specified the -wck option, otherwise an
error message is given.
To create a consistent clocking scheme at the head and tail of each scan chain created
you can use the following commands.
set_db [get_db designs] .dft_clock_edge_for_head_of_scan_chains leading

set_db [get_db designs] .dft_clock_edge_for_tail_of_scan_chains trailing
This will insure the first element of the chain is rising edge and the last is trailing edge. If
the chain is not consistent with that then lockup latches will be inserted.
11. At this point in the script there are wrapper cells inserted into your design but they are
not connected into and wrapper scan chains yet. We need to specify to GENUS how
many chains we want and what elements will be included into those chains.
## Create 1500 Wrapper chains from the previous inserted 1500 cells
set_db / .dft_prefix DFT_WCHAIN
set numWrapChains 3
set core_wrapper_ss [get_db scan_segments * -if {.core_wrapper==true}]
for {set i 0} {$i < $numWrapChains} {incr i} {
define_scan_chain -sdi WCHAIN_SI[$i] -sdo WCHAIN_SO[$i] -create_ports
}
Design System, Inc.
The previous statements define 3 wrapper chains that will have the prefix DFT_WCHAIN.
The individual wrapper cells that were added previously are actually added as
scan_segments in the database. We search these scan_segments to see which of them
have an attribute of core_wrapper on them and use all of these cells to create the
chains. The actual connecting of these chains is done as follows.
check_dft_rules
connect_scan_chains -elements $core_wrapper_ss
set wchains [vfind actual_scan_chain:*/*/DFT_W*]
12. The next step is to create the internal scan channels that will eventually be connected
up to the compression network. The plan is for 24 internal channels to be created with
the prefix of DFT_ICHAIN. This is accomplished in the script as follows.
set num_ichan 24
set_db / .dft_prefix DFT_ICHAIN
for {set i 0} {$i < $num_ichan} {incr i} {
define_scan_chain -sdi ICHAIN_SI[$i] -sdo ICHAIN_SO[$i] -create_ports
}
check_dft_rules
connect_scan_chains -incr
set ichains [vfind actual_scan_chain:*/*/DFT_I*]
13. Now we are all set to insert test compression into the design. We have 3 wrapper
channels ($wchains) and 24 internal channels ($ichains), which will be incorporated into
the compression structure.
add_test_compression -compressor xor -decompressor xor \

-use_existing_channels [vfind actual_scan_chain:*/*/DFT_ICHAIN*] \
-use_existing_wrapper_channels [vfind actual_scan_chain:*/*/DFT_WCHAIN*] \
-bypass_reg \
-build_new_scan_chains 3 /designs/$DESIGN \
-use_wir_macro wir_instance \
-auto_create
There are some key aspects of the compression command to mention here. First is the
-use_existing_*_channels switches which direct the compression synthesis on what
chains to use. The -bypass_reg switch inserts a single register for 1500 bypass mode.
The -use_wir_macro instructs the synthesis to connect the WIR up to the TIM that will
be created. Finally the -build_new_scan_chains 3 will build 3 FULLSCAN chains that
drive the compression structure. Here is what the structure will resemble.
Design System, Inc.
14. The next significant command in the script is directed at checking the 1500 scan chain
configurations that were created during the add_test_compression stage.
check_test_bus_connections -wir_macro wir_instance
Here is a look at some of the logfile that is produced and gives a good understanding of
what is being checked. Parts have been removed to make this text shorter.
Running check_test_bus_connections...
Design supports 1500 serial modes...
Tracing chains for mode SERIAL_BYPASS...

Analyzed 1 scan registers, 0 lockup elements in existing scan chain
Found 1 registers while tracing from WSO (WSO) back to WSI (WSI) in mode
SERIAL_BYPASS
Successfully traced serial chain in mode SERIAL_BYPASS
Tracing chains for mode SERIAL_EXTEST...

Detected scan_en as shift-enable pin (active high) for chain DFT_ICHAINchain_1
Design System, Inc.
Found 42 registers while tracing from WSO (WSO) back to WSI (WSI) in mode
SERIAL_EXTEST
Successfully traced serial chain in mode SERIAL_EXTEST
Tracing chains for mode SERIAL...

Detected scan_en as shift-enable pin (active high) for chain DFT_ICHAINchain_1
Found 560 registers while tracing from WSO (WSO) back to WSI (WSI) in mode SERIAL
Successfully traced serial chain in mode SERIAL
Tracing chains for mode FULLSCAN_EXTEST...

Found 14 registers while tracing from SDO (SO[0]) back to SDI (SI[0]) in mode
FULLSCAN_EXTEST
FULLSCAN_EXTEST
FULLSCAN_EXTEST
Successfully traced parallel chains in mode FULLSCAN_EXTEST
Tracing chains for mode FULLSCAN_INTEST...

FULLSCAN_INTEST
FULLSCAN_INTEST
FULLSCAN_INTEST
Successfully traced parallel chains in mode FULLSCAN_INTEST
Tracing chains for mode FULLSCAN...

Successfully traced parallel chains in mode FULLSCAN
15. This script is finished and exits back to the main run script. On return it goes through an
incremental optimization of the logic and writes out a number of DFT related files and
flows. These are important for the overall hierarchical flow.
Design System, Inc.
write_dft_abstract_model -include_compression_information \
-include_controllable_outputs > $_OUTPUTS_PATH_HierTest/${DESIGN}-scanAbstract
write_hdl -abstract > $_OUTPUTS_PATH_HierTest/${DESIGN}-logicAbstract
These two files are used in the chip level flow to read in a logic model of this core along
with scan information of what is contained in the core. This aids in hierarchical test
connections to the core.
write_dft_atpg -compression -tcl \

-library "./LIBS/atpg/include_libraries.v" \
-ncsim_library "./LIBS/verilog/include_libraries_sim.v" \
-directory $MODUS_WORKDIR_HierTest -hier_test_core -serial
This command creates the MODUS flow for this core. There is a key switch we should
highlight. The -hier_test_core switch will create a MODUS flow for Core pattern
migration for a true hierarchical methodology. This includes creating patterns in
*_INTEST modes. These patterns are then migrated for use in chip-level integration.
Also, the remainder testmodes are prepared for use in chip-level integration. This way
the top understands the EXTEST modes needed for ATPG.
The GENUS flow for CoreA is now complete.
16. Execute the same identical flow now for CoreB.
Run the script as follows: genus -f ./SCRIPTS/run_dft_CoreB.tcl
Design System, Inc.
Lab 1b: Core Level ATPG Generation and
Verification
Goal
This lab discusses the MODUS ATPG generation flow. This includes generating patterns in
multiple modes, migrating patterns for hierarchical integration and verifying the patterns
through simulation.
1. Look at the directory ./atpg_Hiertest_CoreA_workdir and you should see the following
files generated by GENUS:
dtmf_large_recvr_CoreA.test_netlist.v (completed verilog netlist)

runmodus.atpg.tcl (MODUS ATPG run script)
dtmf_large_recvr_CoreA.*_INTEST.pinassign (MODUS file specifying IO pin
behavior in multiple INTEST configurations)
dtmf_large_recvr_CoreA.*_EXTEST.pinassign (MODUS file specifying IO pin
behavior in multiple EXTEST configurations)
dtmf_large_recvr_CoreA.*_BYPASS.pinassign (MODUS file specifying IO pin
behavior in multiple BYPASS configurations)
dtmf_large_recvr_CoreA.*.seqdef (MODUS sequence setup files for multiple
configuration modes)
run_*_intest_sim (NC-sim scripts to verify ATPG patterns in intest modes)
run_*_intest_sim_sdf (NC-sim scripts to verify ATPG patterns in intest
modes with SDF)
Look at the runmodus.atpg.tcl script. The steps in the script are similar to the flow
discussed in the presentation. First is the MODUS core processing mode which takes
the core through building the model, testmodes, verifying them and generating ATPG
patterns. The second flow will migrate the core for chip-level hierarchical integration
along with pattern migration.
22 | Cadence Design System, Inc.

MODUS Core ATPG Flow MODUS Core Migration Flow
The MODUS flow starts with building the testmodes that configure the circuit into
internal and external test structures. These testmodes leverage the TIM (Test Interface
Macro) to control the connection and flow of data. All the scan connections run
through this module as seen below. This is a picture of one of the main configurations
for ATPG pattern generation, COMPRESSION_DECOMP_INTEST.
23 Lab 1b: Core Level ATPG Generation and Verification | Cadence Design System, Inc.
The scan data traces through this structure as follows:
- Scan Input pins (SI) -> CPI bus of TIM

- TIM RSI_SI bus -> RSI_SI bus of Compactor
- Through XOR Decompressor logic -> SWBOX_SI bus of TIM
- CHAIN_SI bus of TIM -> Head of Internal Scan channels
- Tail of Internal Channels -> CHAIN_SO bus of TIM
- SWBOX_SO bus of TIM -> Through XOR Compressor logic -> DSO_SO bus of TIM
- CPO bus of TIM -> Scan Output pins (SO)
2. Take a look at the testmodes that are created and verified in the runmodus.atpg.tcl
script.
- FULLSCAN_INTEST, _EXTEST, _BYPASS
- COMPRESSION_INTEST, _EXTEST, _BYPASS
- COMPRESSION_DECOMP_INTEST, _EXTEST, _BYPASS
- SERIAL_INTEST, _EXTEST, _BYPASS
- WIR_SCAN
The testmodes that create actual ATPG patterns are all of the _INTEST modes. The
order of the ATPG pattern generation is based on configurations that will give the user
the best results with the lowest test time impact. The default values for the
create_logic_tests commands is targeted at achieving the optimal results. There are
design cases where you may need to add switches to improve the efficiency of the tool.
The EXTEST modes are relevant at the chip-level for pattern generation and therefore
we do not generate patterns at this stage.
Once the ATPG pattern generation is completed in the script, the core migration part of
the flow is executed.
3. At this point we should run the MODUS script so we can discuss results and log files.
modus -f ./atpg_HierTest_CoreA_workdir/runmodus.atpg.tcl
4. When the script is finished take a look in the testresults/logs directory.
How many channels are in COMPRESSION_DECOMP_INTEST? (hint: look at the

log_report_test_structures log for that mode)
So how do the ATPG results look?
What is the AtCov testmode fault coverage after COMPRESSION_DECOMP_INTEST?
5. The core migration flow part of the script begins with the building of a migration model.
to be used for hierarchical test.
build_core_migration_model \
-coremigrationdir atpg_HierTest_CoreA_workdir/dtmf_large_recvr_CoreA_DIR
Once you run the script you will see a new directory created as listed above. Inside that
there will be another directory created named dtmf_large_recvr_CoreA(B). This
directory contains elements similar to what you would see in a standard tbdata
directory. That is because this is exactly what it is. This is a tbdata of the migrated core
model. It includes the core model that is needed in chip-level integration and creation
of EXTEST tests. You will also see patterns and coreInfo files for all the testmode
configurations that might be needed in the hierarchical flow.
6. The next step in the script is the migration of the core faults.
prepare_core_migration_faults \
-coremigrationdir atpg_HierTest_CoreA_workdir/dtmf_large_recvr_CoreA_DIR \
-testmode COMPRESSION_DECOMP_INTEST
This command collects information from the core faultModel that will be used when the
core is integrated at the chip level. The information it gathers is for faults that are
associated with logic that is not included in the core migration model (that is, the faults
that are in the INTEST testmodes but not in the EXTEST testmodes. This information
includes the total number of faults and the number of detected faults. It writes the out-
of-context core fault information into the core migration directory listed above as a fault
rule file that is read in during build_faultmodel at the chip level. This command is done
for each testmode that ATPG patterns were generated for.
7. The next step in the flow is migrating information for each core testmode. The end
result is the chip level will have the necessary information to understand all the
testmodes configured into this core.
prepare_core_migration_info \
8. The final step in the migration flow is to prepare the actual patterns generated at the
core for migration to the SOC level. This steps converts the patterns into a format to be
migrated.
prepare_core_migration_tests \
9. At this time we should verify the patterns generated. This requires running Verilog
simulation of the testbenches. These patterns should all run clean without errors.
./atpg_HierTest_CoreA_workdir/run_compression_intest_sim
./atpg_HierTest_CoreA_workdir/run_compression_decomp_intest_sim
./atpg_HierTest_CoreA_workdir/run_fullscan_intest_sim
./atpg_HierTest_CoreA_workdir/run_serial_intest_sim
./atpg_HierTest_CoreB_workdir/run_compression_intest_sim
./atpg_HierTest_CoreB_workdir/run_compression_decomp_intest_sim
./atpg_HierTest_CoreB_workdir/run_fullscan_intest_sim
./atpg_HierTest_CoreB_workdir/run_serial_intest_sim
Lab 2a: Inserting SOC Level XOR Compression,
1500 WIR/JTAG and SOC integration
Goal
This lab discusses the flow and scripting required to run specific aspects of DFT in the GENUS
and MODUS environment. We will:
Run scripts and look into log files to understand the GENUS/MODUS integration
Define and insert JTAG macro with 1500 compatibility
Insert shadow logic around memories
Define and insert 1500 Wrapper Instruction Registers (WIR) at SOC level
Create SOC scan channels
Insert XOR compression and the SOC Test Interconnect Macro (TIM)
Read in core level abstract models
Connect top level test structures and check connections
1. Take a look at the script file dft_setup_chip.tcl. What you will notice that is different in
this file compared to the core flow is the specification for JTAG.
define_dft jtag_instruction_register -name INSTR_REGISTER -length 4 -capture XX01
define_jtag_instruction -name WIR -opcode 0001 -register WIR_REG -length 1

define_jtag_instruction -name SCAN -opcode 0010 -register SCAN_REG -length 1
define_jtag_instruction -name PROGRAM_WIR -opcode 1000 -register
PROGRAM_WIR_REG -length 1
define_jtag_instruction -name EXTEST -opcode 0100
define_jtag_instruction -name SAMPLE -opcode 0101
define_jtag_instruction -name PRELOAD -opcode 0101
define_jtag_instruction -name BYPASS -opcode 0111
The difference from an 1149.1 setup is the added instructions for the WIR register. This
WIR chain will end up being a serial chain from TDI to TDO. See the diagram below and
follow the red arrows. The other connections will be explained later.
27 Lab 2a: Inserting SOC Level XOR Compression, 1500 WIR/JTAG and SOC integration
| Cadence Design System, Inc.
2. The JTAG macro is inserted with a simple command once all the previous definitions are
set.
add_jtag_macro -generate_wrck
The -generate_wrck is an important aspect of this command. It tells GENUS that this
JTAG module will be interfacing to 1500 wrapped cores. It generates appropriate
connections as shown below.
3. Next why dont we execute the main script while we look into the main dft insertion
script.
genus -f ./SCRIPTS/run_dft_top.tcl
4. While that is running take a look at the dft_scan_chip_comp.tcl script. More specifically
the section on WIR register insertion. We are adding another top level WIR to control
the SOC level compression. This WIR will be daisy chained with the core level WIRs.
## Bit 0
define_test_signal -function select_bypass -wir_signal -name SEL_BYPASS
## Bit 1
define_test_signal -function compression_enable -wir_signal -name SCOMP
## Bit 2
define_test_signal -function spread_enable -wir_signal -name SPREAD
## Bit 3
define_test_signal -function select_serial -wir_signal -name SERIAL
## Bit 4
define_test_signal -function broadcast_enable -wir_signal -name BCAST_EN
add_wir_signal_bits
The add_wir_signal_bits has a -preview option. You will see output like this:
add_wir_signal_bits -preview
Info: will insert wir signal for test signal 'SEL_BYPASS' with bit index '0'.
Info: will insert wir signal for test signal 'SCOMP' with bit index '1'.
Info: will insert wir signal for test signal 'SPREAD' with bit index '2'.
Info: will insert wir signal for test signal 'SERIAL' with bit index '3'.
Info: will insert wir signal for test signal 'BCAST_EN' with bit index '4'.
5. We now want to configure the top level scan chains in preparation for insertion of the
SOC level compression structure. The method for this is very similar to what we did at
the core level. The only difference is we are not adding 1500 wrapper chains at this
level.
## Create Internal scan channels to be used by add_test_compression

set num_ichan 24
set_db / .dft_prefix DFT_ICHAIN
for {set i 0} {$i < $num_ichan} {incr i} {
define_dft scan_chain -sdi ICHAIN_SI[$i] -sdo ICHAIN_SO[$i] -create_ports
}
The above for loop will define 24 scan chains and the SI/SO ports that will connect to
them.
## Connect up internal scan channels
connect_scan_chains -chains [vfind scan_chain:*/*/DFT_I*]
The above statement will find all of the DFT_ICHAIN* scan chains that we defined
previously and fill them with all the FFs that pass DFT rules. If you look in the genus
logfile after the run is over you will see similar text to this:
Configuring 24 chains for 569 scan f/f

Domain 'scan_clk' - (rise): 32, (fall): 0
Domain 'TCK' - (rise): 0, (fall): 0
Domain 'refclk' - (rise): 521, (fall): 16
Domain 'JTAG_MODULE__JTAG_WRCK' - (rise): 0, (fall): 0
Clock 'scan_clk' (pin 'port:dtmf_chip/scan_clk') - (rise): 32, (fall): 0
Clock 'TCK' (pin 'port:dtmf_chip/TCK') - (rise): 0, (fall): 0
Clock 'refclk' (pin 'port:dtmf_chip/refclk') - (rise): 521, (fall): 16
Configured 2 chains for Domain: 'scan_clk', edge: 'mixed'
DFT_ICHAINchain_1 (ICHAIN_SI[0] -> ICHAIN_SO[0]) has 16 registers;
Domain:scan_clk, edge: mixed
Domain:scan_clk, edge: mixed
Configured 22 chains for Domain: 'refclk', edge: 'mixed'
Domain:refclk, edge: mixed

6. The insertion of the compression module and Top-TIM are next.
add_test_compression -top -compressor xor -decompressor xor \

-use_wir_macro wir_instance -bypass_reg \
-use_existing_channels [vfind actual_scan_chain:*/*/DFT_ICHAIN*] \
-build_new_scan_chains 3 /designs/$DESIGN \
-auto_create
You will see that this command is very similar to what was done at the core level. The
only difference is at the core level wrapper_channels were included. The command
makes sure that we build an interface to the SOC WIR macro that we created.
7. One aspect of the SOC level connections that needs to be done manually at this time is
the connection of the shift enable signals to the cores. These cores are empty black
boxes at this point.
for {set i 0} {$i < 3} {incr i} {

edit_netlist hier_connect hpin:dtmf_chip/IOPADS_INST/scan_enI
hpin:dtmf_chip/DTMF_INST$i/scan_en
}
This edit_netlist command will find the scan_enI pin, which is the base leaf of the main
shift enable signal. It will then connect it to the 3 cores that were processed
8. Next in the script we need to incorporate the DFT information of these cores so we can
properly connect up signals to them. If you recall we wrote out dft based abstract
models during the core phase.
write_dft_abstract_model -include_compression_information -
include_controllable_outputs > $_OUTPUTS_PATH_HierTest/${DESIGN}-scanAbstract
Take a look at this file to understand what is in it and why its needed. You will mainly
see test port definitions and abstract_segment definitions. Here is a sample.
define_test_bus_port -name {SI[0]} -module dtmf_large_recvr_CoreA -function

compress_sdi -index 0 {SI[0]}
define_test_bus_port -name {SO[0]} -module dtmf_large_recvr_CoreA -function
compress_sdo -index 0 {SO[0]}
define_scan_abstract_segment -module dtmf_large_recvr_CoreA \

-name dtmf_large_recvr_CoreA_DFT_ICHAINchain_1 \
-sdi SI[0] -sdo SO[0] \
-shift_enable_port scan_en -active high \
-test_mode_port ShiftWR -test_mode_active high \
-test_mode_port reset -test_mode_active low \
-test_mode_port DFT_ICHAINITC_CAPTURE_WR -test_mode_active high \
-test_mode_port UpdateWR -test_mode_active high \
-test_mode_port spi_fs -test_mode_active low \
-test_mode_port test_mode -test_mode_active high \
-test_mode_port SelectWR -test_mode_active low \
-test_mode_port WRSTN -test_mode_active high \
-clock_port clk -fall \
-tail_clock_port clk -tail_edge_rise \
-skew_safe \
-head_skew_safe \
-length 187
9. This is how the script reads in the abstract models.
read_dft_abstract_model -assume_connected_shift_enable
./RESULTS_dft_CoreA_HierTest/dtmf_large_recvr_CoreA-scanAbstract
read_dft_abstract_model -assume_connected_shift_enable
./RESULTS_dft_CoreB_HierTest/dtmf_large_recvr_CoreB-scanAbstract
10. At this point we have added almost all of the DFT hardware in this flow. What needs to
be done now is to create the TopTIM and connect everything together. The key aspect
of the TopTIM is that all the chain connections go through here as shown below.
Also connected are the signals from the JTAG to all the WIR interfaces of the cores and
the top-level WIR. This is all done with a simple command.
connect_dft_top_level
11. The last step in the insertion part of the script is to check the different chain
configurations just like we did in Step 14 of Lab1a. You will also see similar log results of
chain configuration tracing.
check_test_bus_connections -wir_macro -wir_instance
12. The execution of the script at this point reverts back to the main run_dft_chip.tcl script.
There is one key element left in the flow and that is to write out the MODUS flow for the
DFT structures that were created. This is what the command looks like.
write_dft_atpg -compression -tcl -directory $MODUS_WORKDIR_HierTest \
-library
"./LIBS/atpg/include_libraries.v,atpg_HierTest_CoreA_workdir/dtmf_large_recvr_CoreA
_DIR,atpg_HierTest_CoreB_workdir/dtmf_large_recvr_CoreB_DIR" \
-build_faultmodel_options
"./atpg_HierTest_CoreA_workdir/dtmf_large_recvr_CoreA_DIR:./atpg_HierTest_CoreB_
workdir/dtmf_large_recvr_CoreB_DIR" \
-ncsim_library "./LIBS/verilog/include_libraries_sim.v"
What is important to note in this command is what is highlighted in red. If you

remember in the core based flow we created ATPG patterns and migrated the faults for
SOC level. The directories listed above are the tbdata locations of the fault databases
for the cores. These will be used at the SOC level in MODUS.
Next step is to run the MODUS flow for the SOC design.
Lab 2b: SOC Level ATPG Generation and
Verification
Goal
This lab discusses the MODUS ATPG generation flow. This includes generating patterns in
multiple modes, migrating patterns of hierarchical cores and verifying the patterns through
simulation.
1. Look at the directory ./CHIP_SCRIPTS and you should see the following files generated
by GENUS:
runmodus.HIER_CORE_MIGRATION_CHIP.atpg.tcl (MODUS ATPG run script

for migration of core level testmodes and patterns)
runmodus.CHIP.atpg.tcl (MODUS ATPG run script for CHIP level)
dtmf_chip.*.pinassign (MODUS files specifying IO pin behavior in multiple
CHIP configurations)
TBDseqPatt.* (MODUS sequence setup files for configuration modes)
run_migrated_sim_* (NC-sim scripts to verify core-level ATPG patterns in
intest modes)
run_*_extest_chip_sim (NC-sim scripts to verify SOC level ATPG patterns
with the cores in EXTEST mode)
These scripts have been custom created for the user. The complete
integrated generation is not available as of this software version.
The netlist needed for MODUS is located in the following path:
RESULTS_dft_chip_Hiertest/dtmf_chip_final_dft.v
2. We should understand what is in the runmodus scripts. The first of the two to run is
runmodus.HIER_CORE_MIGRATION_CHIP.tcl. Execute the following while we take a
look at the flow and what is going on.
modus -f ./CHIP_SCRIPTS/runmodus.HIER_CORE_MIGRATION_CHIP.tcl
3. The first obvious step is to build the Modus test model.
35 Lab 2b: SOC Level ATPG Generation and Verification | Cadence Design System, Inc.
build_model \
-cell dtmf_chip \
-techlib ./LIBS/atpg/include_libraries.v,
atpg_HierTest_CoreA_workdir/dtmf_large_recvr_CoreA_DIR,
atpg_HierTest_CoreB_workdir/dtmf_large_recvr_CoreB_DIR \
-designsource ./RESULTS_dft_chip_HierTest/dtmf_chip_final_dft.v \
-blackboxoutputs z \
-allowmissingmodules yes
build_faultmodel \
-coremigrationpath ./atpg_HierTest_CoreA_workdir/dtmf_large_recvr_CoreA_DIR:
./atpg_HierTest_CoreB_workdir/dtmf_large_recvr_CoreB_DIR
The unique aspect to notice in the two build commands are the items under the
switches -techlib and -coremigrationpath. More specifically the pointers to 2 directories
for CoreA and CoreB integration.
cd into ./ atpg_HierTest_CoreA_workdir/dtmf_large_recvr_CoreA_DIR
You will see another directory. In this case dtmf_large_recvr_CoreA. Change directory
into here. You will notice that this looks similar to a standard Modus tbdata directory.
That is exactly this it is, the Core migration tbdata.
coreInfo.* - The testmode configurations that can be migrated.

coreFaultRule.gz - The faultrule file containing fault info for the migrated core.
TBDtdm.dtmf_large_recvr_CoreA.* - What do you think these are for?
4. Next in the runmodus script are the steps to build testmodes at the chip level that use
the migrated testmodes of the cores. Then migrating the patterns that were created at
the core level. We are migrating a number of different configurations but it is not
limited to those. Lets take a look at the flow for one of these testmodes.
build_core_migration_testmode \
-testmode inst0_intest \
-assignfile ./CHIP_SCRIPTS/dtmf_chip.COMPRESSION_CoreA_inst0.pinassign \
./atpg_HierTest_CoreB_workdir/dtmf_large_recvr_CoreB_DIR \
-seqdef ./CHIP_SCRIPTS/TBDseqPatt.COMP_CoreA_Inst0_wint \
-modedef COMPRESSION_INTERNAL
This testmode will put CoreA Inst0 into INTEST mode and the remaining cores and logic
in either bypass or extest mode.
5. The key aspect to building the testmode at the chip level properly is setting the bits in
the serial WIR register properly. Taking into account all of the WIR bits that have been
added and connection order shown previously in this doc, you should have a 26-bit
serial register that looks like this:
Based on the previous diagram we can then begin to understand the programming
going on in the TBDpatt.* files. The programming of the WIR register is as follows:
- load compliance pins

- JTAG reset
- Load opcode 1000 (PROGRAM_WIR) into Instruction Register
- Move to Shift-DR state to shift in the bits for the WIR
- Shift in the bits
o # Shift-DR. Loading 11000101000000100100010010. ->load instruction wir
- Move to Update-DR state to lock in the values
- Put JTAG module into RunTestIdle
When complete your register should look like this:
6. Once the testmode is built properly the script will migrate the patterns, write the
patterns at the chip level and then commit the faults.
migrate_core_tests \
./atpg_HierTest_CoreB_workdir/dtmf_large_recvr_CoreB_DIR \
-experiment logic_migrated
write_vectors \
-inexperiment logic_migrated \
-scanformat serial
commit_tests -inexperiment logic_migrated -testmode inst0_intest -force yes
7. It is now a good time to simulate and verify the migrated patterns of the cores.
Run the following:
./CHIP_SCRIPTS/run_migrated_sim_coreA_inst0
./CHIP_SCRIPTS/run_migrated_sim_coreA_inst1
./CHIP_SCRIPTS/run_migrated_sim_coreB_inst2
./CHIP_SCRIPTS/run_migrated_sim_coreA_inst0_inst1
The logfiles will end up in the top level atpg directory atpg_HierTest_top_workdir.
8. Look now at the script to generate chip level patterns for the logic at the chip level and
all the cores in EXTEST mode. While we go through this script run the following:
modus -f ./CHIP_SCRIPTS/runmodus.CHIP.atpg.tcl
You will notice this is a pretty standard Modus compression flow. The building of
multiple testmodes, design rule checking, generation of ATPG pattern and writing them.
The interesting aspect to look at here is configuring the cores in EXTEST mode. Lets
look at the seqdef like we did in the previous INTEST mode step.
This is what the seqdef mode initialization file or COMPRESSION_EXTEST_CHIP mode

looks like:
- load compliance pins

- JTAG reset
- Load opcode 1000 (PROGRAM_WIR) into Instruction Register
- Move to Shift-DR state to shift in the bits for the WIR
- Shift in the bits
o # Shift-DR. Loading 01000011001001100100110010. ->load instruction wir
- Move to Update-DR state to lock in the values
- Put JTAG module into RunTestIdle
When complete your register should look like this:
9. It is now a good time to simulate the chip level patterns.
Run the following:
./CHIP_SCRIPTS/run_compression_decomp_extest_chip_sim
./CHIP_SCRIPTS/run_compression_extest_chip_sim
./CHIP_SCRIPTS/run_fullscan_extest_chip_sim
The logfiles will end up in the top level atpg directory atpg_HierTest_top_workdir.
SUMMARY: You have run through the GENUS Hierarchical flow. You should have
knowledge of inserting DFT structures at a core level, wrapping the core with 1500,
inserting an internalWIR register to control the core in testmode, generating patterns
and migrating those to the chip level. Then integrating these cores in a chip level
hierarchical structure. The flow discussed in the labs can be integrated with other DFT
aspects such as boundary scan, memory BIST, SmartScan and LBIST. For more
information on the flow specifics, read the comments in the .tcl files.

Hiertest RAK Lab 16.1

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HANDS-ON LABS

MODUS and GENUS: Integration of Hierarchical

1 Introduction | Cadence Design System, Inc.

All other trademarks are the property of their respective holders.

Restricted Print Permission: This publication is protected by copyright and any

Restricted Rights: Use, duplication, or disclosure by the Government is subject to

2 Introduction | Cadence Design System, Inc.

3 Introduction | Cadence Design System, Inc.

- Core level 1500 wrapping

How to get the RAK Testcase Database

RAK Directory Structure

4 Introduction | Cadence Design System, Inc.

Running the Lab

Unzip and untar MODUS-GENUS-Hiertest-16.2.tgz

Frequently Used Terms

5 Introduction | Cadence Design System, Inc.

Figure 1-1: Design and test structure of the DTMF chip

6 Introduction | Cadence Design System, Inc.

For this lab we will run the main script run_dft_CoreA.tcl.

Running the Lab

Run the script as follows: genus -f ./SCRIPTS/run_dft_CoreA.tcl

Understanding the Flow

Load all the design files and elaborate

4. Let us take a closer look at the define_test_signal definitions in this file.

define_test_signal -create_port -function compress_sdi SI[0] -index 0

add_wir_signal_bits -create_wrapper_shift_enables_for_delay_test scan_en

The -create_wrapper_shift_enables_for_delay_test switch will create separate shift

dtmf_large_recvr_CoreA-tdrcs (initial DFT rule checking)

Advanced DFT Rule Violations:

Total number of DFT violations: 0

Total number of Test Clock Domains: 1

check_design -undriven -report_scan_pins

Checking the design.

Check Design Report

No undriven sequential pin in 'dtmf_large_recvr_CoreA'

The following hierarchical pin(s) in design 'dtmf_large_recvr_CoreA' are undriven

The following port(s) in design 'dtmf_large_recvr_CoreA' are undriven

We will use this technique on the following memories:

add_shadow_logic -mode share -test_control test_mode -exclude CLOCK \

add_shadow_logic -mode share -test_control test_mode -exclude CLOCK \

## Getting a list of input ports and output ports

## Add 1500 Wrapper on Input Ports

## Add 1500 Wrapper on Output Ports

set wrappedOutputList [ add_core_wrapper_cell \

A functional flop in a wrapper cell can be shared if:

set_db [get_db designs] .dft_clock_edge_for_head_of_scan_chains leading

add_test_compression -compressor xor -decompressor xor \

check_test_bus_connections -wir_macro wir_instance

Design supports 1500 serial modes...

Tracing chains for mode SERIAL_BYPASS...

Tracing chains for mode SERIAL_EXTEST...

Tracing chains for mode SERIAL...

Tracing chains for mode FULLSCAN_EXTEST...

Tracing chains for mode FULLSCAN_INTEST...

Tracing chains for mode FULLSCAN...

write_hdl -abstract > $_OUTPUTS_PATH_HierTest/${DESIGN}-logicAbstract

write_dft_atpg -compression -tcl \

The GENUS flow for CoreA is now complete.

16. Execute the same identical flow now for CoreB.

Run the script as follows: genus -f ./SCRIPTS/run_dft_CoreB.tcl

dtmf_large_recvr_CoreA.test_netlist.v (completed verilog netlist)

22 | Cadence Design System, Inc.

- Scan Input pins (SI) -> CPI bus of TIM

4. When the script is finished take a look in the testresults/logs directory.

connect_scan_chains -chains [vfind scan_chain://DFT_I*]