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So

Soff t ware-Defined Radio Handbook


Radio
12th Edition

Sampling
Principles of SDR
FPGA Resources
Resources
Optical Resources
Resources
Products
Complementar
Complementaryy PProducts
roducts
Applications
by

Rodger H
H.. Hosking
Vice-President & Cofounder of Pentek, Inc.

Pentek, Inc.
One Park Way, Upper Saddle River, New Jersey 07458
Tel: (201) 818-5900 Fax: (201) 818-5904
Email: info@pentek.com http://www.pentek.com

Copyright 1998, 2001, 2003, 2006, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016 Pentek, Inc.
Last updated: August 2016
All rights reserved.
Contents of this publication may not be reproduced in any form without written permission.
Specifications are subject to change without notice.
Pentek, GateFlow, ReadyFlow, SystemFlow, Cobalt, Onyx, Talon, Bandit, Flexor, GateXpress, SPARK, and QuickPac are trademarks or registered trademarks of Pentek, Inc.
Other trademarks are properties of their respective owners.

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Software-Defined Radio Handbook

Preface

SDR (Software-Defined Radio) has revolutionized electronic systems for a


variety of applications including communications, data acquisition and signal processing.

This handbook shows how DDCs (Digital Downconverters) and DUCs (Digital Upconverters),
the fundamental building blocks of SDR, can replace legacy analog receiver and transmitter designs while
offering significant benefits in performance, density and cost.

In order to fully appreciate the benefits of SDR, conventional analog receiver and transmitter
systems will be compared to their digital counterparts, highlighting similarities and differences.

The inner workings of the SDR will be explored with an in-depth description of the internal
structure and the devices used. Finally, some actual board- and system-level implementations and available
off-the-shelf SDR products and applications based on such products will be presented.

For more information on complementary subjects, the reader is referred to these Pentek Handbooks:
Critical Techniques for High-Speed A/D Converters in Real-Time Systems
High-Speed Switched Serial Fabrics Improve System Design
Putting FPGAs to Work in Software Radio Systems
High-Speed, Real-Time Recording Systems
Putting VPX and OpenVPX to Work

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Software-Defined Radio Handbook

Sampling

Nyquists Theorem and Sampling A Simple TTechnique


echnique to Visualize Sampling

Before we look at SDR and its various implementa-


tions in embedded systems, well review a theorem
fundamental to sampled data systems such as those Frequency
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
encountered in Software-Defined Radios.

Nyquists Theorem:
Any signal can be represented by discrete Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7
samples if the sampling frequency is at least twice
the bandwidth of the signal.
Figure 1

Notice that we highlighted the word bandwidth To visualize what happens in sampling, imagine that
rather than frequency. In what follows, well attempt to you are using transparent fan-fold computer paper.
show the implications of this theorem and the correct Use the horizontal edge of the paper as the frequency
interpretation of sampling frequency, also known as axis and scale it so that the paper folds line up with
sampling rate. integer multiples of one-half of the sampling frequency s.
Each sheet of paper now represent what we will call a
Nyquist Zone, as shown in Figure 1.

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Software-Defined Radio Handbook

Sampling

Sampling Basics Baseband Sampling

0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2 0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
Energy

No Signal Energy

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7 Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

Figure 2 Figure 4

Use the vertical axis of the fan-fold paper for signal A baseband signal has frequency components that
energy and plot the frequency spectrum of the signal to start at = 0 and extend up to some maximum frequency.
be sampled, as shown in Figure 2. To see the effects of
To prevent data destruction when sampling a baseband
sampling, collapse the transparent fan-fold paper into a
signal, make sure that all the signal energy falls ONLY in
stack.
the 1st Nyquist band, as shown in Figure 4.
There are two ways to do this:
0 fs/2 1. Insert a lowpass filter to eliminate all signals
Folded Signals
Fall On Top of
above s/2, or
Each Other 2. Increase the sampling frequency so all signals
present fall below s/2.
Note that s/2 is also known as the folding frequency.

Sampling Bandpass Signals

Lets consider bandpass signals like the IF frequency


Figure 3 of a communications receiver that might have a 70 MHz
center frequency and 10 MHz bandwidth. In this case,
the IF signal contains signal energery from 65 to 75 MHz.
The resulting spectrum can be seen by holding the
transparent stack up to a light and looking through it. If we follow the baseband sampling rules above, we
You can see that signals on all of the sheets or zones are must sample this signal at twice the highest signal
folded or aliased on top of each other and they frequency, meaning a sample rate of at least 150 MHz.
can no longer be separated. However, by taking advantage of a technique called
Once this folding or aliasing occurs during sampling, undersampling, we can use a much lower sampling rate.
the resulting sampled data is corrupted and can never be
recovered. The term aliasing is appropriate because
after sampling, a signal from one of the higher zones
now appears to be at a different frequency.

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Software-Defined Radio Handbook

Sampling

Undersampling

Folded signals
still fall on top of
each other - but 0 fs/2
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
now there is
energy in
only one sheet !

No Signal Energy No Signal Energy

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

Figure 5 Figure 6

Undersampling allows us to use aliasing to our The major rule to follow for successful undersampling
advantage, providing we follow the strict rules of the is to make sure all of the energy falls entirely in one
Nyquist Theorem. Nyquist zone.
In our previous IF signal example, suppose we try a There two ways to do this:
sampling rate of 40 MHz. 1. Insert a bandpass filter to eliminate all signals
outside the one Nyquist zone.
Figure 5 shows a fan-fold paper plot with Fs = 40 MHz.
2. Increase the sampling frequency so all signals
You can see that zone 4 extends from 60 MHz to 80 MHz,
fall entirely within one Nyquist zone.
nicely containing the entire IF signal band of 65 to 75 MHz.
Now when you collapse the fan fold sheets as shown
in Figure 6, you can see that the IF signal is preserved Summar
Summaryy
after sampling because we have no signal energy in any
other zone. Baseband sampling requires the sample frequency to
be at least twice the signal bandwidth. This is the same
Also note that the odd zones fold with the lower
as saying that all of the signals fall within the first
frequency at the left (normal spectrum) and the even
Nyquist zone.
zones fold with the lower frequency at the right (reversed
spectrum). In real life, a good rule of thumb is to use the 80%
relationship:
In this case, the signals from zone 4 are frequency-
reversed. This is usually very easy to accommodate in the Bandwidth = 0.8 * s / 2 = 0.4 * s
following stages of SDR systems.
Undersampling allows a lower sample rate even though
signal frequencies are high, PROVIDED all of the signal
energy falls within one Nyquist zone.
To repeat the Nyquist theorem: The sampling frequency
must be at least twice the signal bandwidth not the
signal frequency.

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Software-Defined Radio Handbook

Principles of SDR

Analog Radio R
Radio eceiver Block Diagram
Receiver Analog Radio R
Radio eceiver Mixer
Receiver

SPEAKER RF INPUT SIGNAL


FROM ANTENNA
ANTENNA
MIXER TRANSLATES Signal
INPUT SIGNAL BAND
ANALOG to IF FREQUENCY
MIXER

RF IF AMP DEMODULATOR AUDIO


AMP (FILTER) (Detector) AMP
ANALOG LOCAL
OSCILLATOR

ANALOG
LOCAL
OSCILLATOR
0 FIF FRF
Figure 7 Figure 8

The conventional heterodyne radio receiver shown The mixer performs an analog multiplication of the
in Figure 7, has been in use for nearly a century. Lets two inputs and generates a difference frequency signal.
review the structure of the analog receiver so comparison
The frequency of the local oscillator is set so that the
to a digital receiver becomes apparent.
difference between the local oscillator frequency and the
First the RF signal from the antenna is amplified, desired input signal (the radio station you want to
typically with a tuned RF stage that amplifies a region of receive) equals the IF.
the frequency band of interest.
For example, if you wanted to receive an FM
This amplified RF signal is then fed into a mixer station at 100.7 MHz and the IF is 10.7 MHz, you would
stage. The other input to the mixer comes from the local tune the local oscillator to:
oscillator whose frequency is determined by the tuning
100.7 - 10.7 = 90 MHz
control of the radio.
This is called downconversion or translation
The mixer translates the desired input signal to the
because a signal at a high frequency is shifted down to a
IF (Intermediate Frequency) as shown in Figure 8.
lower frequency by the mixer.
The IF stage is a bandpass amplifier that only lets
The IF stage acts as a narrowband filter which only
one signal or radio station through. Common center
passes a slice of the translated RF input. The band-
frequencies for IF stages are 455 kHz and 10.7 MHz
width of the IF stage is equal to the bandwidth of the
for commercial AM and FM broadcasts.
signal (or the radio station) that you are trying to
The demodulator recovers the original modulating receive.
signal from the IF output using one of several different
For commercial FM, the bandwidth is about
schemes.
100 kHz and for AM it is about 5 kHz. This is consis-
For example, AM uses an envelope detector and FM tent with channel spacings of 200 kHz and 10 kHz,
uses a frequency discriminator. In a typical home radio, respectively.
the demodulated output is fed to an audio power amplifier
which drives a speaker.

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Software-Defined Radio Handbook

Principles of SDR

SDR Receiver Block Diagram


Receiver

DDC
Digital Downconverter
Digital
Analog Analog Digital IF Baseband
RF Signal RF IF Signal A/D Samples DIGITAL LOWPASS Samples
DSP
TUNER CONV MIXER FILTER

DIGITAL
LOCAL
OSC

Figure 9

Figure 9 shows a block diagram of a software SDR Receiver Mixer


Receiver
defined radio receiver. The RF tuner converts analog RF
signals to analog IF frequencies, the same as the first three
CHANNEL
stages of the analog receiver. BANDWIDTH MIXER TRANSLATES
INPUT SIGNAL
BAND to DC IF BW
The A/D converter that follows digitizes the IF signal Signal

thereby converting it into digital samples. These samples are


fed to the next stage which is the digital downconverter DIGITAL LOCAL
(DDC) shown within the dotted lines. OSCILLATOR
FLO = FSIG
The digital downconverter is typically a single
monolithic chip or FPGA IP, and it is a key part of the
SDR system.
0 FSIG
Figure 10
A conventional DDC has three major sections:
A digital mixer
A digital local oscillator At the output of the mixer, the high frequency
wideband signals from the A/D input (shown in Figure
An FIR lowpass filter
10 above) have been translated down to DC as complex I
The digital mixer and local oscillator translate the and Q components with a frequency shift equal to the
digital IF samples down to baseband. The FIR lowpass local oscillator frequency.
filter limits the signal bandwidth and acts as a decimat- This is similar to the analog receiver mixer except
ing lowpass filter. The digital downconverter includes a there, the mixing was done down to an IF frequency.
lot of hardware multipliers, adders and shift register Here, the complex representation of the signal allows us
memories to get the job done. to go right down to DC.
The digital baseband samples are then fed to a block By tuning the local oscillator over its range, any
labeled DSP which performs tasks such as demodulation, portion of the RF input signal can be mixed down to DC.
decoding and other processing tasks.
In effect, the wideband RF signal spectrum can be
Traditionally, these needs have been handled with slid around 0 Hz, left and right, simply by tuning the
dedicated application-specific ICs (ASICs), and program- local oscillator. Note that upper and lower sidebands are
mable DSPs. preserved.

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Software-Defined Radio Handbook

Principles of SDR

DDC LLocal
ocal Oscillator and Decimation DDC Signal PProcessing
rocessing

Translation Filtering

Digital
Digital IF Baseband
A/D Samples DIGITAL LOWPASS Samples
CONV MIXER FILTER
90O

DIGITAL
LOCAL
OSC

Tuning Freq Decimation


F1 F2 F3
Figure 12
Figure 11A Local Oscillator Frequency Switching

This process is called decimation and it means keeping


A/D Sample Rate one out of every N signal samples. If the decimated
(before decimation)
Sample Rate: Fs output sample rate is kept higher than twice the output
bandwidth, no information is lost.
Decimated
Filter Output
The clear benefit is that decimated signals can be
Sample Rate: Fs/N processed easier, can be transmitted at a lower rate, or
stored in less memory. As a result, decimation can
Figure 11B FIR Filter Decimation dramatically reduce system costs!
As shown in Figure 12, the DDC performs two
signal processing operations:
Because the local oscillator uses a digital phase
accumulator, it has some very nice features. It switches 1. Frequency translation with the tuning controlled
between frequencies with phase continuity, so you can by the local oscillator.
generate FSK signals or sweeps very precisely with no
2. Lowpass filtering with the bandwidth controlled
transients as shown in Figure 11A.
by the decimation setting.
The frequency accuracy and stability are determined
We will next turn our attention to the Software-
entirely by the A/D clock so its inherently synchronous
Defined Radio Transmitter.
to the sampling frequency. There is no aging, drift or
calibration since its implemented entirely with digital logic.
Since the output of the FIR filter is band-limited, the
Nyquist theorem allows us to lower the sample rate. If we
are keeping only one out of every N samples, as shown in
Figure 11B above, we have dropped the sampling rate by
a factor of N.

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Software-Defined Radio Handbook

Principles of SDR

SDR TTransmitter
ransmitter Block Diagram

Digital Digital Analog Analog


Baseband Baseband Digital IF IF RF
Samples Samples DIGITAL Samples Signal Signal
INTERPOLATION D/A RF Power
DSP
FILTER MIXER CONV Upconverter Amplifier
Fs/N Fs Fs

DUC DIGITAL
Digital Up LOCAL
Converter OSC

Figure 13

The input to the transmit side of an SDR system is a DUC Signal PProcessing
rocessing
digital baseband signal, typically generated by a DSP
stage as shown in Figure 13 above.
The digital hardware block in the dotted lines is a Digital Digital
DUC (digital upconverter) that translates the baseband Baseband Baseband Digital IF
Samples Samples DIGITAL Samples
signal to the IF frequency. INTERPOLATION
FILTER MIXER
Fs/N Fs Fs
The D/A converter that follows converts the digital
IF samples into the analog IF signal. DUC DIGITAL
Digital Up LOCAL
Next, the RF upconverter converts the analog IF Converter OSC

signal to RF frequencies.
Figure 14
Finally, the power amplifier boosts signal energy to
the antenna.
Inside the DUC shown in Figure 14, the digital
mixer and local oscillator at the right translate baseband
samples up to the IF frequency. The IF translation
frequency is determined by the local oscillator.
The mixer generates one output sample for each of
its two input samples. And, the sample frequency at
the mixer output must be equal to the D/A sample
frequency s.
Therefore, the local oscillator sample rate and the
baseband sample rate must be equal to the D/A sample
frequency s.
The local oscillator already operates at a sample rate
of s, but the input baseband sample frequency at the
left is usually much lower. This problem is solved with
the Interpolation Filter.

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Software-Defined Radio Handbook

Principles of SDR

Interpolation FFilter:
ilter: Time domain Interpolation FFilter:
ilter: FFrequency
requency Domain

Fs/N Fs Digital Digital


Baseband Baseband Digital IF
I INTERPOLATING I Samples Samples Samples
LOW PASS INTERPOLATION DIGITAL
Q FIR FILTER Q Fs/N FILTER MIXER
Fs Fs
BASEBAND INTER-
INPUT POLATED DUC
OUTPUT DIGITAL
Digital Up LOCAL
Converter OSC
INTERPOLATION
FACTOR = N
INTERPOLATED
BASEBAND INPUT TRANSLATED OUTPUT
Baseband Input
MIXER
Sample Rate: Fs/N

LOCAL
OSCILLATOR
F = IF Freq
Interpolating
Filter Output
Sample Rate: Fs 0 IF Freq

Figure 15 Figure 16

The interpolation filter must boost the baseband Figure 16 is a frequency domain view of the digital
input sample frequency of s / N up to the required upconversion process.
mixer input and D/A output sample frequency of s.
This is exactly the opposite of the frequency domain
The interpolation filter increases the sample frequency view of the DDC in Figure 10.
of the baseband input signal by a factor N, known as the
The local oscillator setting is set equal to the re-
interpolation factor.
quired IF signal frequency, just as with the DDC.
At the bottom of Figure 15, the effect of the
interpolation filter is shown in the time domain.
Notice the baseband signal frequency content is
completely preserved by filling in additional samples in
the spaces between the original input samples.
The signal processing operation performed by the
interpolation filter is the inverse of the decimation filter
we discussed previously in the DDC section.

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Software-Defined Radio Handbook

Principles of SDR

DDC PProcessing
rocessing DUC PProcessing
rocessing

Translation Filtering Filtering Translation

A/D DIGITAL LOWPASS INTERPOLATE DIGITAL D/A


DSP DSP
CONV MIXER FILTER FILTER MIXER CONV

Fs Fb Fb Fs
DIGITAL N DIGITAL
LOCAL N LOCAL
OSC OSC

Freq uency Deci mation Inter polation Freq uency

Tuning Bandwidth Bandwidth Tuning


Figure 17 Figure 18

Figure 17 shows the two-step processing performed Figure 18 shows the two-step processing performed
by the digital downconverter. by the digital upconverter:
Frequency translation from IF down to baseband is The ratio between the required output sample rate
performed by the local oscillator and mixer. and the sample rate input baseband sample rate deter-
mines the interpolation factor N.
The tuning knob represents the programmability
of the local oscillator frequency to select the desired Baseband bandwidth = 0.8 * b
signal for downconversion to baseband.
Output sample frequency s = b * N
The baseband signal bandwidth is set by setting
Again, the bandwidth equation assumes a complex
decimation factor N and the lowpass FIR filter:
(I+Q) baseband input and an 80% filter.
Baseband sample frequency b = s / N
The bandwidth knob represents the programma-
Baseband bandwidth = 0.8 * b bility of the interpolation factor to select the desired
input baseband signal bandwidth.
The baseband bandwidth equation reflects a typical
80% passband characteristic, and complex (I+Q) samples. Frequency translation from baseband up to IF is
performed by the local oscillator and mixer.
The bandwidth knob represents the program-
mability of the decimation factor to select the desired The tuning knob represents the programmability
baseband signal bandwidth. of the local oscillator frequency to select the desired IF
frequency for translation up from baseband.

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Software-Defined Radio Handbook

Principles of SDR

Key DDC and DUC Benefits SDR TTasks


asks

Digital
Digital IF Baseband
A/D Samples DIGITAL LOWPASS Samples
CONV MIXER FILTER
Fs Fs/N

DIGITAL
DUC
LOCAL Digital Down
OSC Converter

Digital Digital
Baseband Baseband Digital IF
Samples Samples DIGITAL Samples
INTERPOLATION D/A
FILTER MIXER CONV
Fs/N Fs Fs

DUC DIGITAL
Digital Up LOCAL
Converter OSC

Figure 19 Figure 20

Think of the DDC as a hardware preprocessor for Here weve ranked some of the popular signal
programmable DSP or GPP processor. It preselects only processing tasks associated with SDR systems on a two
the signals you are interested in and removes all others. axis graph, with computational Processing Intensity on
This provides an optimum bandwidth and minimum the vertical axis and Flexibility on the horizontal axis.
sampling rate into the processor.
What we mean by process intensity is the degree of
The same applies to the DUC. The processor only highly-repetitive and rather primitive operations. At the
needs to generate and deliver the baseband signals upper left, are dedicated functions like A/D converters
sampled at the baseband sample rate. The DUC then and DDCs that require specialized hardware structures
boosts the sampling rate in the interpolation filter, to complete the operations in real time. ASICs are usually
performs digital frequency translation, and delivers chosen for these functions.
samples to the D/A at a very high sample rate.
Flexibility pertains to the uniqueness or variability
The number of processors required in a system is of the processing and how likely the function may have
directly proportional to the sampling frequency of to be changed or customized for any specific application.
input and output data. As a result, by reducing the At the lower right are tasks like analysis and decision
sampling frequency, you can dramatically reduce the making which are highly variable and often subjective.
cost and complexity of the programmable DSPs or
Programmable general-purpose processors or DSPs
GPPs in your system.
are usually chosen for these tasks since these tasks can be
Not only do DDCs and DUCs reduce the processor easily changed by software.
workload, the reduction of bandwidth and sampling rate
Now lets temporarily step away from the software
helps save time in data transfers to another subsystem. This
radio tasks and take a deeper look at programmable logic
helps minimize recording time and disk space, and reduces
devices.
traffic and bandwidth across communication channels.

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Software-Defined Radio Handbook

FPGA Resources
Resources

Early Roles for FPGAs


Roles Legacy FPGA Design Methodologies

Used primarily to replace discrete digital Tools were oriented to hardware engineers
hardware circuitry for: Schematic processors
Control logic Boolean processors
Glue logic Gates, registers, counters, multipliers

Registers and gates Successful designs required high-level


State machines hardware engineering skills for:
Counters and dividers Critical paths and propagation delays
Devices were selected by hardware engineers Pin assignment and pin locking
Signal loading and drive capabilities
Programmed functions were seldom changed
Clock distribution
after the design went into production Input signal synchronization and skew analysis

Figure 21 Figure 22

As true programmable gate functions became These programmable logic devices were mostly the
available in the 1970s, they were used extensively by domain of hardware engineers and the software tools
hardware engineers to replace control logic, registers, were tailored to meet their needs. You had tools for
gates, and state machines which otherwise would have accepting boolean equations or even schematics to help
required many discrete, dedicated ICs. generate the interconnect pattern for the growing
number of gates.
Often these programmable logic devices were one-
time factory-programmed parts that were soldered down Then, programmable logic vendors started offering
and never changed after the design went into production. predefined logic blocks for flip-flops, registers and
counters that gave the engineer a leg up on popular
hardware functions.
Nevertheless, the hardware engineer was still
intimately involved with testing and evaluating the
design using the same skills he needed for testing
discrete logic designs. He had to worry about propaga-
tion delays, loading, clocking and synchronizingall
tricky problems that usually had to be solved the hard
waywith oscilloscopes or logic analyzers.

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FPGA Resources
Resources

FPGAs: New Device TTechnology


echnology FPGAs: New Development TTools
ools

u 500+ MHz DSP slices and memory structures


u Over 3500 dedicated on-chip hardware multipliers
u On-board GHz serial transceivers High Level Design Tools
u
Partial reconfigurability maintains Block Diagram System Generators
operation during changes Schematic Processors
u Switched fabric interface engines High-level language compilers for
u Over 690,000 logic cells VHDL & Verilog
u Gigabit Ethernet media access controllers Advanced simulation tools for modeling speed,
propagation delays, skew and board layout
u On-chip 405 PowerPC RISC microcontroller cores
Faster compilers and simulators save time
u Memory densities approaching 85 million bits
Graphically-oriented debugging tools
u Reduced power with core voltages at 1 volt
IP (Intellectual Property) Cores
u Silicon geometries to 28 nanometers
FPGA vendors offer both free and licensed cores
u High-density BGA and flip-chip packaging
FPGA vendors promote third party core vendors
u Over 1200 user I/O pins
Wide range of IP cores available
u
Configurable logic and I/O interface standards
Figure 23 Figure 24

Its virtually impossible to keep up to date on FPGA To support such powerful devices, new design tools
technology, since new advancements are being made are appearing that now open up FPGAs to both hard-
every day. ware and software engineers. Instead of just accepting
logic equations and schematics, these new tools accept
The hottest features are processor cores inside the
entire block diagrams as well as VHDL and Verilog
chip, computation clocks to 500 MHz and above, and
definitions.
lower core voltages to keep power and heat down.
Choosing the best FPGA vendor often hinges
Several years ago, dedicated hardware multipliers
heavily on the quality of the design tools available to
started appearing and now youll find literally thousands
support the parts.
of them on-chip as part of the DSP initiative launched
by virtually all FPGA vendors. Excellent simulation and modeling tools help to
quickly analyze worst case propagation delays and
High memory densities coupled with very flexible
suggest alternate routing strategies to minimize them
memory structures meet a wide range of data flow
within the part. This minimizes some of the tricky
strategies. Logic slices with the equivalent of over ten
timing work for hardware engineers and can save one
million gates result from steadily shrinking silicon
hours of tedious troubleshooting during design verifica-
geometries.
tion and production testing.
BGA and flip-chip packages provide plenty of I/O
In the last few years, a new industry of third party
pins to support on-board gigabit serial transceivers and
IP (Intellectual Property) core vendors now offer thou-
other user-configurable system interfaces.
sands of application-specific algorithms. These are ready
New announcements seem to be coming out every to drop into the FPGA design process to help beat the
day from chip vendors like Xilinx and Altera in a never- time-to-market crunch and to minimize risk.
ending game of outperforming the competition.

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FPGA Resources
Resources

FPGAs for SDR FPGAs Bridge the SDR Application Space

Parallel Processing
Hardware Multipliers for DSP
FPGAs can now have over 500 hardware multipliers
Flexible Memory Structures
Dual port RAM, FIFOs, shift registers, look up tables, etc.
Parallel and Pipelined Data Flow
Systolic simultaneous data movement
Flexible I/O
Supports a variety of devices, buses and interface standards
High Speed
Available IP cores optimized for special functions

Figure 25 Figure 26

Like ASICs, all the logic elements in FPGAs can As a result, FPGAs have significantly invaded the
execute in parallel. This includes the hardware multipli- application task space as shown by the center bubble in
ers, and you can now get over 3500 of them on a single the task diagram above.
FPGA.
They offer the advantages of parallel hardware to
This is in sharp contrast to programmable DSPs, handle some of the high process-intensity functions like
which normally have just a handful of multipliers that DDCs and the benefit of programmability to accommo-
must be operated sequentially. date some of the decoding and analysis functions of DSPs.
FPGA memory can now be configured with the These advantages may come at the expense of
design tool to implement just the right structure for increased power dissipation and increased product costs.
tasks that include dual port RAM, FIFOs, shift registers However, these considerations are often secondary to the
and other popular memory types. performance and capabilities of these remarkable devices.
These memories can be distributed along the signal
path or interspersed with the multipliers and math
blocks, so that the whole signal processing task operates
in parallel in a systolic pipelined fashion.
Again, this is dramatically different from sequential
execution and data fetches from external memory as in a
programmable DSP.
As we said, FPGAs now have specialized serial and
parallel interfaces to match requirements for high-speed
peripherals and buses.

15
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Software-Defined Radio Handbook

FPGA Resources
Resources

Pentek PProducts
roducts with FFactor
actor
actoryy-Installed SDR IP Cores

Input Sampling Input DDC Decimation Output DUC Interpol. Chan


Chan.. Out Beam-
Model Channels Freq (max) Bits Chan
Chan.. Range Bits Chan.. Range
Chan Out Bits former

71621 3 200 MHz 16 3 264K 16 or 24 1 2512K 2 16 Yes


71721 3 200 MHz 16 3 264K 16 or 24 1 2512K 2 16 Yes
71624* 2 200 MHz 16 34 5128192 16 34 5128192 2 No
71641 1 or 2 3.6 or 1.8 GHz 12 1 or 2 4, 8 or 16 16 None None None No
71741 1 or 2 3.6 or 1.8 GHz 12 1 or 2 4, 8 or 16 16 None None None No
71651 2 500/400 MHz 12/14 2 2128K 16 or 24 1 2512K 2 16 Yes
71751 2 500/400 MHz 12/14 2 2128K 16 or 24 1 2512K 2 16 Yes
71661 4 200 MHz 16 4 264K 16 or 24 None None None Yes
71662 4 200 MHz 16 32 168K 24 None None None No
71663 4 200 MHz 16 1100 None None None No
71664** 4 200 MHz 16 4 264K 16 or 24 None None None Yes
71671 None None None 4 21024K 4 16 No
71771 None None None 4 21024K 4 16 No

Notes: All products use Virtex-6 FPGAs except: 71721, 71741, 71751, and 71771 which use Virtex-7 FPGAs
* Adaptive relay performance ** Meets VITA 49.0 specification
Figure 27

The above chart shows the salient characteristics for Other information thats specific to each core is
Penteks SDR products with factory-installed IP cores. All included as well as an indication of the models that
of these products are available off-the-self and are in the include a DUC, an interpolation filter and output D/A. As
Pentek datasheets and catalogs. shown in the chart, many of these models include features
that are critical for beamforming and direction-finding
The chart provides information regarding the number
applications.
of input channels, maximum sampling frequency of their
A/Ds, and the number of bits. This information is followed All the models shown here are XMC modules. As with
by DDC characteristics such as number of DDC channels all Pentek SDR products, these models are also available
and the decimation range. in PCI Express, VPX, AMC, and CompactPCI formats.
For more information on these products, click on
the Product Selector below:

16
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Software-Defined Radio Handbook

FPGA Resources
Resources

FPGA Resource Comparison


Resource

Vir tex-II PPro


Virtex-II ro Vir tex-4
Virtex-4 Vir tex-5
Virtex-5 Vir tex-6
Virtex-6 Vir tex-7
Virtex-7
VP FX, LX, SX LX, SX LX, SX VX
Logic Cells 53K74K 55K110K 52K155K 128K314K 326K693K
Slices* 23K33K 24K49K 8K24K 20K49K 51K108K
CLB Flip-Flops 46K66K 48K98K 32K96K 160K392K 408K864K
Block RAM (kb) 4,1765,904 4,1766,768 4,7528,784 9,50425,344 27,00052,920
DSP Hard IP 18x18 Multipliers DSP48 DSP48E DSP48E DSP48E
DSP Slices 232328 96512 128640 4801,344 1,1203,600
Serial Gbit Transceivers N/A 020 1216 2024 2880
PCI Express Support N/A N/A N/A Gen 2 x8 Gen 2 x8, Gen 3 x8
User I/O 852996 576960 480680 600720 7001,000
*Virtex-II Pro and Virtex-4 Slices actually represent 2.25 Logic Cells;
*Virtex-5, Virtex-6 and Virtex-7 Slices actually represent 6.4 Logic Cells
Figure 28

The above chart compares the available resources in The Virtex-5 family LX devices offer maximum
the five Xilinx FPGA families that are used or have been logic resources, gigabit serial transceivers, and Ethernet
used in most of Pentek products. media access controllers. The SX devices push DSP
Virtex-II Pro: VP capabilities with all of the same extras as the LX.
Virtex-4: FX, LX and SX

Virtex-5: LX and SX
The Virtex-5 devices offer lower power dissipation,
Virtex-6: LX and SX
faster clock speeds and enhanced logic slices. They also
Virtex-7: VX
improve the clocking features to handle faster memory
and gigabit interfaces. They support faster single-ended
The Virtex-II family includes hardware multipliers and differential parallel I/O buses to handle faster
that support digital filters, averagers, demodulators peripheral devices.
and FFTsa major benefit for software radio signal
The Virtex-6 and Virtex-7 devices offer still higher
processing. The Virtex-II Pro family dramatically
density, more processing power, lower power consump-
increased the number of hardware multipliers and also
tion, and updated interface features to match the latest
added embedded PowerPC microcontrollers.
technology I/O requirements including PCI Express.
The Virtex-4 family is offered as three subfamilies Virtex-6 supports PCIe 2.0 and Virtex-7 supports PCIe 3.0
that dramatically boost clock speeds and reduce power
The ample DSP slices are responsible for the
dissipation over previous generations.
majority of the processing power of the Virtex-6 and
The Virtex-4 LX family delivers maximum logic and Virtex-7 families. Increases in operating speed from 500 MHz
I/O pins while the SX family boasts of 512 DSP slices in V-4, to 550 MHz in V-5, to 600 MHz in V-6, to
for maximum DSP performance. The FX family is a 900 MHz in V-7 and continuously increasing density
generous mix of all resources and is the only family to allow more DSP slices to be included in the same-size
offer RocketIO, PowerPC cores, and the newly added package. As shown in the chart, Virtex-6 tops out at an
gigabit Ethenet ports. impressive 1,344 DSP slices, while Virtex-7 tops out at
an even more impressive 3,600 DSP slices.

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Software-Defined Radio Handbook

Optical Resources
Resources

Optical Links Offer Many Benefits

Property Copper Optical


Interface Transceiver Cost Low High but dropping
PC Network Interface Cards Integrated in PC or laptop Usually optional at $100-$200
Power over Ethernet Supported at low cost Not possible
Data Rate 1 GHz >10 GHz
Cable Loss - 100 meters 94% 3%
Max Transmission Distance 100 m (cat 6) 300 m (multi-mode)
10 km (single mode)
EMI Susceptibility Risk Moderate Zero
EMI Radiation Risk Moderate Zero
Security / Eavesdropping Risk High Extremely Low
Termination Costs Low High
Cable Cost per Length High Low
Cable Weight per 1000 m 60 to 600 kg 6 kg
Fire Hazard Supports current flow if shorted Zero
Tensile Strength 25 pounds 100-250 pounds
Cleaning Requirements No Yes
Figure 29

One major shortcoming of copper cable is signal loss, Physically, optical cables are much smaller and lighter
which becomes a serious limitation for higher frequency than copper cables, especially important for weight-sensitive
signals and longer cable lengths. Across a span of 100 applications such as weapons, unmanned vehicles, and aircraft.
meters, optical cables can sustain data rates up to 100 times Optical cables will operate just as well when submerged in
higher than copper cable. seawater, and are completely immune to electrical shorting,
especially important where explosive vapors may be present.
Because copper cables radiate electromagnetic energy,
To ease installation through conduits and passages, optical
eavesdropping on network cables is a major security concern,
cables have smaller diameters and can withstand up to ten
not only for military and government customers, but
times more pulling tension than copper cables.
also for corporations, banks, and financial institutions.
Advanced signal sniffers in vehicles and briefcases are Driven by huge commercial markets for data servers,
hard to detect and restrict. Optical cables are extremely storage networks, telecom systems, and home or office
difficult to tap without damaging the cable, resulting internet and entertainment systems, optical interfaces are
in immediate detection. replacing older copper connections for good reasons: cost
and performance. As the use of optical cables becomes
Signals flowing in copper cables are also susceptible
more widespread, the cost per length can be much
to contamination from nearby sources of electromagnetic
lower than copper cables that depend on commodity
radiation, such as antennas, generators, and motors. This
metal pricing. As is often the case, industrial, military
is critical for military and commercial aircraft and ships,
and government embedded systems are now taking
as well as manned or unmanned vehicles, which are often
advantage of the many benefits of this rapidly advanc-
packed with dozens of different electronic payloads. Optical
ing commercial technology.
cables are completely immune to EMI.

18
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Software-Defined Radio Handbook

Optical Resources
Resources

Optical Cables

Hundreds of different types of optical cable connec-


tors exist in the market, each addressing specific applica-
tions and environments. The challenge is connecting the
ends of two optical cables to retain the maximum fidelity of
the light interface, in spite of human factors, tolerances,
contamination, and environments. Special tools and kits
for cleaning the ends of each optical fibre are essential
for reliable operation.

Optical TTransceivers
ransceivers

Coupling electrical signals to light signals for transmis-


sion through optical cables requires optical transceivers. Most
systems require full-duplex operation for each optical link to
support flow-control and error correction. A pair of optical
fibers, often bonded together in the same cable, supports
transmit and receive data flowing in opposite directions.
Figure 30
Although several analog light modulation schemes (includ-
The Pentek Model 52611 Quad SerialFPDP 3U VPX module ing AM and FM) have been used in the past, now almost all
supports four full-duplex LC optical cables for connections transceivers use digital modulation. Optical emitters simply
between chassis, each operating at over 400 MB/sec
translate the digital logic levels into on/off modulation of the laser
light beam, while the detectors convert the modulated light back
into digital signals. This physical layer interface for transporting
An optical cable is a waveguide for propagating light 0s and1s is capable of supporting any protocol.
through an optical fibre. It consists of a central core clad
with a dielectric material having a higher index of The latest transceivers use laser emitters to support
refraction than the core to ensure total internal reflec- data rates to 100 Gbits/sec and higher, and each genera-
tion. Optical cables use either multi-mode or single- tion steadily reduces the power, size and cost of devices.
mode transmission. Different technologies are required for emitters and detectors,
but both are often combined in a single product to provide
Multi-mode cables accept light rays entering the core full-duplex operation.
within a certain angle of the axis. They travel down the
cable by repeatedly reflecting off the dielectric boundary Optical transceivers thus provide a physical layer
between the core and the cladding. The core diameters interface between optical cables and the vast array of
are typically 50 or 62.5 mm, and the wavelength of light electrical multi-gigabit serial ports found on processors,
is typically 850 nm. FPGAs, and network adapters. As a result, optical transceiv-
ers are transparent to the protocols they support, making
Single-mode cables propagate light as an electromag- them appropriate for any high-speed serial digital link.
netic wave operating in a single transverse mode straight
down the fibre using typical wavelengths of 1310 and Electrical signals of the optical transceivers connect
1550 nm. The core diameter must be no greater than ten to the end point device, which must then handle clock
times the light wavelength, typically 8 to 10 m. Although encoding and recovery, synchronization, and line balance
single-mode cables can carry signals over lengths 10 to at the physical layer. Data link layer circuitry establishes
100 times longer than multi-mode, the transceivers are framing so that data words can be sent and received across
more expensive. the channel.

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Software-Defined Radio Handbook

Optical Resources
Resources

Choosing the Right Optical PProtocol


rotocol VITA 49.0: VIT
VITA AR
VITA adio TTranspor
Radio ranspor
ransportt (VRT) Standard

Protocols define the rules and features supported by each


type of system link, ranging from simple transmission of raw
data to sophisticated multi-processor support for distributed
networks, intelligent routing, and robust error correction. Of
course, heavier protocols invariably mean less efficient data
transfers and increased latency. Generally, it is best to use the
simplest protocol that satisfies the system requirements.
Figure 31
As an example of a lightweight protocol, Aurora for Xilinx
FPGAs features on-board link-layer engines and high-speed New extensions to the VITA VRT Protocol define standardized
packets for control and status of radio receiver and transmitter
serial transceivers. Aurora is intended primarily for point-to- equipment and digitized receive and transmit signal
point connectivity for sending data between two FPGAs. It payload packets for added flexibility
includes 8b/10b or 64b/66b channel coding to balance the
transmission channel, and supports single- or full-duplex
operation. Aurora handles virtually any word length and allows Approved as an ANSI standard in 2007, VITA 49.0
multiple serial lanes to be bonded into a single logical channel, defines standardized packets for connecting software
aggregating single lane bit rates for higher data throughput. radio systems for communications, radar, telemetry,
Data rates for each serial lane can be 12.5 Gbits/sec or higher. direction finding, and other applications. The original
Extremely simple and with minimal overhead, Aurora is very specification addressed only receiver functions. Receive
efficient in linking data streams between multiple FPGAs signal data packets deliver digitized payload data, a
within a module, or between modules across a backplane. precise time stamp, and identifiers for each channel and
signal. Context packets include operating parameters of
Stepping up in complexity is the SerialFPDP protocol the receiver including tuning frequency, bandwidth,
defined under VITA 17.1 It addresses several important sampling rate, gain, antenna orientation, speed, heading,
needs of embedded systems including flow control to avoid etc. One notable shortcoming of the original specifica-
data overruns, and copy mode to allow one node to receive tion was its inability to control the receiver.
data and also forward it on to another node. The copy/loop
mode supports a ring of multiple nodes eventually complet- VITA 49.2, a new extension to VRT now in ballot-
ing a closed loop. The nominal data rate on each lane is ing, adds control packets for delivering operational
2.5 Gbits/sec, but advances in device technology now support parameters to all aspects of the radio equipment, as well
rates over twice that speed. as support for transmitters. The new stimulus packets
contain streaming digital samples of signals to be transmit-
Infiniband defines a flexible, low-latency, point-to- ted. Other new packets, called capabilities packets, inform the
point interconnect fabric for data storage and servers with host control system of the available hardware in the radio
current rates of 14 Gbits/sec, moving up to 50 Gbits/sec in along with the allowed range of parameters for control.
the next few years. Channel speeds can be boosted by forming Lastly, spectrum packets from the receiver deliver spectral
logical channels by bonding 4 or 12 lanes. information to help simplify spectral survey and energy
The venerable Ethernet protocol still dominates detection operations required by the control system.
computer networks, with 10GbE now commonly supported With this latest extension, VRT provides a standard-
by a vast range of computers, switches, and adapters. Even ized protocol for controlling and configuring all aspects
though Ethernet suffers from high overhead, making it of a software-radio transceiver. One major objective is
somewhat cumbersome for high-data rate low-latency enabling a common radio hardware platform to handle a
applications, its ubiquitous presence virtually assures wide range of applications simply by implementing new
compatibility. host software algorithms that exploit VRT protocols to
achieve the required modes of operation.

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Software-Defined Radio Handbook

Optical Resources
Resources

Optical Inter faces for VPX


Interfaces

Figure 32

Although optical interfaces using various connectors cable connects to a small VCSEL laser emitter module
and cable types have been deployed in embedded systems and the other connects to a detector module.
for years, most of them use front panel connections. This
Figure 32 shows the industrys first implementation of
can be a maintenance issue and is often not permitted in
the emerging VITA 66.4 standard, the Pentek Model 5973
conduction-cooled systems.
3U VPX Virtex-7 FMC carrier. Here the electrical interfaces
The VITA 66 Fiber Optic Interconnect group has of the FireFly emitter and detector modules are connected
developed a set of standards that bridge optical connections directly to the GTX serial transceiver pins of the Virtex-7
directly through the VPX backplane connector. The first FPGA. Today, FireFly transceivers are rated for 14 Gbits/sec
three are variants for 3U and 6U systems and are based on with 28 Gbits/sec versions coming soon. With the 5973
MT, ARINC 801 Termini, and Mini-Expanded Beam operating at nominal data rates of 10 Gbits/sec through each
optical connector technology, respectively. optical fibre using Aurora protocol, the backplane throughput
is 12 GB/sec, simultaneously in both directions.
The metal housings are physically dimensioned to replace
one or more of the standard MultiGig RT-2 VPX bladed copper The first version of this product uses multi-mode
connectors. The high-density MT variant defined in VITA 66.1 transceivers and cable to support cable lengths of 100 meters
provides the highest density of the three, with up to 12 or 24 pairs or more. Single-mode transceivers will extend the distance to
of optical fibers, while VITA 66.2 and 66.3 each provide 2 pairs. several kilometers. A wide range of MT optical cables and
connector products allow board-to-board connections across
A fourth standard soon to be released, VITA 66.4, uses
the backplane, and backplane-to-chassis connections for
the MT ferrule but with a metal housing half the size of
external MTP cables to remotely located systems.
VITA 66.1, thus occupying only half of the 3U VPX P2
connector position. The 12 GB/sec VITA 66.4 optical interface complements
the 8 GB/sec Gen 3 x8 copper PCIe interface on VPX P1,
To simplify implementation, Samtec offers its FireFlyTM
offering plenty of I/O for demanding applications. System
Micro Fly-Over system. It consists of 12 pairs of optical
engineers can now choose between optical and copper
fibers installed in an MT ferrule. One 12-lane optical flat
links to solve high-data rate connectivity requirements.

21
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Software-Defined Radio Handbook

Products

PMC, XMC, PCI Express, OpenVPX, AMC, FMC, and CompactPCI


Sof tware R
Software adio and Suppor
Radio ting PProducts
Supporting roducts

x8 PCI Express Board


AMC Board
3U VPX Boards
XMC Module COTS and Rugged

6U CompactPCI
Board

PMC/XMC FMC I/O Module 6U VPX


Module Board
FMC Carrier

Figure 33

The Pentek family of board-level software radio All Pentek software radio products include multiboard
products is the most comprehensive in the industry. All synchronization that facilitates the design of multichannel
of these products are available in several formats to systems with synchronous clocking, gating and triggering.
satisfy a wide range of requirements: PMC/XMC,
Penteks comprehensive software support includes
PCI Express, 3U and 6U VPX, AMC, FMC, 3U and 6U
the ReadyFlow Board Support Package, the
CompactPCI.
GateFlow FPGA Design Kit and high-performance
Software radio products are supported by clock factory-installed IP cores that expand the features and
synthesizer, synchronizer and distribution boards. These range of many Pentek software radio products. In
products are also available in the same formats as the addition, Pentek high-speed recording systems are
software radio products. supported with SystemFlow recording software that
features a Windows-based graphical user interface.
In addition to their commercial versions, many of
the above products are available in ruggedized versions In addition to the product overviews presented in
up to and including conduction-cooled. the pages that follow, active links to their datasheets and
the datasheets of similar products on Penteks website,
are included with each product.

22
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Software-Defined Radio Handbook

Products

Cobalt & Onyx XMC Models


Cobalt

Onyx
Model A/D Converters D/A Converters IP or Other I/O
# Type # Type Type
71x20 3 200 MHz / 16-bit 2 800 MHz / 16-bit
71x21 3 200 MHz / 16-bit 2 800 MHz / 16-bit DDC Interp Sum
71x24 3 200 MHz / 16-bit 2 800 MHz / 16-bit Adaptive Relay
71x60 4 200 MHz / 16-bit
71x61 4 200 MHz / 16-bit DDC Sum
71x62 4 200 MHz / 16-bit DDC
71x63 4 200 MHz / 16-bit GSM Channelizer
71x64 4 200 MHz / 16-bit DDC VITA -49
71x90 2 200 MHz / 16-bit .925 2.175 GHz L-Band Tuner

71x50-014 2 400 MHz / 14-bit 2 800 MHz / 16-bit


71x50 2 500 MHz / 12-bit 2 800 MHz / 16-bit
71x51-014 2 400 MHz / 14-bit 2 800 MHz / 16-bit DDC Interp Sum
71x51 2 500 MHz / 12-bit 2 800 MHz / 16-bit DDC Interp Sum
71x30 1 1 GHz / 12-bit 1 1 GHz / 16-bit
1 3.6 GHz / 12-bit
71x40 2 1.8 GHz / 12-bit
1 3.6 GHz / 12-bit
71x41 2 1.8 GHz / 12-bit DDC
71x70 4 1.25 GHz / 16-bit
71x71 4 1.25 GHz / 16-bit Interp
71x10 32 pair LVDS I/O
71x11 Quad Serial FPDP

Notes By changing the 1st and 2nd digits to 52, the 52xxx
The chart above lists only the 71xxx XMC products that 3U VPX products offer the same resources as the table.
form the basis of all Cobalt and Onyx product lines. By changing the 1st and 2nd digits to 53, the 53xxx
By changing the 2nd digit of the model number to 3U VPX products offer a crossbar switch to the
2, the 72xxx 6U cPCI products offer the same resources backplane.
as the table above, plus an extra available XMC site. By changing the 1st and 2nd digits to 56, the 56xxx AMC
By changing the 2nd digit to 3, the 73xxx 3U cPCI products offer the same resources as shown in the table.
products offer the same resources as the table above. By changing the 1st and 2nd digits to 57, the 57xxx
By changing the second digit to 4 the 74xxx 6U cPCI 6U VPX products offer the same resources, plus an
products offer twice the resources shown in the table. extra available XMC site.
By changing the 2nd digit to 8 the 78xxx PCIe products By changing the 1st and 2nd digits of the model number
offer the same resources as the products in the table. to 58, the 58xxx 6U VPX products offer twice the
resources shown in the table above.
Figure 34

23
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Software-Defined Radio Handbook

Products

VPX FFamilies
amilies for Cobalt PProducts
roducts VPX FFamilies
amilies for Onyx PProducts
roducts

VPX Family Comparison VPX Family Comparison


52xxx 53xxx 52xxx 53xxx

Form Factor 3U VPX Form Factor 3U VPX

# of XMCs One XMC # of XMCs One XMC

Crossbar Switch No Yes Crossbar Switch No Yes

PCIe path VPX P1 VPX P1 or P2 PCIe path VPX P1 VPX P1 or P2

PCIe width x4 x8 PCIe width x4 x4 or x8

Option -104 path 20 pairs on VPX P2 Option -104 path 24 pairs on VPX P2 20 pairs on VPX P2

Two x4 or one x8 Two x4 or one x8 Two x4 or one x8 Two x4 or one x8


Option -105 path Option -105 path
on VPX P1 on VPX P1 or P2 on VPX P1 on VPX P1 or P2

Lowest Power Yes No Lowest Power Yes No

Lowest Price Yes No Lowest Price Yes No

Figure 35 Figure 36

Pentek offers two families of Cobalt 3U VPX Pentek offers two families of Onyx 3U VPX
products: the 52xxx and the 53xxx. For more information products: the 52xxx and the 53xxx. For more information
on a 52xxx or a 53xxx product, please refer to the product on a 52xxx or a 53xxx product, please refer to the product
descriptions in the pages that follow. The table above descriptions in the pages that follow. The table above
provides a comparison of the main features of the families. provides a comparison of the main features of the families.
Cobalt products utilize the Xilinx Virtex-6 FPGA. Onyx products utilize the Xilinx Virtex-7 FPGA.

24
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Software-Defined Radio Handbook

Products

3- Channel 200 MHz A/D, DUC, 2-


3-Channel Channel 800 MHz D/A, Vir
2-Channel tex-6 FPGA
Virtex-6

Model 71620 - XMC

RF In RF In RF In RF Out RF Out

RF RF RF RF RF
XFORMR XFORMR XFORMR XFORMR XFORMR
Sample Clk /
Reference Clk In A/D
TIMING BUS Clock/Sync
GENERATOR Bus 200 MHz 200 MHz 200 MHz 800 MHz 800 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT D/A 16-BIT D/A
TTL Gate / Trig Clock / Sync /
DIGITAL
TTL Sync / PPS Gate / PPS
UPCONVERTER
D/A
Sample Clk Clock/Sync 16 16 16
Reset Bus 32
Gate A/D
Gate D/A
Sync / PPS A/D
Sync / PPS D/A VIRTEX-6 FPGA
VCXO
Timing Bus LX130T, LX240T or SX315T

GTX GTX GTX LVDS

16 16 16 16 16 16 16 16 16
8X 4X 4X 40
QDRII+ QDRII+ QDRII+ QDRII+ Config
SRAM SRAM SRAM SRAM FLASH
Model 71620 8 MB 8 MB 8 MB 8 MB 64 MB
XMC QDRII+ option 150 QDRII+ option 160 x8 PCIe Gigabit FPGA
DDR3 option 155 DDR3 option 165 Serial I/O GPIO
(option 105) (option 104)
DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
512 MB 512 MB 512 MB 512 MB P15 P16 P14
XMC XMC PMC
Memory Banks 1 & 2 Memory Banks 3 & 4

Figure 37

Model 71620 is a member of the Cobalt family of Each member of the Cobalt family is delivered
high-performance XMC modules based on the Xilinx with factory-installed applications ideally matched to the
Virtex-6 FPGA. A multichannel, high-speed data boards analog interfaces. The 71620 factory-installed
converter, it is suitable for connection to HF or IF ports functions include an A/D acquisition and a D/A waveform
of a communications or radar system. Its built-in data playback IP module. In addition, IP modules for either
capture and playback features offer an ideal turnkey solution. DDR3 or QDRII+ memories, a controller for all data
It includes three 200 MHz, 16-bit A/Ds, a DUC with clocking and synchronization functions, a test signal
two 800 MHz, 16-bit D/As and four banks of memory. generator and a PCIe interface complete the factory-
In addition to supporting PCI Express Gen. 2 as a installed functions.
native interface, the Model 71620 includes general
Multiple 71620s can be driven from the LVPECL
purpose and gigabit serial connectors for application-
bus master, supporting synchronous sampling and sync
specific I/O .
functions across all connected modules. The architecture
The Pentek Cobalt architecture features a Virtex-6 supports up to four memory banks which can be configured
FPGA. All of the boards data and control paths are acces- with all QDRII+ SRAM, DDR3 SDRAM, or combinations.
sible by the FPGA, enabling factory-installed functions
Versions of the 71620 are also available as an x8 PCIe
including data multiplexing, channel selection, data packing,
half-length board (Model 78620), 3U VPX (Models 52620
gating, triggering and memory control. The Cobalt architec-
and 53620), 6U VPX (Models 57620 and 58620 dual
ture organizes the FPGA as a container for data processing
density), AMC (Model 56620), 6U cPCI (Models 72620
applications where each function exists as an intellec-
and 74620 dual density), and 3U cPCI (Model 73620).
tual property (IP) module.

25
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

3- Channel 200 MHz A/D, DUC, 2-


3-Channel Channel 800 MHz D/A, Vir
2-Channel tex-7 FPGA
Virtex-7

Model 71720 - XMC


717

RF In RF In RF In RF Out RF Out

RF RF RF RF RF
XFORMR XFORMR XFORMR XFORMR XFORMR
Sample Clk /
Reference Clk In A/D
TIMING BUS Clock/Sync
GENERATOR Bus 200 MHz 200 MHz 200 MHz 800 MHz 800 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT D/A 16-BIT D/A
TTL Gate / Trig Clock / Sync /
DIGITAL
TTL Sync / PPS Gate / PPS
UPCONVERTER
D/A
Sample Clk Clock/Sync 16 16 16
Reset Bus 32
Gate A/D
Gate D/A
Sync / PPS A/D
Sync / PPS D/A VIRTEX-7 FPGA
VCXO
Timing Bus VX330T or VX690T

GTX GTX GTX LVDS

CONFIG FPGA 32 32 32 32
FLASH PCIe 4X 4X 48
Config Gen. 3 x8
1 GB
Model 71720 Bus DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
XMC GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
MANAGER
Gigabit FPGA
PCIe Serial I/O GPIO
Gen. 3 x8 (option 105) (option 104)
P15 P16 P14
XMC XMC PMC

Figure 38

Model 71720 is a member of the Onyx family of Each member of the Onyx family is delivered with
high-performance XMC modules based on the Xilinx factory-installed applications ideally matched to the boards
Virtex-7 FPGA. A multichannel, high-speed data converter, analog interfaces. The 71720 factory-installed functions
it is suitable for connection to HF or IF ports of a include three A/D acquisition and a D/A waveform
communications or radar system. Its built-in data playback IP modules for simplifying data capture and
capture and playback features offer an ideal turnkey data transfer. IP modules for DDR3 SDRAM memories, a
solution. It includes three 200 MHz, 16-bit A/Ds, a DUC controller for all data clocking and synchronization func-
with two 800 MHz, 16-bit D/As and four banks of tions, a test signal generator, and a PCIe interface
memory. In addition to supporting PCI Express Gen. 3 as complete the factory-installed functions.
a native interface, the Model 71720 includes general-
Multiple 71720s can be driven from the LVPECL
purpose and gigabit-serial connectors for application-
bus master, supporting synchronous sampling and sync.
specific I/O.
Versions of the 71720 are also available as an x8 PCIe
The Pentek Onyx architecture features a Virtex-7
half-length board (Model 78720), 3U VPX (Models 52720
FPGA. All of the boards data and control paths are
and 53720), 6U VPX (Models 57720 and 58720 dual
accessible by the FPGA, enabling factory-installed
density), AMC (Model 56720), 6U cPCI (Models 72720
functions including data multiplexing, channel selection,
and 74720 dual density), and 3U cPCI (Model 73620).
data packing, gating, triggering and memory control. The
Cobalt architecture organizes the FPGA as a container for GateXpress is a sophisticated configuration manager
data processing applications where each function exists for loading and reloading the Virtex-7 FPGA. More
as an intellectual property (IP) module. information is available in the next page.

26
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

GateXpress for FPGA-PCIe Configuration Management


FPGA-PCIe

ONYX: VIRTEX-7 FPGA


VX330T or VX690T

GTX GTX GTX LVDS

FPGA 32 32 32 32
Config 8X 4X 4X 40 Cobalt
Bus 48 Onyx
DDR3 DDR3 DDR3 DDR3
CONFIG GATEXPRESS PCIe SDRAM SDRAM SDRAM SDRAM
FLASH CONFIGURATION Option Option 1 GB 1 GB 1 GB 1 GB
1 GB MANAGER -105 -104
Serial FPGA
I/O GPIO
PCIe
P15 P16 P14
XMC XMC PMC

Figure 39

The Onyx architecture includes GateXpress, a sophisti- The second option is for applications where the
cated FPGA-PCIe configuration manager for loading and FPGA image must be loaded directly through the PCIe
reloading the FPGA. At power up, GateXpress immediately interface. This is important in security situations where
presents a PCIe target for the host computer to discover, there can be no latent user image left in nonvolatile
effectively giving the FPGA time to load from FLASH. memory when power is removed. In applications where
This is especially important for larger FPGAs where the the FPGA IP may need to change many times during
loading times can exceed the PCIe discovery window, the course of a mission, images can be stored on the host
typically 100 msec on most PCs. computer and loaded through PCIe as needed.
The boards configuration FLASH can hold four The third option, typically used during development,
FPGA images. Images can be factory-installed IP or allows the user to directly load the FPGA through JTAG
custom IP created by the user, and programmed into the using Xilinx iMPACT.
FLASH via JTAG using Xilinx iMPACT or through the
In all three FPGA loading scenarios, GateXpress
boards PCIe interface. At power up the user can choose
handles the hardware negotiation simplifying and stream-
which image will load based on a hardware switch setting.
lining the loading task. In addition, GateXpress preserves
Once booted, GateXpress allows the user three the PCIe configuration space allowing dynamic FPGA
options for dynamically reconfiguring the FPGA with a reconfiguration without needing to reset the host
new IP image. The first is the option to load an alternate computer to rediscover the board. After the reload, the
image from FLASH through software control. The user host simply continues to see the board with the expected
selects the desired image and issues a reload command. device ID.

27
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

3- Channel 200 MHz A/D, DUC, 2-


3-Channel Channel 800 MHz D/A, Installed IP Cores, Vir
2-Channel tex-6 FPGA
Virtex-6

Model 71621- XMC


71621-

from from from to


A/D Ch 1 A/D Ch 2 A/D Ch 3 D/A

D/A loopback
TEST
SIGNAL
INPUT MULTIPLEXER GENERATOR

DDC DDC DDC INTERPOLATOR


DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 2 TO 65536
POWER POWER POWER IP CORE
METER & METER & METER &
THRESHOLD THRESHOLD THRESHOLD DATA UNPACKING
DETECT DETECT DETECT & FLOW CONTROL
MUX
DDC CORE DDC CORE DDC CORE
DATA PACKING & DATA PACKING & DATA PACKING & MUX
FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL MEMORY
METADATA METADATA METADATA
GENERATOR MUX GENERATOR MUX CONTROL
to to to GENERATOR MUX
Mem Mem Mem to LINKED-LIST
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Bank 3 LINKED-LIST Mem DMA ENGINE
DMA ENGINE DMA ENGINE DMA ENGINE
Bank 4 D/A
A/D A/D A/D WAVEFORM
ACQUISITION ACQUISITION ACQUISITION PLAYBACK
Model 71621 IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE

XMC

AURORA sum out


GIGABIT S VIRTEX-6 FPGA DATAFLOW DETAIL PCIe INTERFACE
SERIAL SUMMER
INTERFACE sum in
BEAMFORMER CORE
4X 4X 8X
to next from previous
board board PCIe

Figure 40

Model 71621 is a member of the Cobalt family of high- the A/D sampling frequency. Each DDC can have its
performance XMC modules based on the Xilinx Virtex-6 own unique decimation setting, supporting as many as
FPGA. A multichannel, high-speed data converter based on three different output bandwidths for the board. Decima-
the Model 71620 described in the previous page, it includes tions can be programmed from 2 to 65,536 providing a
factory-installed IP cores to enhance the performance of the wide range to satisfy most applications.
71620 and address the requirements of many applications.
The 71621 also features a complete beamforming
The 71621 factory-installed functions include three A/D subsystem. Each DDC core contains programable I & Q
acquisition and one D/A waveform playback IP modules. phase and gain adjustments followed by a power meter
Each of the three acquisition IP modules contains a that continuously measures the individual average power
powerful, programmable DDC IP core. The waveform output. The power meters present average power measure-
playback IP module contains an interpolation IP core, ideal ments for each DDC core output in easy-to-read registers. A
for matching playback rates to the data and decimation threshold detector automatically sends an interrupt to
rates of the acquisition modules. IP modules for either the processor if the average power level of any DDC
DDR3 or QDRII+ memories, a controller for all data core falls below or exceeds a programmable threshold.
clocking and synchronization functions, a test signal
Versions of the 71621 are also available as an x8 PCIe half-
generator, an Aurora gigabit serial interface, and a PCIe
length board (Model 78621), 3U VPX (Models 52621 and
interface complete the factory-installed functions.
53621), 6U VPX (Models 57621 and 58621 dual density),
Each DDC has an independent 32-bit tuning AMC (Model 56621), 6U cPCI (Models 72621 and
frequency setting that ranges from DC to s, where s is 74621 dual density), and 3U cPCI (Model 73621).

28
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

3- Channel 200 MHz A/D, DUC, 2-


3-Channel Channel 800 MHz D/A, Installed IP Cores, Vir
2-Channel tex-7 FPGA
Virtex-7

Model 56721- AMC

from from from to


A/D Ch 1 A/D Ch 2 A/D Ch 3 D/A

D/A loopback
TEST
SIGNAL
INPUT MULTIPLEXER GENERATOR

DDC DDC DDC INTERPOLATOR


DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 2 TO 65536
POWER POWER POWER IP CORE
METER & METER & METER &
THRESHOLD THRESHOLD THRESHOLD DATA UNPACKING
DETECT DETECT DETECT & FLOW CONTROL
MUX
DDC CORE DDC CORE DDC CORE
DATA PACKING & DATA PACKING & DATA PACKING & MUX
FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL MEMORY
METADATA METADATA METADATA
GENERATOR MUX GENERATOR MUX CONTROL
to to to GENERATOR MUX
Mem Mem Mem to LINKED-LIST
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Bank 3 LINKED-LIST Mem DMA ENGINE
DMA ENGINE DMA ENGINE DMA ENGINE
Bank 4 D/A
A/D A/D A/D WAVEFORM
ACQUISITION ACQUISITION ACQUISITION PLAYBACK Model 56721
IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE AMC

AURORA sum out


GIGABIT S VIRTEX-7 FPGA DATAFLOW DETAIL PCIe INTERFACE
SERIAL SUMMER
INTERFACE sum in
BEAMFORMER CORE
4X 4X
to next from previous
8X See page 27
board board PCIe

Figure 41

Model 56721 is a member of the Onyx family of high- the A/D sampling frequency. Each DDC can have its
performance AMC modules based on the Xilinx Virtex-7 own unique decimation setting, supporting as many as
FPGA. A multichannel, high-speed data converter based on three different output bandwidths for the board. Decima-
the Model 71720 described previously, it includes factory- tions can be programmed from 2 to 65,536 providing a
installed IP cores to enhance the performance of the 71720 wide range to satisfy most applications.
and address the requirements of many applications.
The 56721 also features a complete beamforming
The 56721 factory-installed functions include three A/D subsystem. Each DDC core contains programable I & Q
acquisition and one D/A waveform playback IP modules. phase and gain adjustments followed by a power meter
Each of the three acquisition IP modules contains a that continuously measures the individual average power
powerful, programmable DDC IP core. The waveform output. The power meters present average power measure-
playback IP module contains an interpolation IP core, ideal ments for each DDC core output in easy-to-read registers. A
for matching playback rates to the data and decimation threshold detector automatically sends an interrupt to
rates of the acquisition modules. IP modules for either the processor if the average power level of any DDC
DDR3 or QDRII+ memories, a controller for all data core falls below or exceeds a programmable threshold.
clocking and synchronization functions, a test signal
Versions of the 56721 are also available as an XMC
generator, an Aurora gigabit serial interface, and a PCIe
module (Model 71721), x8 PCIe board (Model 78721),
interface complete the factory-installed functions.
3U VPX (Models 52721 and 53721), 6U VPX (Models
Each DDC has an independent 32-bit tuning 57721 and 58721 dual density), 6U cPCI (Models 72721
frequency setting that ranges from DC to s, where s is and 74721 dual density), and 3U cPCI (Model 73721).

29
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

Dual- Channel 34-Signal Adaptive IF R


Dual-Channel elay
elay,, Installed IP Cores, Vir
Relay tex-6 FPGA
Virtex-6

Model 52624 - 3U VPX


52624

DDC INPUT OUTPUT DUC


1 GAIN 1 GAIN 1 1

SUMMATION 1
200 MHz 800 MHz IF 1
IF 1 INTERP
16-BIT 16-BIT
In X4 Out
A/D DDC INPUT OUTPUT DUC D/A

OUTPUT MULTIPLEXER
INPUT MULTIPLEXER

2 GAIN 2 GAIN 2 2

DDC INPUT OUTPUT DUC


3 GAIN 3 GAIN 3 3

SUMMATION 2
IF 2 200 MHz 800 MHz IF 2
16-BIT INTERP 16-BIT
In X4 Out
A/D D/A
DDC INPUT OUTPUT DUC
34 GAIN 34 GAIN 34 34

TRANSMIT DMA
A/D CONTROLLER
Sample Clk /
Reference Clk In Clock/Sync Bus
TIMING BUS RECEIVE DMA PCIe
TTL Gate / Trig GENERATOR D/A CONTROLLER INTERFACE
Model 52624 COTS
TTL Sync / PPS Clock/Sync Bus and rugged
Gate A/D Triggering/
Clock / Sync /
PCIe
Gate D/A To All STATUS &
Gen. 1 x8
Sync / PPS A/D Gate / PPS VCXO Sections CONTROL
Sync / PPS D/A
VPX-P1
VPX BACKPLANE

Figure 42

Model 52624 is a member of the Cobalt family of A PCIe Gen 1 system interface supports control, status
high-performance 3U VPX boards based on the Xilinx and data transfers.
Virtex-6 FPGA. As an IF relay, it accepts two IF analog
The Model 52624 digitizes two analog IF inputs
input channels, modifies up to 34 signals, and then delivers
using two 200 MHz 16-bit A/D converters. The band-
them to two analog IF outputs. Any signal within each
width of each IF signal can be up to 80 MHz, and may
IF band can be independently enabled or disabled,
contain multiple signals, each centered at a different
and changed in both frequency and amplitude as it passes
frequency. An array of 34 DDCs can be independently
through the board.
programmed to translate any signal to baseband and
The 52624 supports many useful functions for both then bandlimit the signal as required. DDC tuning frequency
commercial and military communications systems including is programmable from 0 Hz to the A/D sample rate. Output
signal drop/add/replace, frequency shifting and hopping, bandwidth is programmable from around 20 kHz to 312 kHz
amplitude equalization, and bandwidth consolidation. for a sample rate of 200 MHz. Each DDC can indepen-
Applications include countermeasures, active tracking and dently source IF data from either of the two A/Ds.
monitoring, channel security, interception, adaptive
Versions of the 52624 are also available as a different
spectral management, jamming, and encryption.
3U VPX (Model 53624), 6U VPX (Models 57624 and
The Pentek Cobalt product family features the Virtex-6 58624 with dual density), XMC module (Model 71624),
FPGA. All of the boards data converters, interfaces and an x8 PCIe board (Model 78624), AMC (Model 56624),
control lines are connected to the FPGA, which performs 6U cPCI (Models 72624 and 74624 dual density), and 3U
the data-routing and DSP functions for the adaptive relay. cPCI (Model 73624).

30
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

1 GHz A/D, 1 GHz D/A, Vir tex-6 FPGA


Virtex-6

Model 78630 - PCIe

RF In RF Out

RF RF
Sample Clk / XFORMR XFORMR
Reference Clk In
TTL
PPS/Gate/Sync TIMING BUS
A/D Clock/Sync Bus 1 GHz
GENERATOR
Gate In 12-BIT A/D
Sync In Clock / Sync / 1 GHz
Gate / PPS 16-BIT D/A
A/D Sync Bus D/A Clock/Sync Bus

Gate In 12
16
Sync In
D/A Sync Bus
VIRTEX-6 FPGA
LX130T, LX240T or SX315T
VCXO

LVDS GTX GTX GTX

16 16 16 16 16 16 16 16 16
40 8X 4X 4X
Model 78630
DDR3 DDR3 DDR3 DDR3 Config
SDRAM SDRAM SDRAM SDRAM FLASH x8 PCIe
512 MB 512 MB 512 MB 512 MB 64 MB
Optional Optional
Memory Banks 1 & 2 Memory Banks 3 & 4 FPGA x8 PCIe Serial
DDR3 option 155 DDR3 option 165
GPIO I/O
QDRII+ QDRII+
SRAM SRAM Dual 4X
8 MB 8 MB 68-pin Serial
Header Conn
QDRII+ option 150
x8 PCI Express
Figure 43

Model 78630 is a member of the Cobalt family of high- Each member of the Cobalt family is delivered
performance PCIe boards based on the Xilinx Virtex-6 with factory-installed applications ideally matched to the
FPGA. A high-speed data converter, it is suitable for boards analog interfaces. The 78630 factory-installed
connection to HF or IF ports of a communications or radar functions include an A/D acquisition and a D/A waveform
system. Its built-in data capture and playback features offer playback IP module. In addition, IP modules for either
an ideal turnkey solution as well as a platform for develop- DDR3 or QDRII+ memories, a controller for all data
ing and deploying custom FPGA processing IP. It includes clocking and synchronization functions, a test signal
1 GHz, 12-bit A/D, 1 GHz, 16-bit D/A converters and generator and a PCIe interface complete the factory-
four banks of memory. In addition to supporting PCI installed functions.
Express Gen. 2 as a native interface, the Model 78630
Multiple 78630s can be driven from the LVPECL bus
includes optional general purpose and gigabit serial card
master, supporting synchronous sampling and sync functions
connectors for application- specific I/O protocols.
across all connected boards. The architecture supports up to
The Pentek Cobalt architecture features a Virtex-6 four memory banks which can be configured with all
FPGA. All of the boards data and control paths are acces- QDRII+ SRAM, DDR3 SDRAM, or as combinations.
sible by the FPGA, enabling factory-installed functions
Versions of the 78630 are also available as an XMC
including data multiplexing, channel selection, data packing,
module (Model 71630), 3U VPX (Models 52630 and
gating, triggering and memory control. The Cobalt architec-
53630), 6U VPX (Models 57630 and 58630 with dual
ture organizes the FPGA as a container for data process-
density), AMC (Model 56630), 6U cPCI (Models 72630
ing applications where each function exists as an intellec-
and 74630 with dual density), and 3U cPCI (Model 73630).
tual property (IP) module.

31
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

1 GHz A/D, 1 GHz D/A, Vir tex-7 FPGA


Virtex-7

Model 71730 - XMC

RF In RF Out

RF RF
Sample Clk / XFORMR XFORMR
Reference Clk In
TTL
PPS/Gate/Sync TIMING BUS
A/D Clock/Sync Bus 1 GHz
GENERATOR
Gate In 12-BIT A/D
Sync In Clock / Sync / 1 GHz
Gate / PPS 16-BIT D/A
A/D Sync Bus D/A Clock/Sync Bus

Gate In 12
16
Sync In
D/A Sync Bus

VIRTEX-7 FPGA
VX330T or VX690T
VCXO
GTX GTX GTX LVDS

CONFIG FPGA 32 32 32 32
FLASH PCIe 4X 4X 48
Model 71730 1 GB
Config Gen. 3 x8
Bus DDR3 DDR3 DDR3 DDR3
XMC SDRAM SDRAM SDRAM SDRAM
GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
MANAGER
Gigabit FPGA
PCIe Serial I/O GPIO
Gen. 3 x8 (option 105) (option 104)
P15 P16 P14
XMC XMC PMC
See page 27

Figure 44

Model 71730 is a member of the Onyx family of high- Each member of the Onyx family is delivered with
performance XMC modules based on the Xilinx Virtex-7 factory-installed applications ideally matched to the
FPGA. A high-speed data converter, it is suitable for boards analog interfaces. The 71730 factory-installed
connection to HF or IF ports of a communications or functions include an A/D acquisition and a D/A waveform
radar system. Its built-in data capture and playback features playback IP module for simplifying data capture and
offer an ideal turnkey solution as well as a platform for data transfer. IP modules for DDR3 SDRAM memories, a
developing and deploying custom FPGA processing IP. controller for all data clocking and synchronization functions,
It includes 1 GHz A/D and D/A converters and four a test signal generator and a PCIe interface complete the
banks of memory. In addition to supporting PCI factory-installed functions and enable the 71730 to
Express Gen. 3 as a native interface, the Model 71730 operate without the need to develop any FPGA IP.
includes optional general purpose and gigabit serial card
The front end accepts an analog HF or IF input on a front
connectors for application-specific I/O.
panel SSMC connector with transformer coupling into a TI
The Pentek Onyx architecture features a Virtex-7 ADS5400 1 GHz, 12-bit A/D converter. The digital outputs
FPGA. All of the boards data and control paths are are delivered to the Virtex-7 FPGA for signal processing, etc.
accessible by the FPGA, enabling factory-installed
Versions of the 71730 are also available as an x8 PCIe
functions including data multiplexing, channel selection,
half-length board (Model 78730), 3U VPX (Models 52730
data packing, gating, triggering and memory control. The
and 53730), 6U VPX (Models 57730 and 58730 dual
Onyx architecture organizes the FPGA as a container for
density), AMC (Model 56730), 6U cPCI (Models 72730
data processing applications where each function exists
and 74730 with dual density), and 3U cPCI (Model 73730).
as an intellectual property (IP) module.

32
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

1- or 2- Channel 3.6 GHz and 2- or 4-


2-Channel Channel 1.8 GHz, 12-bit A/D, Vir
4-Channel tex-6 FPGA
Virtex-6

Model 72640 - 6U cPCI

RF In RF In
Block Diagram, Model 72640
Model 74640 doubles all resources
except the PCI-to-PCI Bridge
RF RF
XFORMR XFORMR
Sample Clk

TTL
PPS/Gate/Sync TIMING BUS
GENERATOR 3.6 GHz (1 Channel)
A/D Clock/Sync Bus or
Gate In Clock / Sync / 1.8 GHz (2 Channel)
Reset In Gate / PPS 12-bit A/D
Ref Clk In
Ref Clk Out 12 12
Sync Bus

VIRTEX-6 FPGA
LX130T, LX240T or SX315T
MODEL 73640
LVDS GTX
INTERFACES ONLY

32 32 32 32 16 From/To Other
VIRTEX-6 FPGA 40 4X
x4 PCIe XMC Module of
LVDS GTX DDR3 DDR3 DDR3 DDR3 Config
SDRAM SDRAM SDRAM SDRAM FLASH MODEL 74640
512 MB 512 MB 512 MB 512 MB 64 MB PCIe
to PCI
40 BRIDGE
PCIe Memory Banks 1 & 2 Memory Banks 3 & 4
Optional to PCI
FPGA I/O BRIDGE Optional PCI Model 74640 Model 73640
to PCI
(Option -104) FPGA I/O BRIDGE Dual Density Single Density
(Option -104)
J2 PCI/PCI-X BUS
32-bit, 33/66 MHz
J3 PCI/PCI-X BUS
32/64-bit, 33/66 MHz

Figure 45

Models 72640, 73640 and 74640 are members modules. In addition, IP modules for DDR3 memories,
of the Cobalt family of high-performance CompactPCI controllers for all data clocking and synchronization
boards based on the Xilinx Virtex-6 FPGA. They functions, a test signal generator and a PCIe interface
consist of one or two Model 71640 XMC modules complete the factory-installed functions.
mounted on a cPCI carrier board. These models include one
The front end accepts analog HF or IF inputs on
or two 3.6 GHz, 12-bit A/D converters and four or eight
a pair of front panel SSMC connectors with transformer
banks of memory.
coupling into a Texas Instruments ADC12D1800 12-bit
The Pentek Cobalt architecture features a Virtex-6 A/D. The converter operates in single-channel interleaved
FPGA. All of the boards data and control paths are mode with a sampling rate of 3.6 GHz and an input
accessible by the FPGA, enabling factory-installed bandwidth of 1.75 GHz; or, in dual-channel mode with a
functions including data multiplexing, channel selec- sampling rate of 1.8 GHz and input bandwidth of 2.8
tion, data packing, gating, triggering and memory control. GHz. The ADC12D1800 provides a programmable 15-bit
The Cobalt architecture organizes the FPGA as a container gain adjustment allowing an input range of +2 to +4 dBm.
for data processing applications where each function exists
Model 72640 is a 6U cPCI board, while Model 73640
as an intellectual property (IP) module.
is a 3U cPCI board; Model 74640 isa dual density 6U
Each member of the Cobalt family is delivered cPCI board; also available are an XMC (Model 71640),
with factory-installed applications ideally matched to the x8 PCIe (Model 78640), 3U VPX (Models 52640 and
boards analog interfaces. The factory-installed functions of 53640), 6U VPX (Models 57640 and 58640 dual density),
these models include one or two A/D acquisition IP and AMC (Model 56640).

33
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

1- Channel 3.6 GHz or 2- Channel 1.8 GHz, 12-bit A/D, W


2-Channel ideband DDC, Vir
Wideband tex-6 FPGA
Virtex-6

Model 56641 - AMC

from from
A/D A/D

VIRTEX-6 FPGA DATAFLOW DETAIL


*Two channel mode shown. TEST
Programmable decimation of 8, 16 or 32 INPUT MULTIPLEXER SIGNAL
available in one channel mode. GENERATOR

DDC DDC
*DEC: 4, 8 or 16 *DEC: 4, 8 or 16
POWER POWER
METER & METER &
THRESHOLD THRESHOLD
DETECT DETECT
DDC CORE DDC CORE
DATA PACKING & DATA PACKING &
FLOW CONTROL FLOW CONTROL

MUX to MUX
MEM
CONTROL
METADATA METADATA
GENERATOR GENERATOR

LINKED-LIST LINKED-LIST
DMA ENGINE DMA ENGINE

A/D A/D
ACQUISITION ACQUISITION
MEMORY
CONTROLLER IP MODULE IP MODULE
MEMORY
CONTROLLER
Model 56641
AMC
PCIe INTERFACE

to to 8X 40 to to
Mem Mem FPGA Mem Mem
Bank 1 Bank 2 PCIe GPIO Bank 3 Bank 4

Figure 46

Model 56641 is a member of the Cobalt family of high- In single-channel mode, decimation can be programmed
performance AMC modules based on the Xilinx Virtex-6 to 8x, 16x or 32x. In dual-channel mode, both channels
FPGA. A very high-speed data converter based on the Model share the same decimation rate, programmable to 4x, 8x
71640 described in the previous page, it includes additional or 16x.
factory-installed IP cores to enhance its performance and
The decimating filter for each DDC accepts a
address the requirements of many applications.
unique set of user-supplied 16-bit coefficients. The 80%
The 56641 factory-installed functions include an A/D default filters deliver an output bandwidth of 0.8*s/N,
acquisition IP module. In addition, within the FPGA is where N is the decimation setting. The rejection of
a powerful factory-installed DDC IP core. The core adjacent-band components within the 80% output
supports a single-channel mode, accepting data samples bandwidth is better than 100 dB. Each DDC delivers a
from the A/D at the full 3.6 GHz rate. Additionally, a complex output stream consisting of 16-bit I + 16-bit Q
dual-channel mode supports the A/Ds 1.8 GHz two- samples at a rate of s/N.
channel operation.
Versions of the 56641 are also available as an XMC
In dual-channel mode, each DDC has an indepen- module (Model 71641), x8 PCIe board (Model 78641),
dent 32-bit tuning frequency setting that ranges from 3U VPX (Models 52641 and 53641), 6U VPX (Models
DC to s, where s is the A/D sampling frequency. 57641 and 58641 dual density), 6U cPCI (Models 72641
and 74641 dual density), and 3U cPCI (Model 73641).

34
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

1- Channel 3.6 GHz or 2-


1-Channel Channel 1.8 GHz, 12-bit A/D, W
2-Channel ideband DDC, Vir
Wideband tex-7 FPGA
Virtex-7

Model 71741 - XMC

RF In RF In

RF RF
XFORMR XFORMR
Sample Clk

TTL
PPS/Gate/Sync TIMING BUS
GENERATOR 3.6 GHz (1 Channel)
A/D Clock/Sync Bus or
Gate In Clock / Sync / 1.8 GHz (2 Channel)
Reset In Gate / PPS 12-Bit A/D
Ref Clk In
Ref Clk Out 12 12
Sync Bus

VIRTEX-7 FPGA
VX330T or VX690T

GTX GTX GTX LVDS

CONFIG FPGA 32 32 32 32
FLASH PCIe 4X 4X 48
Config Gen. 3 x8
1 GB
Model 71741 Bus DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
XMC GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
MANAGER
Gigabit FPGA
PCIe Serial I/O GPIO
Gen. 3 x8 (option 105) (option 104)
P15 P16 P14
XMC XMC PMC
See page 27

Figure 47

Model 71741 is a member of the Onyx family of The 71741 factory-installed functions include an A/
high-performance XMC modules based on the Xilinx D acquisition IP module and a programmable digital
Virtex-7 FPGA. A high-speed data converter with a downconverter.
programmable digital downconverter, it is suitable for
The DDC core supports a single-channel mode,
connection to HF or IF ports of a communications or radar
accepting data samples from the A/D at the full 3.6 GHz
system. Its built-in data capture features offer an ideal
rate. Additionally, a dual-channel mode supports the A/Ds
turnkey solution. It includes a 3.6 GHz, 12-bit A/D
1.8 GHz two-channel operation. In dual-channel mode, each
converter and four banks of memory. In addition to support-
DDC has an independent 32-bit tuning frequency setting
ing PCI Express Gen. 3 as a native interface, Model 71741
that ranges from DC to s,. In single-channel mode, decimation
includes an optional connection to the Virtex-7 FPGA for
can be programmed to 8x, 16x or 32x. In dual-channel mode,
custom I/O.
both channels share the same decimation rate, programmable
The Pentek Onyx architecture features a Virtex-7 to 4x, 8x or 16x. See the dataflow diagram of the 71641 on
FPGA. All of the boards data and control paths are the previous page for more detail.
accessible by the FPGA, enabling factory-installed
Versions of the 71741 are also available as an x8 PCIe
functions including data multiplexing, channel selection,
half-length board (Model 78741), 3U VPX (Models 52741
data packing, gating, triggering and memory control. The
and 53741), 6U VPX (Models 57741 and 58741 (dual
Onyx architecture organizes the FPGA as a container for
density), AMC (Model 56741), 6U cPCI (Models 72741
data processing applications where each function exists
and 74721 with dual density), and 3U cPCI (Model 73741).
as an intellectual property (IP) module.

35
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

2- Channel 500 MHz A/D, DUC, 2-


2-Channel Channel 800 MHz D/A, Vir
2-Channel tex-6 FPGA
Virtex-6

Model 52650 - 3U VPX

RF In RF In RF Out RF Out

RF RF RF RF
Sample Clk / XFORMR XFORMR XFORMR XFORMR
Reference Clk In A/D
TTL TIMING BUS Clock/Sync
PPS/Gate/Sync GENERATOR Bus 500 MHz 500 MHz 800 MHz 800 MHz
12-BIT A/D 12-BIT A/D 16-BIT D/A 16-BIT D/A
TTL Gate / Trig Clock / Sync /
DIGITAL
TTL Sync / PPS Gate / PPS
D/A UPCONVERTER
Sample Clk Clock/Sync 16 16
Reset Bus 32
Gate A/D
Gate D/A
Sync / PPS A/D VCXO VIRTEX-6 FPGA
Sync / PPS D/A LX130T, LX240T or SX315T
Timing Bus
LVDS GTX GTX GTX

16 16 16 16 16 16 16 16 16
40 4X 4X 4X
QDRII+ QDRII+ QDRII+ QDRII+ Config
SRAM SRAM SRAM SRAM FLASH
8 MB 8 MB 8 MB 8 MB 64 MB
Model 52650 3U
QDRII+ option 150 QDRII+ option 160
DDR3 option 155 DDR3 option 165
VPX COTS and
Option -104 Option -105
This Model is also DDR3 DDR3 DDR3 DDR3 FPGA Gigabit rugged
SDRAM SDRAM SDRAM SDRAM I/O Serial I/O
available with 400 MHz, 512 MB 512 MB 512 MB 512 MB
x4
PCIe
14-bit A/Ds
Memory Banks 1 & 2 Memory Banks 3 & 4
VPX-P2 VPX-P1
VPX BACKPLANE

Figure 48

Model 52650 is a member of the Cobalt family of Each member of the Cobalt family is delivered
high-performance 3U VPX boards based on the Xilinx with factory-installed applications ideally matched to the
Virtex-6 FPGA. A two-channel, high-speed data boards analog interfaces. The 52650 factory-installed
converter, it is suitable for connection to HF or IF ports functions include an A/D acquisition and a D/A waveform
of a communications or radar system. Its built-in data playback IP module. In addition, IP modules for either
capture and playback features offer an ideal turnkey DDR3 or QDRII+ memories, a controller for all data
solution as well as a platform for developing and deploying clocking and synchronization functions, a test signal
custom FPGA processing IP. The 52650 includes two generator and a PCIe interface complete the factory-
500 MHz 12-bit A/Ds, one DUC, two 800 MHz 16-bit installed functions.
D/As and four banks of memory. It features built-in
Multiple 52650s can be driven from the LVPECL bus
support for PCI Express over the 3U VPX backplane.
master, supporting synchronous sampling and sync functions
The Pentek Cobalt architecture features a Virtex-6 across all connected boards. The architecture supports up to
FPGA. All of the boards data and control paths are acces- four memory banks which can be configured with all
sible by the FPGA, enabling factory-installed functions QDRII+ SRAM, DDR3 SDRAM, or as combinations.
including data multiplexing, channel selection, data packing,
Versions of the 52650 are also available as a 3U VPX
gating, triggering and memory control. The Cobalt architec-
(Model 53650), 6U VPX (Models 57650 and 58650
ture organizes the FPGA as a container for data process-
dual density), XMC module (Model 71650), an x8 PCIe
ing applications where each function exists as an intellec-
board (Model 78650), AMC (Model 56650), 6U cPCI (Models
tual property (IP) module.
72650 and 74650 dual density), and 3U cPCI (Model 73650).

36
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

2- or 4- Channel 500 MHz A/D, with DDCs, DUCs, 2- or 4-


4-Channel Channel 800 MHz D/A, Vir
4-Channel tex-6 FPGA
Virtex-6

Model 72651 - 6U cPCI

from from to
A/D Ch 1 A/D Ch 2 D/A

D/A loopback
TEST
SIGNAL
INPUT MULTIPLEXER GENERATOR

DDC DDC INTERPOLATOR


DEC: 2 TO 131027 DEC: 2 TO 131027 2 TO 65536
POWER POWER IP CORE
METER & METER &
THRESHOLD THRESHOLD DATA UNPACKING
DETECT DETECT & FLOW CONTROL
MUX
DDC CORE DDC CORE
DATA PACKING & DATA PACKING & MUX
FLOW CONTROL FLOW CONTROL
MEMORY MEMORY
CONTROL CONTROL MEMORY
METADATA METADATA
GENERATOR MUX GENERATOR MUX CONTROL
to to
Mem Mem to LINKED-LIST
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Mem DMA ENGINE
DMA ENGINE DMA ENGINE
Bank 4 D/A
A/D A/D WAVEFORM
ACQUISITION ACQUISITION PLAYBACK
IP MODULE 1 IP MODULE 2 IP MODULE

AURORA sum out Model 74651 Model 73651


GIGABIT S
SERIAL SUMMER
PCIe INTERFACE Dual Density Single Density
INTERFACE sum in
BEAMFORMER CORE
4X 4X 4X
to next from previous VIRTEX-6 FPGA DATAFLOW DETAIL
board board PCIe

Figure 49

Models 72651, 73651 and 74651 are members of the A/D sampling frequency. Each DDC can have its
the Cobalt family of high-performance CompactPCI boards own unique decimation setting, supporting as many as
based on the Xilinx Virtex-6 FPGA. They consist of two or four different output bandwidths for the board.
one or two Model 71651 XMC modules mounted on a Decimations can be programmed from 2 to 131,072
cPCI carrier board. These models include two or four A/Ds, providing a wide range to satisfy most applications.
two or four multiband DDCs, one ot two DUCs, two
In addition to the DDCs, these models feature one
or four D/As and three or six banks of memory.
or two complete beamforming subsystems. Each DDC
These models feature two or four A/D Acquisition IP core contains programable I & Q phase and gain adjust-
modules for easily capturing and moving data. Each ments followed by a power meter that continuously
module can receive data from either of the two A/Ds, a measures the individual average power output. The time
test signal generator or from the D/A Waveform Playback constant of the averaging interval for each meter is program-
IP module in loopback mode. mable up to 8K samples. The power meters present average
power measurements for each DDC core output.
Within each A/D Acquisition IP Module is a
powerful DDC IP core. Because of the flexible input Model 72651 is a 6U cPCI board, while Model 73651
routing of the A/D Acquisition IP Modules, many different is a 3U cPCI board; Model 74651 a dual density 6U cPCI
configurations can be achieved including one A/D driving board; also available are an XMC (Model 71651), an x8
both DDCs or each of the two A/Ds driving its own DDC. PCIe (Model 78651), 3U VPX (Models 52651 and 53651),
6U VPX (Models 57651 and 58651 dual density), and
Each DDC has an independent 32-bit tuning
AMC (Model 56651).
frequency setting that ranges from DC to s, where s is

37
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

2- Channel 500 MHz A/D, with DDCs, DUCs, 2-


2-Channel Channel 800 MHz D/A, Vir
2-Channel tex-7 FPGA
Virtex-7

Model 56751 - AMC

RF In RF In RF Out RF Out

RF RF RF RF
Sample Clk / XFORMR XFORMR XFORMR XFORMR
Reference Clk In A/D
TTL TIMING BUS Clock/Sync
PPS/Gate/Sync GENERATOR Bus 500 MHz 500 MHz 800 MHz 800 MHz
12-BIT A/D 12-BIT A/D 16-BIT D/A 16-BIT D/A
TTL Gate / Trig Clock / Sync /
DIGITAL
TTL Sync / PPS Gate / PPS
D/A UPCONVERTER
Sample Clk Clock/Sync 16 16
Reset Bus 32
Gate A/D
Gate D/A
Sync / PPS A/D VCXO VIRTEX-7 FPGA
Sync / PPS D/A VX330T or VX690T
Timing Bus
GTX LVDS

CONFIG FPGA 32 32 32 32
FLASH PCIe 48
Config Gen. 2 x8
1 GB
Bus DDR3 DDR3 DDR3 DDR3
IPMI SDRAM SDRAM SDRAM SDRAM Model 56751
GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
CONTROLLER AMC
MANAGER
RS-232 FPGA
PCIe GPIO
Gen. 2 x8 AMC (option 104)
Ports 4 to 11 Front Front
Panel Panel

See page 27
Figure 50

Model 56751 is a member of the Onyx family of Each member of the Onyx family is delivered with
high-performance AMC modules based on the Xilinx factory-installed applications ideally matched to the boards
Virtex-7 FPGA. A multichannel, high-speed data converter analog interfaces. The 56751 factory-installed functions
with a programmable DDC, it is suitable for connection to include two A/D acquisition and a D/A waveform playback
HF or IF ports of a communications or radar system. Its IP modules. Each of the two acquisition IP modules
built-in data capture and playback features offer an ideal contains a powerful, programmable DDC IP core. The
turnkey solution as well as a platform for developing and waveform playback IP module contains an interpola-
deploying custom FPGA processing IP. It includes two A/Ds, tion IP core, ideal for matching playback rates to the data
two D/As and four banks of memory. In addition to and decimation rates of the acquisition modules. IP modules
supporting PCI Express Gen. 2 as a native interface, the for DDR3 memories, a controller for all data clocking and
Model 56751 includes a general-purpose front-panel synchronization functions, a test signal generator, and a
connector for application-specific I/O. PCIe interface complete the factory-installed functions
and enable the 56751 to operate as a turnkey solution,
The Pentek Onyx architecture features a Virtex-7
See the block diagram on the previous page for more detail.
FPGA. All of the boards data and control paths are
accessible by the FPGA, enabling factory-installed Versions of the 56751 are also available as an XMC
functions including data multiplexing, channel selection, module (Model 71751), x8 PCIe board (Model 78751),
data packing, gating, triggering and memory control. The 3U VPX (Models 52751 and 53751), 6U VPX (Models
Onyx architecture organizes the FPGA as a container for 57751 and 58751 dual density), 6U cPCI (Models 72751
data processing applications where each function exists and 74751 dual density), and 3U cPCI (Model 73751).
as an intellectual property (IP) module.

38
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 200 MHz 16-bit A/D with Vir


4-Channel tex-6 FPGA
Virtex-6

Model 7166
71660 - XMC
660

RF In RF In RF In RF In

RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clk /
Reference Clk In
Gate / Trigger / TIMING BUS
Sync / PPS GENERATOR A/D Clock/Sync Bus
200 MHz 200 MHz 200 MHz 200 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D
TTL Gate / Trig Clock / Sync /
TTL Sync / PPS Gate / PPS

Sample Clk 16 16 16 16
Reset
Gate A
Gate B
Sync / PPS A
Sync / PPS B VCXO
VIRTEX-6 FPGA
Timing Bus LX130T, LX240T or SX315T

GTX GTX GTX LVDS

16 16 16 16 16 16 16 16 16
8X 4X 4X 40
QDRII+ QDRII+ QDRII+ QDRII+ Config
SRAM SRAM SRAM SRAM FLASH
Model 71660 8 MB 8 MB 8 MB 8 MB 64 MB

XMC QDRII+ option 150 QDRII+ option 160 x8 PCIe Gigabit FPGA
DDR3 option 155 DDR3 option 165 Serial I/O GPIO
(option 105) (option 104)
DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
512 MB 512 MB 512 MB 512 MB P15 P16 P14
XMC XMC PMC
Memory Banks 1 & 2 Memory Banks 3 & 4

Figure 51

Model 71660 is a member of the Cobalt family of Each member of the Cobalt family is delivered
high-performance XMC modules based on the Xilinx with factory-installed applications ideally matched to the
Virtex-6 FPGA. A multichannel, high-speed data boards analog interfaces. The 71660 factory-installed
converter, it is suitable for connection to HF or IF ports functions include four A/D acquisition IP modules. In
of a communications or radar system. Its built-in data addition, IP modules for either DDR3 or QDRII+
capture and playback features offer an ideal turnkey solution memories, a controller for all data clocking and syn-
as well as a platform for developing and deploying custom chronization functions, a test signal generator and a
FPGA processing IP. It includes four 200 MHz, 16-bit A/Ds PCIe interface complete the factory-installed functions.
and four banks of memory. In addition to supporting
Multiple 71660s can be driven from the LVPECL
PCI Express Gen. 2 as a native interface, the Model
bus master, supporting synchronous sampling and sync
71660 includes general purpose and gigabit serial connec-
functions across all connected modules. The architecture
tors for application-specific I/O .
supports up to four memory banks which can be configured
The Pentek Cobalt architecture features a Virtex-6 with all QDRII+ SRAM, DDR3 SDRAM, or as combina-
FPGA. All of the boards data and control paths are acces- tion of two banks of each type of memory.
sible by the FPGA, enabling factory-installed functions
Versions of the 71660 are also available as an x8 PCIe
including data multiplexing, channel selection, data packing,
half-length board (Model 78660), 3U VPX (Models 52660
gating, triggering and memory control. The Cobalt architec-
and 53660), 6U VPX (Models 57660 and 58660 dual
ture organizes the FPGA as a container for data processing
density), AMC (Model 56660), 6U cPCI (Models 72660
applications where each function exists as an intellec-
and 74660 with dual density), and 3U cPCI (Model 73660).
tual property (IP) module.

39
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 200 MHz, 16-bit A/D with Vir


4-Channel tex-7 FPGA
Virtex-7

Model 7176
71760 - XMC
760

RF In RF In RF In RF In

RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clk /
Reference Clk In
Gate / Trigger / TIMING BUS
Sync / PPS GENERATOR A/D Clock/Sync Bus
200 MHz 200 MHz 200 MHz 200 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D
TTL Gate / Trig Clock / Sync /
TTL Sync / PPS Gate / PPS

Sample Clk 16 16 16 16
Reset
Gate A
Gate B
Sync / PPS A
Sync / PPS B VIRTEX-7 FPGA
VCXO
Timing Bus VX330T or VX690T

GTX GTX GTX LVDS

CONFIG FPGA 32 32 32 32
FLASH PCIe 4X 4X 48
Config Gen. 3 x8
1 GB
Bus DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
Model 71760 GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
XMC MANAGER
Gigabit FPGA
PCIe Serial I/O GPIO
Gen. 3 x8 (option 105) (option 104)
P15 P16 P14
XMC XMC PMC

See page 27
Figure 52

Model 71760 is a member of the Onyx family of Each member of the Onyx family is delivered with factory-
high-performance XMC modules based on the Xilinx installed applications ideally matched to the boards analog
Virtex-7 FPGA. A multichannel, high-speed data converter, interfaces. The 71760 factory-installed functions include four
it is suitable for connection to HF or IF ports of a A/D acquisition IP modules for simplifying data capture and
communications or radar system. Its built-in data capture data tranfer. IP modules for DDR3 SDRAM memories, a
features offer an ideal turnkey solution as well as a controller for all data clocking and synchronization functions, a
platform for developing and deploying custom FPGA test signal generator, and a PCIe interface complete the factory-
processing IP. It includes four A/Ds and four banks of installed functions.
memory. In addition to supporting PCI Express Gen. 3 as a
The 71760 architecture supports four independent
native interface, the Model 71760 includes general purpose
DDR3 SDRAM memory banks. Each bank is 1 GB deep
and gigabit serial connectors for application-specific I/O.
and is an integral part of the modules DMA capabili-
Based on the proven design of the Pentek Cobalt family, ties, providing FIFO memory space for creating DMA
Onyx raises the processing performance with the new flagship packets. Built-in memory functions include multichannel
family of Virtex-7 FPGAs from Xilinx. As the central feature of A/D data capture, tagging and streaming.
the board architecture, the FPGA has access to all data and
Versions of the 71760 are also available as an x8 PCIe
control paths, enabling factory-installed functions including data
half-length board (Model 78760), 3U VPX (Models 52760
multiplexing, channel selection, data packing, gating, triggering
and 53760), 6U VPX (Models 57760 and 58760 (dual
and memory control. The Onyx Architecture organizes the
density), AMC (Model 56760), 6U cPCI (Models 72760
FPGA as a container for data processing applications where each
and 74760 dual density), and 3U cPCI (Model 73760).
function exists as an intellectual property (IP) module.

40
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 200 MHz 16-bit A/D with Installed IP Cores, Vir


4-Channel tex-6 FPGA
Virtex-6

Model 71661 - XMC


71661

from from from from


A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4

TEST
SIGNAL INPUT MULTIPLEXER
GENERATOR

DDC DDC DDC DDC


DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536
POWER POWER POWER POWER
METER & METER & METER & METER &
THRESHOLD THRESHOLD THRESHOLD THRESHOLD
DETECT DETECT DETECT DETECT
MUX
DDC CORE DDC CORE DDC CORE DDC CORE
DATA PACKING & DATA PACKING & DATA PACKING & DATA PACKING &
FLOW CONTROL FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL CONTROL
METADATA METADATA METADATA METADATA
to GENERATOR MUX to GENERATOR MUX to GENERATOR MUX to GENERATOR MUX
Mem Mem Mem Mem
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Bank 3 LINKED-LIST Bank 4 LINKED-LIST
DMA ENGINE DMA ENGINE DMA ENGINE DMA ENGINE
A/D A/D A/D A/D
ACQUISITION ACQUISITION ACQUISITION ACQUISITION
IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4

Model 71661
XMC
AURORA
sum out
GIGABIT S VIRTEX-6 FPGA DATAFLOW DETAIL PCIe INTERFACE
SERIAL SUMMER
INTERFACE sum in
BEAMFORMER CORE
4X 4X 8X
to next from previous
board board PCIe

Figure 53

Model 71661 is a member of the Cobalt family of high- can be programmed from 2 to 65,536 providing a wide
performance XMC modules based on the Xilinx Virtex-6 range to satisfy most applications.
FPGA. A multichannel, high-speed data converter based on
The 71661 also features a complete beamforming
the Model 71660 described in the previous page, it includes
subsystem. Each DDC core contains programable I & Q
factory-installed IP cores to enhance the performance of the
phase and gain adjustments followed by a power meter
71620 and address the requirements of many applications.
that continuously measures the individual average power
The 71661 factory-installed functions include four A/D output. The power meters present average power measure-
acquisition IP modules. Each of the four acquisition IP ments for each DDC core output in easy-to-read registers. A
modules contains a powerful, programmable DDC IP threshold detector automatically sends an interrupt to
core. IP modules for either DDR3 or QDRII+ memo- the processor if the average power level of any DDC
ries, a controller for all data clocking and synchronization core falls below or exceeds a programmable threshold.
functions, a test signal generator, an Aurora gigabit
For larger systems, multiple 71661s can be chained
serial interface, and a PCIe interface complete the
together via the built-in Xilinx Aurora gigabit serial
factory-installed functions.
interface through the P16 XMC connector.
Each DDC has an independent 32-bit tuning frequency
Versions of the 71661 are also available as an x8 PCIe
setting that ranges from DC to s, where s is the A/D
half-length board (Model 78661), 3U VPX (Models 52661
sampling frequency. Each DDC can have its own
and 53661), 6U VPX (Models 57661 and 58661 dual
unique decimation setting, supporting as many as four
density), AMC (Model 56661), 6U cPCI (Models 72661
different output bandwidths for the board. Decimations
and 74661 with dual density), and 3U cPCI (Model 73661).

41
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 200 MHz 16-bit A/D with Installed IP Cores, Vir


4-Channel tex-7 FPGA
Virtex-7

Model 58761 - 6U VPX, Dual Density

RF In RF In RF In RF In

RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clk /
Reference Clk In
Gate / Trigger / TIMING BUS
Sync / PPS GENERATOR A/D Clock/Sync Bus 200 MHz 200 MHz 200 MHz 200 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D
TTL Gate / Trig Clock / Sync /
TTL Sync / PPS Gate / PPS 16 16 16 16

Sample Clk
Reset
Gate A
Gate B VIRTEX-7 FPGA
Sync / PPS A VX330T or VX690T Aurora
Sync / PPS B VCXO Gigabit Serial I/O
Timing Bus LVDS GTX GTX GTX

32 32 32 32 FPGA PCIe
48 Config Gen. 3 4X 4X
DDR3 DDR3 DDR3 DDR3 Bus x8
SDRAM SDRAM SDRAM SDRAM From/To
CONFIG GATEXPRESS PCIe
1 GB 1 GB 1 GB 1 GB FLASH CONFIGURATION Other XMC
1 GB MANAGER Module of Model 58761
Model 58761
PCIe 6U VPX
Gen. 3 x8
Block Diagram, Model 57761. Option -104 Sum Sum
dual density
FPGA PCIe-to PCIe from to
Model 58761 doubles all resources I/O SWITCH prior next
board board
except the PCIe-to-PCIe Switch and PCIe
provides 24 LVDS pairs from the Gen. 3 x8
2nd FPGA to VPX-P5 VPX-P3 VPX-P1 VPX-P2
VPX BACKPLANE
See page 27
Figure 54

Model 58761 is a member of the Onyx family of high- tions can be programmed from 2 to 65,536 providing a
performance VPX boards based on the Xilinx Virtex-7 FPGA. wide range to satisfy most applications.
A multichannel, high-speed data converter based on the Model
The 58761 also features two complete beamforming
71760 described previously, it includes factory-installed IP
subsystems. Each DDC core contains programmable I &
cores to enhance the performance of the 71760 and address
Q phase and gain adjustments followed by a power meter
the requirements of many applications.
that continuously measures the individual average power
The 58761 factory-installed functions include eight A/D output. The power meters present average power measure-
acquisition IP modules. Each of the acquisition IP modules ments for each DDC core output in easy-to-read registers. A
contains a powerful, programmable DDC IP core. IP threshold detector automatically sends an interrupt to
modules for DDR3 memories, controllers for all data the processor if the average power level of any DDC
clocking and synchronization functions, test signal core falls below or exceeds a programmable threshold.
generators, Aurora gigabit serial interfaces, and a PCIe
For larger systems, multiple 58761s can be chained
interface complete the factory-installed functions.
together via the built-in Xilinx Aurora gigabit serial
Each DDC has an independent 32-bit tuning interfaces.
frequency setting that ranges from DC to s, where s is
Versions of the 58761 are also available as XMC (Model
the A/D sampling frequency. Each DDC can have its
71761), x8 PCIe half-length board (Model 78761), 3U VPX
own unique decimation setting, supporting as many as
(Models 52761 and 53761), 6U VPX (Model 57761 single
eight different output bandwidths for the board. Decima-
density), AMC (Model 56761), 6U cPCI (Models 72761
and 74761 dual density), and 3U cPCI (Model 73761).

42
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 200 MHz 16-bit A/D with Installed IP Cores, Vir


4-Channel tex-6 FPGA
Virtex-6

Model 78662 - PCIe


78662

from from from from


A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4

TEST
SIGNAL INPUT MULTIPLEXER
GENERATOR

DIGITAL DIGITAL DIGITAL DIGITAL


DOWN- DOWN- DOWN- DOWN-
CONVERTER
.
CONVERTER
.
CONVERTER
.
CONVERTER
.

BANK 1: CH 1-8 BANK 2: CH 9-16 BANK 3: CH 17-24 BANK 4: CH 18-32


DEC: 16 TO 8192 DEC: 16 TO 8192 DEC: 16 TO 8192 DEC: 16 TO 8192
DDC DDC DDC DDC
CORE CORE CORE CORE
DATA PACKING & DATA PACKING & DATA PACKING & DATA PACKING &
FLOW CONTROL FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL CONTROL
METADATA METADATA METADATA METADATA
to GENERATOR MUX to GENERATOR MUX GENERATOR MUX GENERATOR MUX
to to
Mem Mem Mem Mem
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Bank 3 LINKED-LIST LINKED-LIST
DMA ENGINE DMA ENGINE DMA ENGINE
Bank 4 DMA ENGINE
A/D A/D A/D A/D
ACQUISITION ACQUISITION ACQUISITION ACQUISITION
IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4
Model 78662
x8 PCIe
VIRTEX-6 FPGA DATAFLOW DETAIL (supports user installed IP)
PCIe INTERFACE

32 32 32 32 8X 4X 4X 40
Memory Memory Memory Memory PCIe Gigabit FPGA
Bank 1 Bank 2 Bank 3 Bank 4 Serial I/O GPIO

Figure 55

Model 78662 is a member of the Cobalt family of can have its own unique decimation setting supporting
high-performance PCIe boards based on the Xilinx Virtex-6 a different bandwidth associated with each of the four
FPGA. Based on the Model 71660 presented previously, acquisition modules.
this four-channel, high-speed data converter with
The decimating filter for each DDC bank accepts a
programmable DDCs is suitable for connection to HF or
unique set of user-supplied 18-bit coefficients. The 80%
IF ports of a communications or radar system.
default filters deliver an output bandwidth of 0.8*s/N,
The 78662 factory-installed functions include four A/D where N is the decimation setting. The rejection of
acquisition IP modules. Each of the four acquisition IP adjacent-band components is better than 100 dB.
modules contains a powerful, programmable 8-channel
Each DDC delivers a complex output stream consisting
DDC IP core. IP modules for either DDR3 or QDRII+
of 24-bit I + 24-bit Q samples at a rate of s/N. Any
memories, a controller for all data clocking and synchroni-
number of channels can be enabled within each bank,
zation functions, a test signal generator, voltage and
selectable from 0 to 8. Multiple 78662s can be driven
temperature monitoring, and a PCIe interface complete the
from the LVPECL bus master, supporting synchronous
factory-installed functions.
sampling and sync functions across all connected boards.
Each of the 32 DDC channels has an independent
Versions of the 78662 are also available as an XMC
32-bit tuning frequency setting that ranges from DC to
module (Model 71662), 3U VPX (Models 52662 and
s, where s is the A/D sampling frequency. All of the
53662), 6U VPX (Models 57662 and 58662 with dual
8 channels within a bank share a common decimation
density), AMC (Model 56662), 6U cPCI (Models 72662
setting ranging from 16 to 8192. Each 8-channel bank
and 74662 with dual density), and 3U cPCI (Model 73662).

43
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

1100- Channel GSM Channelizer with Quad A/D, Vir


1100-Channel tex-6 FPGA
Virtex-6

Model 52663 - 3U VPX


52663

Ch A 180 MHz
RF In 16-BIT A/D M GSM SUPER FIFO &
PACKET
U CHANNELIZER CHANNEL LINKED-LIST
GENERATOR
X 375 CHANNELS ENGINE DMA ENGINE
Ch B 180 MHz
RF In 16-BIT A/D
M GSM SUPER FIFO &
PACKET
U CHANNELIZER CHANNEL LINKED-LIST
GENERATOR
X 375 CHANNELS ENGINE DMA ENGINE
Ch C 180 MHz GEN 2
RF In 16-BIT A/D x4 PCIe
M GSM SUPER FIFO & INTERFACE
PACKET
U CHANNELIZER CHANNEL LINKED-LIST
GENERATOR
Ch D X 175 CHANNELS ENGINE DMA ENGINE
180 MHz
RF In 16-BIT A/D 4X

M GSM SUPER FIFO &


PACKET
U CHANNELIZER CHANNEL LINKED-LIST
Sample / GENERATOR
X 175 CHANNELS ENGINE DMA ENGINE
Ref Clock In
Model 52633 3U VPX
Clock / CLOCK, SYNC
180 MHz
x4 COTS and rugged
Sync & TRIGGER PCIe
GENERATOR VCXO
Bus

Gate / Trigger / VPX-P1


Sync / PPS VPX BACKPLANE

Figure 56

The Model 52663 accepts four analog inputs from Super-channel packets are formed by appending
an external analog RF tuner, such as the Pentek Model enabled super-channel samples sequentially from each
8111, where the GSM RF bands are downconverted to bank. Once complete, a unique super-channel packet
an IF frequency. These IF signals are then digitized by header is inserted at the beginning of each packet for
four A/D converters and routed to four channelizer identification. The header contains a time stamp, a
banks, which perform digital downconversion of all sequential packet count, the number of enabled super-
GSM channels to baseband. Two of the banks handle channels, the DMA channel identifier, and other information.
175 channels for the lower GSM transmit/receive bands
The 52663 is ideal for mobile monitoring systems
and two more banks handle 375 channels for the upper
that must capture some or all of the 1100 uplink and
bands. The DDC channels within each bank are equally
downlink signals in both upper and lower GSM bands.
spaced at 200 kHz.
This full-global system for mobile communications
Each DDC output is resampled to a 4x symbol rate spectrum monitoring targets homeland security, govern-
of 1.08333 MHz to simplify symbol recovery. Every four ment and military applications.
DDC outputs are combined into a frequency-division
Versions of the 52633 are also available as an XMC
super-channel that allows transmission of all 1100
module (Model 71663), an x8 PCIe half-length board
channels across the PCIe Gen. 2 x4 interface. The GSM
(Model 78663), 3U VPX (Model 53663), 6U VPX
channelizer IP core is supported with factory-installed
(Models 57663 and 58663 with dual density), AMC
FPGA functions including packet formation, time
(Model 56663), 6U cPCI (Models 72663 and 74663
stamping, four DMA controllers, gating and triggering.
with dual density), and 3U cPCI (Model 73663).

44
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 200 MHz 16-bit A/D with Installed DDC and VIT
4-Channel A 49.0 IP Cores, Vir
VITA tex-6 FPGA
Virtex-6

Model 53664 - 3U VPX


from from from from
A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4

TEST
SIGNAL INPUT MULTIPLEXER
GENERATOR

DDC DDC DDC DDC


DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536
POWER POWER POWER POWER
METER & METER & METER & METER &
THRESHOLD THRESHOLD THRESHOLD THRESHOLD
DETECT DETECT DETECT DETECT
MUX
DDC CORE DDC CORE DDC CORE DDC CORE
DATA PACKING & DATA PACKING & DATA PACKING & DATA PACKING &
FLOW CONTROL FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL CONTROL
METADATA METADATA METADATA METADATA
to GENERATOR MUX to GENERATOR MUX to GENERATOR MUX to GENERATOR MUX
Mem Mem Mem Mem
Bank 1 LINKED-LIST DMA Bank 2 LINKED-LIST DMA Bank 3 LINKED-LIST DMA Bank 4 LINKED-LIST DMA
ENGINE & VITA 49.0 ENGINE & VITA 49.0 ENGINE & VITA 49.0 ENGINE & VITA 49.0
A/D A/D A/D A/D
ACQUISITION ACQUISITION ACQUISITION ACQUISITION
IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4
Model 53664 3U VPX
COTS & Rugged
AURORA
sum out
GIGABIT S VIRTEX-6 FPGA DATAFLOW DETAIL PCIe INTERFACE
SERIAL SUMMER
INTERFACE sum in
BEAMFORMER CORE
4X 4X 8X
to next from previous
board board PCIe

Figure 57

Model 53664 is a member of the Cobalt family of high- Defined Radio (SDR) systems. Specifically, each SDR
performance 3U VPX boards based on the Xilinx Virtex-6 receiver manufacturer typically develops custom and
FPGA. A multichannel, high-speed data converter based on proprietary digitized data and metadata formats, making
the Model 71660 described previously, it includes a program- interoperability of data from different receivers impossible.
mable DDC and is suitable for connection to HF or IF ports
of a communications or radar system. Its built-in data capture VITA 49.0 solves this problem by providing a frame-
and playback features offer an ideal turnkey solution. The work for SDR receivers used for analysis of RF spectrum
53664 PCIe output supports fully the VITA 49.0 VITA and localization of RF emmisions. It is based upon a
Radio Transport (VRT) Standard described on page 20. transport protocol layer to convey time-stamped digital
data between components in the system. With a com-
The 53664 factory-installed functions include four A/D mon protocol, SDR receivers can be interchanged, thereby
acquisition IP modules. Each of the four acquisition IP enabling hardware upgrades and mitigating hardware
modules contains a powerful, programmable DDC IP lifecycle limitations. This eliminates the need to create
core. IP modules for either DDR3 or QDRII+ memo- new software to support each new receiver. The 53664
ries, a controller for all data clocking and synchronization supports fully the VITA-49.0 specification.
functions, a test signal generator, an Aurora gigabit
serial interface, and a PCIe interface complete the Versions of the 53664 are also available as a different
factory-installed functions. 3U VPX (Model 52664), 6U VPX (Models 57664 and
58664 dual density), XMC (Model 71664), x8 PCIe (Model
The VITA 49.0 specification addresses the problem of 78664), AMC (Model 56664), 6U cPCI (Models 72664
interoperability between different elements of Software and 74664 dual density), and 3U cPCI (Model 73664).

45
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 1.25 GHz D/A with DUC, Vir


4-Channel tex-6 FPGA
Virtex-6

Model 57670 - 6U VPX


57670 VPX,, Single Density

RF Out RF Out RF Out RF Out

RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clk /
Reference Clk In
TIMING BUS
Trigger In GENERATOR 1.25 GHz 1.25 GHz 1.25 GHz 1.25 GHz
Clock/Sync
16-BIT D/A 16-BIT D/A 16-BIT D/A 16-BIT D/A
Clock / Sync / Bus A
DIGITAL DIGITAL DIGITAL DIGITAL
Gate In Gate / PPS
UPCONVERTER UPCONVERTER UPCONVERTER UPCONVERTER
Sync In Clock/Sync
Bus B
mSync Bus A
16 16
Gate In
Sync In
mSync Bus B VIRTEX-6 FPGA
VCXO
LX130T, LX240T or SX315T Option -105
Gigabit Serial I/O
LVDS GTX GTX GTX

32 32 32 32 16
40 8X 4X 4X
DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
Config
FLASH
Model 57670
512 MB 512 MB 512 MB 512 MB 64 MB 6U VPX
Memory Banks 1 & 2 Memory Banks 3 & 4 single density
Option -104 PCIe
FPGA Gen. 2 x8
I/O

VPX-P3 VPX-P1 VPX-P2


VPX BACKPLANE

Figure 58

Model 57670 is a member of the Cobalt family of Each member of the Cobalt family is delivered with
high-performance 6U VPX boards based on the Xilinx factory-installed applications ideally matched to the boards
Virtex-6 FPGA. This 4-channel, high-speed data analog interfaces. The Model 57670 factory-installed
converter is suitable for connection to transmit HF or IF functions include a sophisticated D/A Waveform
ports of a communications or radar system. Its built-in Playback IP module. Four linked-list controllers support
data playback features offer an ideal turnkey solution waveform generation to the four D/As from tables stored
for demanding transmit applications. It includes four in either on-board memory or off-board host memory.
D/As, four digital upconverters and four banks of
IP modules for DDR3 SDRAM memories, a
memory. In addition to supporting PCI Express Gen. 2 as
controller for all data clocking and synchronization
a native interface, the Model 57670 includes a front panel
functions, a test signal generator, and a PCIe interface
general-purpose connector for application-specific I/O.
complete the factory-installed functions and enable the
The Pentek Cobalt Architecture features a Virtex-6 57670 to operate as a turnkey solution without the need to
FPGA. All of the boards data and control paths are develop FPGA IP.
accessible by the FPGA, enabling factory-installed functions
Versions of the 57670 are also available as XMC
including data multiplexing, channel selection, data
(Model 71670), x8 PCIe (Model 78670), 3U VPX (Models
packing, gating, triggering and memory control. The
52670 and 53670), 6U VPX (Model 58670 dual density),
Cobalt Architecture organizes the FPGA as a container
AMC (Model 56670), 6U cPCI (Models 72670 and
for data processing applications where each function
74670 dual density), and 3U cPCI (Model 73670).
exists as an intellectual property (IP) module.

46
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 1.25 GHz D/A with DUC, Extended Interpolation


4-Channel Interpolation,, Vir tex-6 FPGA
Virtex-6

Model 71671 - XMC


71671

to to
16 16
D/A Ch 1 & 2 D/A Ch 3 & 4

TEST DATA DATA


SIGNAL INTERLEAVER INTERLEAVER
GENERATOR

INTERPOLATOR INTERPOLATOR INTERPOLATOR INTERPOLATOR


2 TO 65536 2 TO 65536 2 TO 65536 2 TO 65536
IP CORE IP CORE IP CORE IP CORE

DATA DATA DATA DATA


UNPACKING UNPACKING UNPACKING UNPACKING
& FLOW & FLOW & FLOW & FLOW
CONTROL CONTROL CONTROL CONTROL

MUX MUX MUX MUX

MEMORY MEMORY MEMORY MEMORY


CONTROL CONTROL CONTROL CONTROL

to LINKED-LIST to LINKED-LIST to LINKED-LIST to LINKED-LIST


Mem DMA ENGINE Mem DMA ENGINE Mem DMA ENGINE Mem DMA ENGINE
Bank 1 D/A Bank 2 D/A Bank 3 D/A Bank 4 D/A
WAVEFORM WAVEFORM WAVEFORM WAVEFORM
PLAYBACK PLAYBACK PLAYBACK PLAYBACK
IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4
Model 71671
XMC
PCIe INTERFACE (supports user installed IP)
VIRTEX-6 FPGA DATAFLOW DETAIL

Memory Memory Memory Memory 8X 4X 4X 40


Bank 1 Bank 2 Bank 3 Bank 4 Gigabit FPGA
PCIe Serial I/O GPIO

Figure 59

Model 71671 is a member of the Cobalt family of high- selectable IF center frequency. It delivers real or quadra-
performance XMC modules based on the Xilinx Virtex-6 ture (I+Q) analog outputs to a 16-bit D/A converter.
FPGA. A multichannel, high-speed data converter based on
If translation is disabled, each D/A acts as an
the Model 71670 described previously, it includes factory-
interpolating 16-bit D/A with output sampling rates up
installed IP cores to enhance the performance of the 71670
to 1.25 GHz. In both modes, the D/A provides interpolation
and address the requirements of many applications.
factors of 2x, 4x, 8x and 16x.
The Model 56671 factory-installed functions
In addition to the DAC3484, the 71671 features an
include a sophisticated D/A Waveform Playback IP
FPGA-based interpolation engine which adds two
module. Four linked-list controllers support waveform
additonal interpolation stages programmable from 2x to
generation to the four D/As from tables stored in either
256x. The combined interpolation results in a range
on-board memory or off-board host memory.
from 2x to 1,048,576x for each D/A channel and is ideal
Two Texas Instruments DAC3484s provide four DUC for matching the digital downconversion and data
(digital upconverter) and D/A channels. Each channel reduction used on the receiving channels of many
accepts a baseband real or complex data stream from the communications systems.
FPGA and provides that input to the upconvert, interpo-
Versions of the 71761 are also available as an x8 PCIe half-
late and D/A stage.
length board (Model 78671), 3U VPX (Models 52671 and
When operating as a DUC, it interpolates and trans- 53671), 6U VPX (Models 57671 and 58671 with dual
lates real or complex baseband input signals to a user density), AMC (Model 56671), 6U cPCI (Models 72671
and 74671 with dual density), and 3U cPCI (Model 73671).

47
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 1.25 GHz D/A with DUC, Extended Interpolation


4-Channel Interpolation,, Vir tex-7 FPGA
Virtex-7

Model 71771 - XMC

RF Out RF Out RF Out RF Out

RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clk /
Reference Clk In
TIMING BUS
Trigger In GENERATOR 1.25 GHz 1.25 GHz 1.25 GHz 1.25 GHz
Clock/Sync
16-BIT D/A 16-BIT D/A 16-BIT D/A 16-BIT D/A
Clock / Sync / Bus A
DIGITAL DIGITAL DIGITAL DIGITAL
Gate In Gate / PPS
UPCONVERTER UPCONVERTER UPCONVERTER UPCONVERTER
Sync In Clock/Sync
Bus B
mSync Bus A
16 16
Gate In
Sync In
mSync Bus B VIRTEX-7 FPGA
VCXO
VX330T or VX690T

GTX GTX GTX LVDS

CONFIG FPGA 32 32 32 32
Model 71771 FLASH PCIe 4X 4X 48
Config Gen. 3 x8
1 GB
XMC Bus DDR3 DDR3
SDRAM
DDR3
SDRAM
DDR3
SDRAM
SDRAM
GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
MANAGER
Gigabit FPGA
PCIe Serial I/O GPIO
Gen. 3 x8 (option 105) (option 104)

See page 27 P15 P16 P14


XMC XMC PMC

Figure 60

Model 71771 is a member of the Onyx family of The Model 71771 factory-installed functions
high-performance XMC modules based on the Xilinx include a sophisticated D/A Waveform Playback IP
Virtex-7 FPGA. This 4-channel, high-speed data module to support waveform generation to the four
converter is suitable for connection to transmit HF or IF D/As from tables stored in on-board or off-board host
ports of a communications or radar system. Its built-in memory.
data playback features offer an ideal turnkey solution
Two Texas Instruments DAC3484s provide four DUC
for demanding transmit applications.
and D/A channels with interpolation factors of 2x, 4x, 8x and
It includes four digital upconverters, four D/As 16x. In addition to the DAC3484, the 71771 features an
with a wide range of programmable interpolation factors, FPGA-based interpolation engine. The combined total
and four banks of memory. In addition to supporting PCI interpolation results in a range from 2x to 1,048,576x for
Express Gen. 3 as a native interface, the Model 71771 each D/A channel and is ideal for matching the digital
includes optional general-purpose and gigabit serial downconversion and data reduction used on the receiving
connectors for application-specific I/O. channels of many communications systems. See the block
diagram of the 71671 on the previous page for more detail.
The Pentek Onyx architecture features a Virtex-7
FPGA. All of the boards data and control paths are Versions of the 71771 are also available as an x8 PCIe half-
accessible by the FPGA, enabling factory-installed length board (Model 78771), 3U VPX (Models 52771 and
functions including data multiplexing, channel selection, 53771), 6U VPX (Models 57771 and 58771 with dual
data packing, gating, triggering and memory control. density), AMC (Model 56771), 6U cPCI (Models 72771
and 74771 with dual density), and 3U cPCI (Model 73771).

48
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

L-Band RF TTuner
uner with 2- Channel 200 MHz A/D and Vir
2-Channel tex-6 FPGA
Virtex-6

Model 53690 - 3U VPX


53690

Ref RF Ref
In In Out

MAX2112
GC 12-BIT
D/A

Sample Clk / Control


Reference Clk In Ref
I Q
Trigger 1 TIMING
Trigger 2 GENERATOR A/D Clock/Sync 200 MHz 200 MHz
Clock / Sync / 16-BIT A/D 16-BIT A/D
TTL Gate / Trig Gate / PPS
TTL Sync / PPS

Sample Clk 16 16 2
Ref In
Gate A 2
IC
Gate B
Sync / PPS A
Sync / PPS B VCXO VIRTEX-6 FPGA
Timing Bus LX130T, LX240T or SX315T Option -105
Gigabit Serial I/O
LVDS GTX GTX GTX

16 16 16 16 16 16 16 16 16
40 8X 4X 4X
QDRII+ QDRII+ QDRII+ QDRII+ Config Option -104
SRAM SRAM SRAM SRAM FLASH FPGA x8
8 MB 8 MB 8 MB 8 MB 64 MB PCIe
I/O
Model 53690 3U VPX
QDRII+ option 150 QDRII+ option 160
CROSSBAR
COTS and rugged
DDR3 option 155 DDR3 option 165
SWITCH
DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X
512 MB 512 MB 512 MB 512 MB
Gbit Gbit Gbit Gbit
Serial Serial Serial Serial
Memory Banks 1 & 2 Memory Banks 3 & 4
VPX-P2 VPX-P1
VPX BACKPLANE

Figure 61

Model 53690 is a member of the Cobalt family of boards analog interfaces. The 53690 factory-installed
high-performance 3U VPX boards based on the Xilinx functions include two A/D acquisition IP modules. IP
Virtex-6 FPGA. A 2-channel high-speed data converter, it modules for either DDR3 or QDRII+ memories, a
is suitable for connection directly to the RF port of a controller for all data clocking and synchronization
communications or radar system. Its built-in data capture functions, a test signal generator, and a PCIe interface
features offer an ideal turnkey solution. The Model 53690 complete the factory-installed functions.
includes an L-Band RF tuner, two 200 MHz, 16-bit
A front panel connector accepts L-Band signals
A/Ds and four banks of memory. It features built-in
between 925 MHz and 2175 MHz from an antenna LNB.
support for PCI Express over the 3U VPX backplane.
A Maxim MAX2112 tuner directly converts these signals to
The Pentek Cobalt architecture features a Virtex-6 baseband using a broadband I/Q downconverter. The device
FPGA. All of the boards data and control paths are acces- includes an RF variable-gain LNA (low-noise amplifier), a
sible by the FPGA, enabling factory-installed functions PLL synthesized local oscillator, quadrature (I + Q) down-
including data multiplexing, channel selection, data packing, converting mixers, baseband lowpass filters and variable-
gating, triggering and memory control. The Cobalt architec- gain baseband amplifiers.
ture organizes the FPGA as a container for data processing
Versions of the 53690 are also available as an XMC
applications where each function exists as an intellec-
(Model 71690), an x8 PCI board (Model 78690), 3U VPX
tual property (IP) module.
(Model 52690), 6U VPX (Models 57690 and 58690 dual
Each member of the Cobalt family is delivered with density), AMC (Model 56690), 6U cPCI (Models 72690
factory-installed applications ideally matched to the and 74690 dual density), and 3U cPCI (Model 73690).

49
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

L-Band RF TTuner
uner with 2- Channel 500 MHz A/D and Vir
2-Channel tex-7 FPGA
Virtex-7

Model 71791 - XMC


Maxim 2121 L-Band Tuner
IF or Baseband I
Ref In L-Band RF In LNA LPF

Q IF or Base-
VCO LPF band Q
Sample Clk / 975 2175 MHz
I Baseband
Reference Clk In Amps 123.75 MHz
Ref Out
TIMING
GENERATOR AGC In
XTAL 500 MHz 500 MHz
OSC 12-BIT A/D 12-BIT A/D
Clock / Sync / Control 12-BIT
TTL Gate / Trig Gate / PPS D/A
TTL Sync / PPS
A/D Clock Q I
Sample Clk
Sync Clock 12 12 12
Gate A
Gate B
Sync
PPS PHASE-LOCKED VIRTEX-7 FPGA MULTIBAND MULTIBAND
PROGRAMMABLE VX330T or VX690T DDC DDC
Timing Bus VCXO

GTX GTX GTX LVDS


Model 71791
CONFIG FPGA
XMC
PCIe 48 32 32 32 32
FLASH Config 4X 4X
1 GB Gen. 3 x8
Bus DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
MANAGER Option -105 Option -104
Gigabit FPGA
PCIe Serial I/O GPIO
Gen. 3 x8
P15 P16 P14 See page 27
XMC XMC PMC

Figure 62

Model 71791 is a member of the Onyx family of The 71791 factory-installed functions include two A/D
high-performance XMC modules based on the Xilinx acquisition IP modules, four DDR3 memory controllers,
Virtex-7 FPGA. It is suitable for connection directly to two DDCs (digital downconverters), an RF tuner
an L-band signal for SATCOM and communications controller, a clock and synchronization generator, a
systems. Its built-in data capture features offer an ideal test signal generator, and a Gen 3 PCIe interface.
turnkey solution as well as a platform for developing
A front panel SSMC connector accepts L-Band signals
and deploying custom FPGA processing IP.
between 925 MHz and 2175 MHz, typically from an L-Band
It includes an L-Band RF tuner, two A/Ds and four antenna or an LNB (low noise block). The Maxim MAX2121
banks of memory. In addition to supporting PCI Express tuner directly converts these L-Band signals to IF or baseband
Gen. 3 as a native interface, the Model 71791 includes using a broadband I/Q downconverter. The device
general purpose and gigabit serial connectors for includes an RF variable-gain LNA, a PLL (phase-locked
application-specific I/O. loop) synthesized local oscillator, quadrature (I+Q)
down-converting mixers, output low pass filters, and
The Pentek Onyx Architecture features a Virtex-7 FPGA. All
variable-gain baseband amplifiers.
of the boards data and control paths are accessible by the FPGA, to
suport factory-installed functions including data acquisition, Versions of the 71791 are also available as an x8 PCIe half-
control, channel selection, data packing, gating, triggering and length board (Model 78791), 3U VPX (Models 52791 and
memory control. The Onyx Architecture organizes the FPGA as a 53791), 6U VPX (Models 57791 and 58791 with dual
container for data processing applications where each density), AMC (Model 56791), 6U cPCI (Models 72791
function exists as an intellectual property (IP) module. and 74791 with dual density), and 3U cPCI (Model 73791).

50
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Software-Defined Radio Handbook

Products

LVDS Digital I/O with Vir tex-6 FPGA


Virtex-6

Model 71610 - XMC

80-pin Front Panel


Connector

32 Pairs LVDS Data Data


LVDS Data Clock Valid Suspend

VIRTEX-6 FPGA
LX130T, LX240T or SX315T

LVDS GTX GTX GTX

32 32 32 32 16
40 8X 4X 4X
DDR3 DDR3 DDR3 DDR3 Config
SDRAM SDRAM SDRAM SDRAM FLASH
512 MB 512 MB 512 MB 512 MB 64 MB
Optional Optional
Model 71610 Memory Banks 1 & 2 Memory Banks 3 & 4 FPGA x8 PCIe Gigabit
Option 165
XMC GPIO Serial I/O

PMC P14 XMC P15 XMC P16

Figure 63

Model 71610 is a member of the Cobalt family of boards interface. The 71610 factory-installed functions
high-performance XMC modules based on the Xilinx include 32-bit acquisition and generation IP modules, to
Virtex-6 FPGA. This digital I/O module provides 32 support either input or output functions, respectively.
LVDS differential inputs or outputs plus LVDS clock,
IP modules for DDR3 SDRAM memories, a control-
data valid, and data flow control on a front panel 80-pin
ler for all data clocking, a test signal generator, and a PCIe
connector. Its built-in data capture and data generation
interface complete the factory-installed functions and
feature offers an ideal turnkey solution.
enable the 71610 to operate as a complete turnkey
In addition to supporting PCI Express as a native solution without the need to develop any FPGA IP.
interface, the Model 71610 includes a general-purpose
The Model 71610 includes an industry-standard
connector for application-specific I/O.
interface fully compliant with PCI Express Gen. 1 bus
The Pentek Cobalt Architecture features a Virtex-6 specifications. Supporting a PCIe x4 or x8 connection,
FPGA. All of the boards data and control paths are the interface includes multiple DMA controllers for
accessible by the FPGA, enabling factory-installed functions efficient transfers to and from the module.
including data transfer and memory control. The Cobalt
Versions of the 71610 are also available as an x8 PCIe
Architecture organizes the FPGA as a container for data
board (Model 78610), 3U VPX (Models 52610 and 53610),
processing applications where each function exists as an
6U VPX (Models 57610 and 58610 dual density), AMC
intellectual property (IP) module.
(Model 56610), 6U cPCI (Models 72610 and 74610 with
Each member of the Cobalt family is delivered with dual density), and 3U cPCI (Model 73610).
factory-installed applications ideally matched to the

51
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Software-Defined Radio Handbook

Products

Digital I/O: Quad Serial FPDP Inter face with Vir


Interface tex-6 FPGA
Virtex-6

Model 71611 - XMC

CH 1 CH 2 CH 3 CH 4
RX TX RX TX RX TX RX TX

FIBER OPTIC FIBER OPTIC FIBER OPTIC FIBER OPTIC


or COPPER or COPPER or COPPER or COPPER
INTERFACE INTERFACE INTERFACE INTERFACE

GTX GTX GTX GTX

VIRTEX-6 FPGA
LX240T, SX315T or SX475T

GTX LVDS

32 32 32 32 16
8X 40
DDR3 DDR3 DDR3 DDR3 Config
SDRAM SDRAM SDRAM SDRAM FLASH
Model 71611 512 MB 512 MB 512 MB 512 MB 64 MB
XMC FPGA
Memory Banks 1 & 2 Memory Banks 3 & 4 x8 PCIe GPIO
DDR3 option 155 DDR3 option 165
(option -104)

P15 P14
XMC PMC

Figure 64

Model 71611 is a member of the Cobalt family of for data processing applications where each function exists
high-performance XMC modules based on the Xilinx as an intellectual property (IP) module.
Virtex-6 FPGA. A multichannel, gigabit serial interface,
IP modules for DDR3 SDRAM memories, controllers
it is ideal for interfacing to serial FPDP data converter boards
for data routing and flow control, CRC support, advanced
or as a chassis-to-chassis data link.
DMA engines, and a PCIe interface complete the factory-
The 71611 is fully compatible with the VITA 17.1 installed functions and enable the 71611 to operate as a
Serial FPDP specification. Its built-in data transfer complete turnkey solution without developing FPGA IP.
features make it a complete turnkey solution. For users
The 71611 is fully compatible with the VITA 17.1
who require application-specific functions, the 71611
Serial FPDP specification. With the capability to support
serves as a flexible platform for developing and
1.0625, 2.125, 2.5, 3.125, and 4.25 Gbaud link rates
deploying custom FPGA processing IP.
and the option for multi-mode and single-mode optical
In addition to supporting PCI Express as a native interfaces, the board can work in virtually any system.
interface, the Model 71611 includes a general purpose Programmable modes include: flow control in both receive
connector for application-specific I/O. and transmit directions, CRC support, and copy/loop.
The Pentek Cobalt Architecture features a Virtex-6 Versions of the 71611 are also available as an x8 PCIe
FPGA. All of the boards data and control paths are board (Model 78611), 3U VPX (Models 52611 and 53611),
accessible by the FPGA, enabling factory-installed func- 6U VPX (Models 57611 and 58611 dual density), AMC
tions including data transfer and memory control. The (Model 56611), 6U cPCI (Models 72611 and 74611 with
Cobalt Architecture organizes the FPGA as a container dual density), and 3U cPCI (Model 73611).

52
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

Vir tex-7 PProcessor


Virtex-7 rocessor and FMC Carrier - FMC

Model 5973 - 3U VPX

FMC
CONNECTOR

160 10X

LVDS GTX

VIRTEX-7 FPGA
VX330T or VX690T

GTX GTX LVDS GTX

CONFIG FPGA 32 32 32 32
FLASH PCIe 12X
Config Gen. 3 x8 4X 16
1 GB pairs FPGA
Bus DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM Gigabit
GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB Serial I/O
CONFIGURATION
MANAGER
FPGA Gigabit FPGA OPTICAL
PCIe Serial I/O LVDS TRANSCEIVER
(Optional)
Model 5973 Gen. 3 x8 GPIO
FMC
VPX-P2 ()
VPX-P0 VPX-P1 VPX-P2 () VITA 66.4
VPX BACKPLANE

See page 27
Figure 65

The Flexor Model 5973 is a high-performance When integrated with a Pentek FMC, the 5973 is
3U VPX board based on the Xilinx Virtex-7 FPGA. As a delivered with factory-installed applications ideally
stand-alone processor board, it provides an ideal matched to the boards analog or digital interfaces.
development and deployment platform for demanding These can include A/D acquisition and D/A waveform
signal-processing applications. playback engines for simplifying data capture and
playback.
The 5973 includes a VITA-57.1 FMC site providing
access to a wide range of I/O options. When combined with Data tagging and metadata packet generation, in
any of Penteks analog interface FMCs, it becomes a conjunction with powerful linked-list DMA engines,
complete multichannel data conversion and processing provide a streamlined interface for moving data on and
subsystem suitable for connection to IF, HF or RF ports off the board and identifying data packets with
of a communications or radar system. channel, timing and sample count information.
The 5973 architecture includes an optional built-in IP modules for DDR3 SDRAM memories, controllers
gigabit serial optical interface. Up to 12 high-speed duplex for all data clocking and synchronization functions, a test
optical lanes are available on an MTP connector. With signal generator, and a PCIe interface complete the
the installation of a serial protocol in the FPGA, this factory-installed functions and enable the 5973 and its
interface enables a high-bandwidth connection between installed FMC to operate as a complete turnkey solution
5973s mounted in the same chassis or even over extended without the need to develop any FPGA IP.
distances between them.

53
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Software-Defined Radio Handbook

Products

PCI Express Vir tex-7 PProcessor


Virtex-7 rocessor and FMC Carrier - FMC

Model 7070 - x8 PCIe

FMC
CONNECTOR

160 10X

LVDS GTX

VIRTEX-7 FPGA
VX330T or VX690T

GTX LVDS GTX

CONFIG FPGA 32 32 32 32
FLASH PCIe 16 12X
Config Gen. 3 x8 pairs
1 GB FPGA
Bus DDR3 DDR3 DDR3 DDR3 Model 7070 shown
SDRAM SDRAM SDRAM SDRAM Gigabit with Model 3312
GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB Serial I/O
CONFIGURATION multichannel A/D &
MANAGER
OPTICAL D/A FMC module
TRANSCEIVER
FPGA (optional)
PCIe LVDS
GPIO To Second Slot
Gen. 3 x8 Front Panel
PCIe Gen 3 x8 Card Edge Connector MTP Connector

See page 27
Figure 66

The Flexor Model 7070 is a high-performance PCIe When integrated with a Pentek FMC, the 7070 is
board based on the Xilinx Virtex-7 FPGA. As a stand- delivered with factory-installed applications ideally matched
alone processor board, it provides an ideal development to the boards analog or digital interfaces. These can
and deployment platform for demanding signal process- include A/D acquisition and D/A waveform playback
ing applications. engines for simplifying data capture and playback.
The 7070 includes a VITA-57.1 FMC site providing Data tagging and metadata packet generation, in
access to a wide range of I/O options. When combined conjunction with powerful linked-list DMA engines,
with any of Penteks analog interface FMCs, it becomes provide a streamlined interface for moving data on and off
a complete multichannel data conversion and processing the board and identifying data packets with channel, timing
subsystem suitable for connection to IF, HF or RF ports and sample-count information.
of a communications or radar system.
IP modules for DDR3 SDRAM memories, controllers
The 7070 architecture includes an optional built-in for all data clocking and synchronization functions, a test
gigabit serial optical interface. Up to 12 high-speed duplex signal generator, and a PCIe interface complete the
optical lanes are available on an MTP connector. With factory-installed functions and enable the 7070 and
the installation of a serial protocol in the FPGA, this installed FMC to operate as a complete turnkey
interface enables a high-bandwidth connection between solution without the need to develop any FPGA IP.
7070s mounted in the same chassis or even over extended
distances between them.

54
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Software-Defined Radio Handbook

Products

4- Channel 250 MHz 16-bit A/D, 2-


4-Channel Channel 800 MHz 16-bit D/A
2-Channel

Model 3312 - FMC

RF In RF In RF In RF In RF Out RF Out

RF RF RF RF RF RF
Sample Clk / XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR
Reference Clk In
TIMING BUS
Gate / Trigger / GENERATOR
Sync / PPS A/D Clock/Sync Bus
250 MHz 250 MHz 250 MHz 250 MHz 800 MHz
Clock / Sync / 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT D/A
Gate / PPS
D/A Clock/Sync Bus DIGITAL
UPCONVERTER
Control
& Status

16 16 16 16 16
VCXO

FMC
Model 3312 CONNECTOR
FMC

Figure 67

The Flexor Model 3312 is a multichannel, high- While users will find the Model 3312 an excellent
speed data converter FMC module. It is suitable for analog interface to any compatible FMC carrier, the true
connection to HF or IF ports of a communications or performance of the 3312 can be unlocked only when used
radar system. It includes four 250 MHz, 16-bit A/Ds, with the Pentek Model 5973 or Model 7070 FMC carriers.
two 800 MHz, 16-bit D/As, programmable clocking,
With factory-installed IP, the board-set provides a
and multiboard synchronization for support of larger
turnkey data acquisition subsystem eliminating the need to
high-channel-count systems.
create any FPGA IP. Installed features include flexible A/D
When combined with either the Model 5973 3U VPX acquisition, programmable linked-list DMA engines, and
or Model 7070 PCIe FMC carrier, the board-set becomes a a D/A waveform playback IP module.
turnkey data acquisition and signal generation solution.
When used with the 5973 or the 7070, the 3312 features a
For applications that require custom processing, the
sophisticated D/A waveform playback IP module. A linked-list
board-set is an ideal IP development and deployment
controller allows users to easily play back to the D/As waveforms
subsystem.
stored in either on-board or off-board host memory.
The front end accepts four analog HF or IF inputs
on front-panel connectors with transformer-coupling into
two Texas Instruments ADS42LB69 Dual 250 MHz,
16-bit A/D converters.

55
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4-Channel 2
Channel 50 MHz A/D
250 A/D,, 2- Channel 800 MHz D/A
2-Channel

3U VPX FlexorSet 5973-312 or x8 PCIe FlexorSet 7070-312


Model 3312 FMC Module

from from from from D/A loopback to


A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 D/A

TEST
SIGNAL
INPUT MULTIPLEXER
GENERATOR

DATA DATA DATA


PACKING PACKING UNPACKING
& FLOW & FLOW & FLOW
CONTROL CONTROL CONTROL

MEMORY MUX A/D MEMORY MUX MUX


CONTROL ACQUISITION CONTROL
IP MODULES
to METADATA 2&3 to METADATA
Mem GENERATOR Mem GENERATOR MEMORY
Bank 1 Bank 4 CONTROL

LINKED-LIST LINKED-LIST to LINKED-LIST


DMA ENGINE DMA ENGINE Mem DMA ENGINE Model 5973-312
Bank 4 D/A
A/D A/D WAVEFORM
ACQUISITION ACQUISITION PLAYBACK
IP MODULE 1 IP MODULE 4 IP MODULE

DETAILS OF VIRTEX-7 FPGA IP


INSTALLED IN MODEL 5973-312 PCIe INTERFACE
to
to to to A/D Acq
A/D Acq A/D Acq A/D Acq Mod 4 &
Module 1 Module 2 Module 3 D/A Mod
32 32 32 32 8X 4X 32
Gigabit FPGA
Memory Memory Memory Memory PCIe Serial I/O GPIO See page 27
Bank 1 Bank 2 Bank 3 Bank 4
Figure 68

Models 5973-312 and 7070-312 are members of the When delivered as an assembled board set, the FlexorSet
Flexor family of high-performance 3U VPX or x8 PCIe includes factory-installed applications ideally matched to
boards based on the Xilinx Virtex-7 FPGA. the boards analog interfaces. The functions include four A/D
acquisition IP modules for simplifying data capture and data
As FlexorSet integrated solutions, the Model 3312
transfer. Each of the four acquisition IP modules contains IP
FMC is factory-installed on the 5973 or 7070 carrier.
modules for DDR3 SDRAM memories.
The required FPGA IP is installed and the board set is
delivered ready for immediate use. Both models feature a sophisticated D/A waveform
playback IP module. A linked-list controller allows users to
The delivered FlexorSet is a multichannel, high-speed
easily play back to the D/As waveforms stored in either on-
data converter and is suitable for connection to the HF or
board or off-board host memory. Parameters including
IF ports of a communications or radar system. Its built-in
length of waveform, delay from playback trigger, waveform
data capture features offer an ideal turnkey solution as well as
repetition, etc. can be programmed for each waveform. Up
a platform for developing and deploying custom FPGA-
to 64 individual link entries can be chained together to
processing IP.
create complex waveforms with a minimum of programming.
Each FlexorSet includes four 250 MHz, 16-bit A/Ds,
A controller for all data clocking and synchronization
one digital upconverter, two 800 MHz, 16-bit D/As, and
functions, a test signal generator, and a PCIe interface
four banks of memory. In addition to supporting PCIe
complete the factory-installed functions and enable these
Gen. 3 as a native interface, these models include optional
models to operate as turnkey solutions without the need
copper and optical connections to the Virtex-7 FPGA for
to develop any FPGA IP.
custom I/O.

56
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Software-Defined Radio Handbook

Products

4-Channel 2
Channel 50 MHz A/D with DDCs, 2-
250 Channel 800 MHz D/A with Extended Interpolation
2-Channel

x8 PCIe FlexorSet 7070-313 or 3U VPX FlexorSet 5973-313


Model 3312 FMC Module

from from from from D/A loopback to


A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 D/A
TEST
SIGNAL
INPUT MULTIPLEXER
GENERATOR

DDC DDC INTERPOLATOR


DEC: 2 TO 65536 DEC: 2 TO 65536 2 TO 65536
POWER POWER IP CORE
METER & METER &
THRESHOLD THRESHOLD DATA UNPACKING
DETECT A/D DETECT & FLOW CONTROL
DDC CORE ACQUISITION DDC CORE
IP MODULES
DATA PACKING & 2&3 DATA PACKING & MUX
FLOW CONTROL FLOW CONTROL
MEMORY MEMORY
CONTROL CONTROL MEMORY
METADATA METADATA
CONTROL
Model 7070-313
to GENERATOR MUX to GENERATOR MUX
Mem Mem to LINKED-LIST
Bank 1 LINKED-LIST Bank 4 LINKED-LIST Mem DMA ENGINE
DMA ENGINE DMA ENGINE
Bank 4 D/A
A/D A/D WAVEFORM
ACQUISITION ACQUISITION PLAYBACK
IP MODULE 1 IP MODULE 4 IP MODULE

DETAILS OF VIRTEX-7 FPGA IP


INSTALLED IN MODEL 5973-313
to PCIe INTERFACE
to to to A/D Acq
A/D Acq A/D Acq A/D Acq Mod 4 &
Module 1 Module 2 Module 3 D/A Mod
32 32 32 32 8X 32
FPGA
Memory Memory Memory Memory PCIe
Bank 1 Bank 2 Bank 3 Bank 4
GPIO See page 27
Figure 69

Models 7070-313 and 5973-313 are members of the When delivered as an assembled board-set, the
Flexor family of high-performance x8 PCIe or 3 U VPX FlexorSet includes factory-installed applications ideally
boards based on the Xilinx Virtex-7 FPGA. matched to the boards analog interfaces. The functions
include four A/D acquisition IP modules for simplifying
As FlexorSet integrated solutions, the Model 3312
data capture and data transfer. Each of the four acquisition
FMC is factory-installed on the 7070 or 5973 carrier.
IP modules contains a programmable DDC core with
The required FPGA IP is installed and the board-set is
decimations from 2 to 65,536.
delivered ready for immediate use.
The decimating filter for each DDC accepts a unique set of
The delivered FlexorSet is a multichannel, high-speed
user-supplied 18-bit coefficients. The 80% default filters deliver
data converter with progammable DDCs and is suitable for
an output bandwidth of 0.8*s/N, where N is the decimation
connection to HF or IF ports of a communications or radar
setting. The rejection of adjacent-band components within the
system. Its built-in data capture and playback features offer
80% output bandwidth is better than 100 dB. Each DDC
an ideal turnkey solution as well as a platform for developing
delivers a complex output stream consisting of 24-bit I + 24-bit
and deploying custom FPGA-processing IP.
Q or 16-bit I + 16-bit Q samples at a rate of s/N.
Each FlexorSet includes four 250 MHz, 16-bit A/Ds,
A controller for all data clocking and synchronization
one digital upconverter, two 800 MHz, 16-bit D/As,
functions, a test signal generator, and a PCIe interface
and four banks of memory. In addition to supporting
complete the factory-installed functions and enable these
PCIe Gen. 3 as a native interface, these models include
models to operate as turnkey solutions without the need
optional copper and optical connections to the Virtex-7
to develop any FPGA IP.
FPGA for custom I/O.

57
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Software-Defined Radio Handbook

Products

8- Channel 250 MHz 16-bit A/D


8-Channel

Model 3316 - FMC

RF In RF In RF In RF In RF In RF In RF In RF In

RF RF RF RF RF RF RF RF
Sample Clk / XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR
Reference Clk In A/D
TIMING BUS
Gate / Trigger / GENERATOR Clock/Sync
Sync / PPS Bus 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz
Clock / Sync / 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D
Gate / PPS

Control
& Status

16 16 16 16 16 16 16 16
VCXO

FMC
CONNECTOR

Model 3316
FMC

Figure 70

The Flexor Model 3316 is a multichannel, high- While users will find the Model 3316 an excellent
speed data converter FMC module. It is suitable for analog interface to any compatible FMC carrier, the true
connection to HF or IF ports of a communications or performance of the 3316 can be unlocked only when used
radar system. It includes eight 250 MHz, 16-bit A/Ds, with the Pentek Model 5973 or Model 7070 carriers.
on-board programmable clocking, and multiboard
With factory-installed IP, the board-set provides a
synchronization for support of larger high-channel-count
turnkey data acquisition subsystem eliminating the need to
systems.
create any FPGA IP. Installed features include flexible A/D
When combined with either the Model 5973 3U acquisition, programmable linked-list DMA engines, and
VPX or Model 7070 PCIe carrier, the board-set becomes a metadata packet creator.
a turnkey data acquisition solution. For applications
When the 3316 is installed on either the 5973 or
that require custom processing, the board-set is an ideal IP
the 7070 FMC carrier, the board-set features eight A/D
development and deployment subsystem
Acquisition IP modules for easily capturing and moving
The front end accepts eight analog HF or IF inputs data. Each module can receive data from any of the eight
on front-panel connectors with transformer-coupling into A/Ds, or a test signal generator.
four Texas Instruments ADS42LB69 Dual 250 MHz,
16-bit A/D converters.

58
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

8-Channel 2
Channel 50 MHz A/D with Vir
250 tex-7 FPGA - 3U VPX
Virtex-7

3U VPX FlexorSet 5973-316 or x8 PCIe FlexorSet 7070-316


Model 3316 FMC Module

from from from from from from from from


A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 A/D Ch 5 A/D Ch 6 A/D Ch 7 A/D Ch 8
TEST
SIGNAL INPUT MULTIPLEXER
GENERATOR

DATA DATA DATA


PACKING PACKING PACKING
& FLOW & FLOW A/D & FLOW
CONTROL CONTROL ACQUISITION CONTROL
IP MODULES
3-7
MEMORY MEMORY MEMORY
CONTROL MUX CONTROL MUX CONTROL MUX

to METADATA to METADATA to METADATA


Mem GENERATOR Mem GENERATOR Mem GENERATOR
Bank 1 Bank 1 Bank 4 Model 5973-316
LINKED-LIST LINKED-LIST LINKED-LIST
DMA ENGINE DMA ENGINE DMA ENGINE
A/D A/D A/D
ACQUISITION ACQUISITION ACQUISITION
IP MODULE 1 IP MODULE 2 IP MODULE 8

DETAILS OF VIRTEX-7 FPGA IP PCIe INTERFACE


to to to to
A/D Acq A/D Acq A/D Acq A/D Acq
INSTALLED IN MODEL 5973-316
Mod 1 & 2 Mod 3 & 4 Mod 5 & 6 Mod 7 & 8
32 32 32 32 4X 32 8X
Memory Memory Memory Memory Gigabit FPGA
PCIe
Bank 1 Bank 2 Bank 3 Bank 4 Serial I/O GPIO See page 27
Figure 71

Models 5973-316 and 7070-316 are members of the When delivered as an assembled board-set, the
Flexor family of high-performance 3U VPX or x8 PCIe FlexorSet includes factory-installed applications ideally
boards based on the Xilinx Virtex-7 FPGA. matched to the boards analog interfaces. These functions
include eight A/D acquisition IP modules for simplifying
As FlexorSet integrated solutions, the Model 3316
data capture and transfer.
FMC is factory-installed on the 5973 or 7070 carrier.
The required FPGA IP is installed and the board-set is Each of the eight acquisition IP modules contains IP
delivered ready for immediate use. modules for DDR3 SDRAM memories. A controller
for all data clocking and synchronization functions, a
The delivered FlexorSet is a multichannel, high-speed
test signal generator, and a PCIe interface complete the
data converter and is suitable for connection to the HF or
factory-installed functions and enable these models to
IF ports of a communications or radar system. Its built-in
operate as turnkey solutions without the need to develop
data capture features offer an ideal turnkey solution as well
any FPGA IP.
as a platform for developing and deploying custom FPGA-
processing IP. For applications that require specialized functions,
users can install their own custom IP for data processing.
Each FlexorSet includes eight A/Ds and four banks of
Pentek GateFlow FPGA Design Kits include all of the
memory. In addition to supporting PCIe Gen. 3 as a
factory-installed modules as documented source code.
native interface, these models include optional copper and
Developers can integrate their own IP with the Pentek
optical connections to the Virtex-7 FPGA for custom I/O.
factory-installed functions or use the GateFlow kit to
completely replace the Pentek IP with their own.

59
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

8-Channel 2
Channel 50 MHz A/D with Digital Downconver
250 ters - x8 PCIe
Downconverters

x8 PCIe FlexorSet 7070-317 or 3U VPX FlexorSet 5973-317


Model 3316 FMC Module

from from from from from from from from


A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 A/D Ch 5 A/D Ch 6 A/D Ch 7 A/D Ch 8
TEST
SIGNAL INPUT MULTIPLEXER
GENERATOR

DDC DDC DDC


DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536
POWER POWER POWER
METER & METER & METER &
THRESHOLD THRESHOLD THRESHOLD
DETECT DETECT A/D DETECT
DDC CORE DDC CORE ACQUISITION DDC CORE
IP MODULES
DATA PACKING & DATA PACKING & 3-7 DATA PACKING &
FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL
METADATA METADATA METADATA
to GENERATOR MUX to GENERATOR MUX to GENERATOR MUX
Mem Mem Mem Model 7070-317
Bank 1 LINKED-LIST Bank 1 LINKED-LIST Bank 4 LINKED-LIST
DMA ENGINE DMA ENGINE DMA ENGINE
A/D A/D A/D
ACQUISITION ACQUISITION ACQUISITION
IP MODULE 1 IP MODULE 2 IP MODULE 8

DETAILS OF VIRTEX-7 FPGA IP


to to to to PCIe INTERFACE
INSTALLED IN MODEL 7070-317
A/D Acq A/D Acq A/D Acq A/D Acq
Mod 1 & 2 Mod 3 & 4 Mod 5 & 6 Mod 7 & 8
32 32 32 32 32 8X
Memory Memory Memory Memory FPGA
PCIe
Bank 1 Bank 2 Bank 3 Bank 4 GPIO See page 27
Figure 72

Models 7070-317 and 5973-317 are members of the When delivered as an assembled board-set, the
Flexor family of high-performance x8 PCIe or 3U VPX FlexorSet includes factory-installed applications ideally
boards based on the Xilinx Virtex-7 FPGA. matched to the boards analog interfaces. The functions
include eight A/D acquisition IP modules for simplifying
As FlexorSet integrated solutions, the Model 3316
data capture and data transfer.
FMC is factory-installed on the 7070 or 5973 carrier.
The required FPGA IP is installed and the board-set is Within each A/D Acquisition IP Module is a powerful
delivered ready for immediate use. DDC IP core. Each DDC has an independent 32-bit
tuning frequency setting that ranges from DC to s, where
The delivered FlexorSet is a multichannel, high-speed
s is the A/D sampling frequency. Each DDC can have
data converter with programmable DDCs (Digital
its own unique decimation setting, supporting as many as
Downconverters) and is suitable for connection to the
eight different output bandwidths for the board. Decimations
HF or IF ports of a communications or radar system. Its
can be programmed from 2 to 65,536 providing a wide range
built-in data capture features offer an ideal turnkey solution
to satisfy most applications.
as well as a platform for developing and deploying custom
FPGA-processing IP. The decimating filter for each DDC accepts a
unique set of user-supplied 18-bit coefficients. The 80%
Each FlexorSet includes eight A/Ds and four banks of
default filters deliver an output bandwidth of 0.8*s/N,
memory. In addition to supporting PCIe Gen. 3 as a
where N is the decimation setting. The rejection of
native interface, these models include optional copper and
adjacent-band components within the 80% output
optical connections to the Virtex-7 FPGA for custom I/O.
bandwidth is better than 100 dB.

60
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Software-Defined Radio Handbook

Products

2- Channel 3.0 GHz A/D, 2-


2-Channel Channel 2.8 GHz D/A - FMC
2-Channel

Model 3320 - FMC

RF In RF In RF Out RF Out

Sample Clk /
RF RF RF RF
Reference Clk In
XFORMR XFORMR XFORMR XFORMR

TIMING BUS
Gate / Trigger / A/D
Sync / PPS
GENERATOR
Clock/Sync 3.0 GHz* 3.0 GHz*
Bus 14-BIT A/D 14-BIT A/D
Clock / Sync / DIGITAL DIGITAL 2.8 GHz* 2.8 GHz*
Gate / PPS D/A
Clock/Sync DOWNCONVERT DOWNCONVERT 16-BIT D/A 16-BIT D/A
Bus DIGITAL DIGITAL
UPCONVERT UPCONVERT
Control
& Status

VCXO

FMC CONNECTOR

Model 3320
FMC

Figure 73

The Flexor Model 3320 is a multichannel, high-speed Designed to allow users to optimize data conversion
data converter FMC. It is suitable for connection to RF or rates and modes for specific application requirements, the
IF ports of a communications or radar system. It includes FlexorSet provides preconfigured conversion profiles.
two 3.0 GHz A/Ds, two 2.8 GHz D/As, programmable Users can use these profiles which include: digital down-
clocking and multiboard synchronization for support of converter and digital upconverter modes, conversion resolution
larger high-channel-count systems. and A/D and D/A sample rates, or program their own
profiles. In addition to supporting PCIe Gen. 3 as a
When combined with either the Model 5973 3U
native interface, the FlexorSet includes optional copper
VPX or Model 7070 PCIe carrier, the board-set becomes
and optical connections to the Virtex-7 FPGA for custom I/O.
a turnkey data acquisition solution. For applications
that require custom processing, the board-set is an ideal IP The front end accepts two analog RF or IF inputs
development and deployment subsystem. on front-panel connectors with transformer-coupling into a
Texas Instruments ADC32RF45 dual channel A/D. With
The true performance of the 3320 can be unlocked
dual built-in digital downconverters and programmable
only when used with the Pentek Model 5973 or Model
decimations, the converter serves as an ideal interface for a
7070 FMC carriers. With factory-installed IP, the board-
range of radar, signal intelligence and electronic counter-
set provides a turnkey data acquisition subsystem eliminating
measures applications.
the need to create any FPGA IP. Installed features
include flexible A/D acquisition, programmable With the 3320 installed on either the 5973 or the
linked-list DMA engines, and D/A waveform playback 7070 carrier, the board-set features two A/D Acquisition IP
IP modules. modules for easily capturing and moving data.

61
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Software-Defined Radio Handbook

Products

2- Channel 3.0 GHz A/D, 2-


2-Channel Channel 2.8 GHz D/A - FMC
2-Channel

3U VPX FlexorSet 5973-320 or x8 PCIe FlexorSet 7070-320


Model 3320 FMC Module

From From To To
A/D Ch 1 A/D Ch 2 D/A Ch 1 D/A Ch 2
D/A loopback
D/A loopback TEST
SIGNAL
INPUT MULTIPLEXER GENERATOR

DATA DATA DATA DATA


PACKING PACKING UNPACKING UNPACKING
& FLOW & FLOW & FLOW & FLOW
CONTROL CONTROL CONTROL CONTROL

MEMORY MEMORY MUX MUX MUX


MUX
CONTROL CONTROL

to METADATA to METADATA
Mem GENERATOR Mem GENERATOR MEMORY MEMORY
Bank Bank CONTROL CONTROL

LINKED-LIST LINKED-LIST to LINKED-LIST


DMA ENGINE
to LINKED-LIST
DMA ENGINE
Model 5973-320
DMA ENGINE DMA ENGINE Mem Mem
Bank D/A Bank D/A
A/D A/D WAVEFORM WAVEFORM
ACQUISITION ACQUISITION PLAYBACK PLAYBACK
IP MODULE 1 IP MODULE 2 IP MODULE 1 IP MODULE 2

DETAILS OF VIRTEX-7 FPGA IP


INSTALLED IN MODEL 5973-320 PCIe INTERFACE

To Acquisition / To Acquisition /
Playback Playback
Module Module
32 8X 4X 32 Memory 32 Memory
FPGA Gigabit
GPIO PCIe Serial I/O Banks 1 & 2 Banks 3 & 4
See page 27
Figure 74

Models 5973-320 and 7070-320 are members of the and D/A sample rates, or program their own profiles. In
Flexor family of high-performance 3U VPX or x8 PCIe addition to supporting PCIe Gen. 3 as a native interface,
boards based on the Xilinx Virtex-7 FPGA. these models include optional copper and optical connec-
tions to the Virtex-7 FPGA for custom I/O.
As a FlexorSet integrated solution, the Model 3320
FMC is factory-installed on the 5973 or 7070 carrier. When delivered as an assembled board-set, these
The required FPGA IP is installed and the board-set is models include factory-installed applications ideally
delivered ready for immediate use. matched to the boards analog interfaces. The functions
include two A/D acquisition IP modules for simplifying
The delivered FlexorSet is a multichannel, high-speed
data capture and data transfer.
data converter and is suitable for connection to the RF or
IF ports of a communications or radar system. Its built-in Each of the acquisition IP modules contains IP
data capture and playback features offer an ideal turnkey modules for DDR3 SDRAM memories.
solution as well as a platform for developing and deploy-
Both FlexorSets feature two sophisticated D/A wave-form
ing custom FPGA- processing IP.
playback IP modules. A linked-list controller allows
Designed to allow users to optimize data conversion users to easily play back to the D/As waveforms stored
rates and modes for specific application requirements, the in either on-board or off-board host memory. Param-
FlexorSet provides preconfigured conversion profiles. Users eters including length of waveform, delay from playback
can use these profiles which include: digital downconverter trigger, waveform repetition, etc. can be programmed
and digital upconverter modes, conversion resolution and A/D for each waveform.

62
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4- Channel 500 MHz 16-bit A/D, 4-


4-Channel Channel 2 GHz 16-bit D/A
4-Channel

Model 3324 - FMC

RF In RF In RF In RF In RF Out RF Out RF Out RF Out

Sample Clk /
RF RF RF RF RF RF RF RF
Reference Clk In
XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR

TIMING BUS A/D


Gate / Trigger /
GENERATOR Clock/Sync
Sync / PPS
Bus 500 MHz 500 MHz 500 MHz 500 MHz
Clock / Sync / 2 GHz 2 GHz 2 GHz 2 GHz
D/A 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D
Gate / PPS 16-BIT D/A 16-BIT D/A 16-BIT D/A 16-BIT D/A
Clock/Sync
Bus DIGITAL DIGITAL DIGITAL DIGITAL
UPCONVERT UPCONVERT UPCONVERT UPCONVERT
Control
& Status

VCXO

FMC
CONNECTOR

Model 3324
FMC

Figure 75

The Flexor Model 3324 is a multichannel, high-speed performance of the 3324 can be unlocked only when used
data converter FMC. It is suitable for connection to HF or with the Pentek Model 5973 or Model 7070 carriers.
IF ports of a communications or radar system. It includes
With factory-installed IP, the board-set provides a
four 500 MHz, 16-bit A/Ds, four 2 GHz, 16-bit D/As,
turnkey data acquisition and signal generation subsystem,
programmable clocking, and multi-board synchroniza-
eliminating the need to create any FPGA IP. Installed
tion for support of larger high-channel-count systems.
features include flexible A/D acquisition engines, D/A waveform
When combined with either the Model 5973 3U playback engines, programmable linked-list DMA engines,
VPX or Model 7070 PCIe FMC carrier, the board-set and a metadata-packet creator.
becomes a turnkey data acquisition solution. For
The board-set features four A/D Acquisition IP Modules
applications that require custom processing, the board-set
for easily capturing and moving data. Each module can receive
is an ideal IP development and deployment subsystem.
data from any of the four A/Ds, a test signal generator or from
The front end accepts four analog HF or IF inputs the D/A waveform playback IP module in loopback mode.
on front-panel connectors with transformer-coupling into
When used with a Pentek FMC carrier, the 3324
four 500 MHz, 16-bit A/D converters.
features four sophisticated D/A waveform playback IP
While users will find the Model 3324 an excellent modules. A linked-list controller allows users to easily
analog interface to any compatible FMC carrier, the true play back via the D/As waveforms stored in either on-
board or off-board host memory.

63
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

4-Channel 500 MHz 16-bit A/D


Channel A/D,, 4- Channel 2 GHz 16-bit D/A - x8 PCIe
4-Channel

x8 PCIe FlexorSet 7070-324 or 3U VPX FlexorSet 5973-324


Model 3324 FMC Module

From From From From To To To To


A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 D/A Ch 1 D/A Ch 2 D/A Ch3 D/A loopback D/A Ch 4

D/A loopback TEST


SIGNAL
INPUT MULTIPLEXER GENERATOR

DATA DATA DATA DATA


PACKING PACKING UNPACKING D/A UNPACKING
A/D
& FLOW & FLOW & FLOW WAFEFORM & FLOW
ACQUISITION
CONTROL CONTROL CONTROL PLAYBACK CONTROL
IP MODULES
IP MODULES
2&3
2&3
MEMORY MUX MEMORY MUX MUX MUX
CONTROL 2 goes to CONTROL 2 goes to
Mem Bank 1
Mem Bank 3
to METADATA 3 goes to to METADATA 3 goes to
GENERATOR Mem Bank 2 GENERATOR
Mem Mem MEMORY Mem Bank 4 MEMORY
Bank 1 Bank 2 CONTROL CONTROL Model 7070-324
LINKED-LIST LINKED-LIST to LINKED-LIST to LINKED-LIST
DMA ENGINE DMA ENGINE Mem DMA ENGINE Mem DMA ENGINE
Bank 3 D/A Bank 4 D/A
A/D A/D WAVEFORM WAVEFORM
ACQUISITION ACQUISITION PLAYBACK PLAYBACK
IP MODULE 1 IP MODULE 4 IP MODULE 1 IP MODULE 4

DETAILS OF VIRTEX-7 FPGA IP


INSTALLED IN MODEL 7070-324 PCIe INTERFACE

To A/D Acq To A/D Acq To D/A Playback To D/A Playback


Modules 1 & 2 Modules 3 & 4 Modules 1 & 2 Modules 3 & 4
32 Memory 32 Memory 32 8X 32 Memory 32 Memory
FPGA
Bank 1 Bank 2 GPIO PCIe Bank 3 Bank 4 See page 27

Figure 76

Models 7070-324 and 5973-324 are members of the When delivered as an assembled board-set, these models
Flexor family of high-performance x8 PCIe or 3U VPX include factory-installed applications ideally matched to the
boards based on the Xilinx Virtex-7 FPGA. boards analog interfaces. The functions include four A/D
acquisition IP modules for simplifying data capture and data
As a FlexorSet integrated solution, the Model 3324
transfer. Each of the four acquisition IP modules contains IP
FMC is factory-installed on the 7070 or 5973 carrier.
modules for DDR3 SDRAM memories.
The required FPGA IP is installed and the board-set is
delivered ready for immediate use. Each FlexorSet features four sophisticated D/A waveform
playback IP modules. A linked-list controller allows users
The delivered FlexorSet is a multichannel, high-speed
to easily play back to the D/As waveforms stored in either
data converter and is suitable for connection to the HF or
on-board or off-board host memory. Parameters including
IF ports of a communications or radar system. Its built-in
length of waveform, delay from playback trigger, waveform
data capture and playback features offer an ideal turnkey
repetition, etc. can be programmed for each waveform. In each
solution as well as a platform for developing and deploy-
playback module, up to 64 individual link entries can be
ing custom FPGA-processing IP.
chained together to create complex waveforms with a
Each FlexorSet includes four 500 MHz, 16-bit A/Ds, minimum of programming.
four digital upconverters, four 2 GHz, 16-bit D/As, and four
A controller for all data clocking and synchronization
banks of memory. In addition to supporting PCIe Gen. 3 as
functions, a test signal generator and a PCIe interface complete
a native interface, these models include optional copper and
the factory-installed functions and enable these models to operate
optical connections to the Virtex-7 FPGA for custom I/O.
as turnkey solutions without the need to develop any FPGA IP.

64
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

PC Development System for PCIe Cobalt, Onyx and Flexor Boards

Model 8266

Model 8266

Figure 77

The Model 8266 is a fully-integrated PC develop- control over hardware, and Penteks Signal Analyzer, a
ment system for Pentek Cobalt, Onyx and Flexor PCI full-featured analysis tool that continuously displays live
Express software radio, data acquisition, and I/O boards. signals in both time and frequency domains.
It was created to save engineers and system integrators
Built on a professional 4U rackmount workstation,
the time and expense associated with building and testing a
the 8266 is equipped with the latest Intel processor,
development system that ensures optimum performance
DDR3 SDRAM and a high-performance motherboard.
of Pentek boards.
These features accelerate application code development
A fully-integrated system-level solution, the 8266 and provide unhindered access to the high-bandwidth
provides the user with a streamlined out-of-the-box data available with Cobalt, Onyx and Flexor analog and
experience. It comes preconfigured with Pentek hardware, digital interfaces. The 8266 can be configured with
drivers and software examples installed and tested to allow 64-bit Windows or Linux operating systems.
development engineers to run example applications out
The 8266 uses a 19 4U rackmount chassis that
of the box.
is 21 deep. Enhanced forced-air ventilation assures
Pentek ReadyFlow drivers and board support adequate cooling for Pentek boards. A 1000-W power
libraries are preinstalled and tested with the 8266. supply guarantees more than enough power for addi-
ReadyFlow includes example applications with full tional boards.
source code, a command line interface for custom

65
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

3U OpenVPX Development System for Cobalt, Onyx and Flexor Boards

Model 8267

Model 8267

Figure 78

The Model 8267 is a fully-integrated, 3U OpenVPX hardware, and Penteks Signal Analyzer, a full-featured
development system for Pentek Cobalt, Onyx and Flexor analysis tool that continuously displays live signals in
software radio, data acquisition, and I/O boards. It was both time and frequency domains.
created to save engineers and system integrators the time
Built on a professional 4U rackmount workstation,
and expense associated with building and testing a develop-
the 8267 is equipped with the latest Intel i7 processor,
ment system that ensures optimum performance of
DDR3 SDRAM and a high-performance single-board
Pentek boards.
computer. These features accelerate application code
A fully-integrated system-level solution, the 8267 development and provide unhindered access to the high-
provides the user with a streamlined out-of-the-box bandwidth data available with Cobalt, Onyx and Flexor
experience. It comes preconfigured with Pentek hardware, analog and digital interfaces. The 8267 can be config-
drivers and software examples installed and tested to allow ured with 64-bit Windows or Linux operating systems.
development engineers to run example applications out
The 8267 uses a 19 4U rackmount chassis that is
of the box.
12 deep. Nine VPX slots provide ample space for an
Pentek ReadyFlow drivers and board support libraries SBC, a switch card and multiple Pentek boards. Enhanced
are preinstalled and tested with the 8267. ReadyFlow forced-air ventilation assures adequate cooling for all
includes example applications with full source code, a boards and dual 250-W power supplies gurantee more
command line interface for custom control over than adequate power for all installed boards.

66
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Products

6U OpenVPX Development System for Cobalt and Onyx Boards

Model 8264

Model 8264
with 6U VPX Boards

Figure 79

The Model 8264 is a fully-integrated, 6U OpenVPX hardware, and Penteks Signal Analyzer, a full-featured
development system for Pentek Cobalt and Onyx soft- analysis tool that continuously displays live signals in
ware radio, data acquisition, and I/O boards. It was both time and frequency domains.
created to save engineers and system integrators the time
Built on a professional 6U rackmount workstation,
and expense associated with building and testing a develop-
the 8264 is equipped with the latest Intel i7 processor,
ment system that ensures optimum performance of
DDR3 SDRAM and a high-performance single-board
Pentek boards.
computer. These features accelerate application code
A fully-integrated system-level solution, the 8264 development and provide unhindered access to the high-
provides the user with a streamlined out-of-the-box bandwidth data available with Cobalt and Onyx analog
experience. It comes preconfigured with Pentek hardware, and digital interfaces. The 8264 can be configured with
drivers and software examples installed and tested to allow 64-bit Windows or Linux operating systems.
development engineers to run example applications out
The 8264 uses a 19 6U rackmount chassis that is
of the box.
12 deep. Nine VPX slots provide ample space for an
Pentek ReadyFlow drivers and board support libraries SBC, a switch card and multiple Pentek boards. Enhanced
are preinstalled and tested with the 8264. ReadyFlow forced-air ventilation assures adequate cooling for all
includes example applications with full source code, a boards and dual 500-W power supplies gurantee more
command line interface for custom control over than adequate power for all installed boards.

67
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Complementar
Complementaryy PProducts
roducts

Bandit TTwo
wo
wo--Channel Analog RF W ideband Downconver
Wideband ter
Downconverter

Model 7820 - PCIe

LOWPASS I
LOW LOW LOW IF I Out
OR I/Q
RF In NOISE NOISE NOISE
BANDPASS DOWNCONVERTER Q
AMP AMP AMP IF Q Out
FILTER
(optional)
Gain 1 Control Gain 2 Control
SYNTHESIZER

Tuning Control
Ref In OVEN
CONTROLLED
Gain 1 Control Ref Out
REFERENCE
USB Gain 2 Control
USB OSCILLATOR
INTERFACE
Tuning Control (option 015)
Tuning Control

SYNTHESIZER
Gain 1 Control Gain 2 Control Model 7820 PCIe

LOWPASS I
LOW LOW LOW IF I Out
OR I/Q
RF In NOISE NOISE NOISE
BANDPASS DOWNCONVERTER Q
AMP AMP AMP IF Q Out
FILTER
(optional)

Figure 80

The Bandit Model 7820 is a two-channel, high- suppression. The 7820 features a pair of Analog
performance, stand-alone analog RF wideband down- Devices ADL5380 quadrature mixers. The ADL5380s
converter. Packaged in a small, shielded PCIe board are capable of excellent accuracy with amplitude and phase
with front-panel connectors for easy integration into RF balances of ~0.07 dB and ~0.2, respectively.
systems, the board offers programmable gain, high
The 7820 uses an Analog Devices ADF4351 low-
dynamic range and a low noise figure.
noise, on-board frequency synthesizer as the LO (Local
With an input frequency range from 400 to 4000 Oscillator). Locked to an external input reference for
MHz and a wide IF bandwidth of up to 390 MHz, the accuracy with a fractional-N phase-locked loop, its
7820 is an ideal solution for amplifying and downconverting frequency is programmable across the 400 to the 4000 MHz
antenna signals for communications, radar and SIGINT. band with a tuning resolution of better than 100 kHz.
The 7820 accepts RF signals on two front-panel Output is provided as baseband I and Q signals at
SSMC connectors. LNAs (Low Noise Amplifiers) are bandwidths up to 390 MHz. User-provided in-line output
provided, along with two programmable attenuators IF filters allow customizing the output bandwidth and
allowing downconversion of input signals ranging from offset frequency to the specific application requirements.
60 dBm to 20 dBm in steps of 0.5 dB. Higher level
Versions of the 7820 are also available as an XMC
signals can be attenuated prior to input. An optional
module (Model 7120), 3U VPX (Models 5220 and 5320),
five-stage lowpass or bandpass input filter can be
6U VPX (Models 5720 and 5820 with dual density),
included with several available frequency and attenuation
AMC (Model 5620), 6U cPCI (Models 7220 and 7420
characteristics for RF image rejection and harmonic
with dual density), and 3U cPCI (Model 7320).

68
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Software-Defined Radio Handbook

Complementar
Complementaryy PProducts
roducts

Bandit Modular Analog RF Downconver ter Series


Downconverter

Model 8111

RF In IF Out
LOW BANDPASS GAIN GAIN GAIN
STEP STEP
NOISE BLOCK MIXER BLOCK IF FILTER BLOCK
FILTER ATTENUATOR ATTENUATOR
AMP

GAIN
Control BLOCK
RF Attenuation
In
USB IF Attenuation
INTERFACE LO Select
LO Synthesizer Tuning Frequency RF SWITCH

OVEN
CONTROLLED
LO CRYSTAL
OSCILLATOR

Ext
Ref Ref
LO
In Out
In

Model 8111
Figure 81

The Bandit Model 8111 provides a series of high-performance, Seven different input-frequency band options are
stand-alone RF slot receiver modules. Packaged in a small, offered, each tunable across a 400 MHz band, with an
shielded enclosure with connectors for easy integration overlap of 100 MHz between adjacent bands. As a group,
into RF systems, the modules offer programmable gain, high these seven options accommodate RF input signals from
dynamic range and a low noise figure. With input options 800 MHz to 3.000 GHz as follows:
to cover specific frequency bands of the RF spectrum, and Option Frequency Band
an IF output optimized for A/D converters, the 8111 is an 001 800-1200 MHz
ideal solution for amplifying and downconverting antenna 002 1100-1500 MHz
signals for communications, radar and signal intelligence 003 1400-1800 MHz
systems. 004 1700-2100 MHz
005 2000-2400 MHz
The 8111 accepts RF signals on a front panel SMA
006 2300-2700 MHz
connector. An LNA (Low Noise-figure Amplifier) is
007 2600-3000 MHz
provided along with two programmable attenuators
An 80 MHz wide IF output is provided at a 225 MHz
allowing downconversion of input signals ranging from
center frequency. This output is suitable for A/D
60 dBm to 20 dBm in steps of 0.5 dB. Higher level
conversion using Pentek high-performance signal
signals can be attenuated prior to input.
acquisition products, such as those in the Cobalt and
Onyx families.

69
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Software-Defined Radio Handbook

Complementar
Complementaryy PProducts
roducts

Multifrequency Clock Synthesizer

Model 7190 - PMC

Reference Clock Out


In CLOCK 1 Out
SYNTHESIZER 1
2
QUAD AND JITTER 4 In C
VCXO CLEANER 8 Clock Out
R 2
A A 16
O
S
Clock Out
S Out
CLOCK 3
1 B
SYNTHESIZER 2 A Clock Out
QUAD AND JITTER 4 In
CLEANER
R 4
VCXO 8
B B 16
S
Clock Out
W Out
5
I
CLOCK 1
SYNTHESIZER T Clock Out
2
AND JITTER 4 C 6
QUAD In
CLEANER 8 H
VCXO
C C 16 Clock Out
Out
7
Supports:
CLOCK any In to any Out,
1
SYNTHESIZER 2 any In to multiple
QUAD AND JITTER 4 In Outs
VCXO CLEANER 8 Clock Out
D 16 Out
Model 7190 D 8
PMC Control
PCI INTERFACE
PCI BUS
32 (32 Bits / 66 MHz)

Figure 82

Model 7190 generates up to eight synthesized clock The CDC7005 includes phase-locking circuitry
signals suitable for driving A/D and D/A converters in that locks the frequency of its associated VCXO to an input
high-performance real-time data acquisition and software reference of 5 MHz to 100 MHz.
radio systems. The clocks offer exceptionally low phase noise
Eight front panel SMC connectors supply synthesized
and jitter to preserve the signal quality of the data converters.
clock outputs driven from the five clock output drivers.
These clocks are synthesized from on-board quad VCXOs
This supports a single identical clock to all eight outputs or
and can be phase-locked to an external reference signal.
up to five different clocks to various outputs. With four
The 7190 uses four Texas Instruments CDC7005 clock independent quad VCXOs and each CDC7005 capable
synthesizer and jitter cleaner devices. Each CDC7005 is paired of providing up to five different submultiple clocks, a
with a dedicated VCXO to provide the base frequency for wide range of clock configurations is possible. In systems
the clock synthesizer. Each of the four VCXOs can be where more than five different clock outputs are required
independently programmed to generate one of four frequen- simultaneously, multiple 7190s can be used and phase-
cies between 50 MHz and 700 MHz. locked with the 5 MHz to 100 MHz system reference.
The CDC7005 can output the selected frequency Versions of the 7190 are also available as a PCIe half-
of its associated VCXO, or generate submultiples using length board (Model 7890), 3U VPX board (Model
divisors of 2, 4, 8 or 16. The four CDC7005s can output 5390), 6U VPX (Models 5790 and 5890 with dual
up to five frequencies each. The 7190 can be programmed to density), AMC (Model 5690) PCI board (Model 7690),
route any of these 20 frequencies to the modules five 6U cPCI (Models 7290 and 7290D dual density), or 3U
output drivers. cPCI (Model 7390).

70
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Programmable Multifrequency Clock Synthesizer

Model 7191 - PMC

Reference Clock Out


In CLOCK 1 Out
SYNTHESIZER 1
2
PROGRAM AND JITTER 4 In C
VCXO CLEANER 8 Clock Out
R 2
A A 16
O
S
Clock Out
S Out
CLOCK 3
1 B
SYNTHESIZER 2 A Clock Out
PROGRAM AND JITTER 4 In
CLEANER
R 4
VCXO 8
B B 16
S
Clock Out
W Out
5
I
CLOCK 1
SYNTHESIZER T Clock Out
2
AND JITTER 4 C 6
PROGRAM In
CLEANER 8 H
VCXO
C C 16 Clock Out
Out
7
Supports:
CLOCK any In to any Out,
1
SYNTHESIZER 2 any In to multiple
PROGRAM AND JITTER 4 In Outs
VCXO CLEANER 8 Clock Out
D 16 Out
Model 7191 D 8
PMC Control
PCI INTERFACE
PCI BUS
32 (32 Bits / 66 MHz)

Figure 83

Model 7191 generates up to eight synthesized clock The CDC7005 includes phase-locking circuitry
signals suitable for driving A/D and D/A converters in that locks the frequency of its associated VCXO to an input
high-performance real-time data acquisition and software reference of 5 MHz to 100 MHz.
radio systems. The clocks offer exceptionally low phase noise
Eight front panel SMC connectors supply synthesized
and jitter to preserve the signal quality of the data converters.
clock outputs driven from the five clock output drivers.
These clocks are synthesized from programmable VCXOs
This supports a single identical clock to all eight outputs or
and can be phase-locked to an external reference signal.
up to five different clocks to various outputs. With four
The 7191 uses four Texas Instruments CDC7005 clock programmable VCXOs and each CDC7005 capable of
synthesizer and jitter cleaner devices. Each CDC7005 is paired providing up to five different submultiple clocks, a
with a dedicated VCXO to provide the base frequency for wide range of clock configurations is possible. In systems
the clock synthesizer. Each of the four VCXOs can be where more than five different clock outputs are required
independently programmed to a desired frequency between simultaneously, multiple 7191s can be used and phase-
50 MHz and 700 MHz with 32-bit tuning resolution. locked with the 5 MHz to 100 MHz system reference.
The CDC7005 can output the programmed frequency Versions of the 7191 are also available as a PCIe half-
of its associated VCXO, or generate submultiples using length board (Model 7891), 3U VPX board (Model
divisors of 2, 4, 8 or 16. The four CDC7005s can output 5391), 6U VPX (Models 5791 and 5891 with dual
up to five frequencies each. The 7191 can be programmed to density),AMC (Model 5691), PCI board (Model 7691),
route any of these 20 frequencies to the modules five 6U cPCI (Models 7291 and 7291D dual density), or 3U
output drivers. cPCI (Model 7391).

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High-Speed Synchronizer and Distribution Board

Model 7192 - PMC/XMC

PROGRAMMABLE
VCXO
Sample Clk /
Reference
Clk In Clk
MUX In Clock /
Calibration Out
PLL
:N
&
DIVIDER
:N
Ref mSync 1
In Reference Clk In *
TWSI Control In
TWSI
CONTROL Gate / Trigger Out
Sync Out
Reference Clk Out

mSync 2
Gate / Trigger Out
Sync Out
Clk/ Reference Clk Out
MUX Ref
In BUFFER mSync 3
Gate / Trigger In &
Trig/ Gate / Trigger Out
Gate PROGRAM
Model 7192 In DELAYS Sync Out
Sync In Reference Clk Out
PMC/XMC Sync
In mSync 4
Gate / Trigger Out
Sync Out
* For 71640 A/D calibration Reference Clk Out

Figure 84

The Model 7192 High-Speed Synchronizer and The 7192 provides four front panel Sync output
Distribution Board synchronizes multiple Pentek Cobalt connectors, compatible with a range of high-speed
or Onyx modules within a system. It enables synchronous Pentek Cobalt and Onyx modules. The Sync signals
sampling and timing for a wide range of multichannel include a reference clock, gate/trigger and sync signals and are
high-speed data acquisition, DSP, and software radio distributed through matched cables, simplifying system
applications. Up to four modules can be synchronized design. The 7192 features a calibration output specifi-
using the 7192, with each receiving a common clock cally designed to work with the 71640 or 71740
along with timing signals that can be used for synchro- 3.6 GHz A/D module and provide a signal reference for
nizing, triggering and gating functions. phase adjustment across multiple D/As.
Model 7192 provides three front panel MMCX The 7192 supports all high-speed models in the Cobalt
connectors to accept input signals from external sources: and Onyx families including the 71630/71730 1 GHz A/D
one for clock, one for gate or trigger and one for a synchro- and D/A XMC, the 71640/71741 3.6 GHz A/D XMC
nization signal. Clock signals can be applied from an and the 71670/71771 Four-channel 1.25 GHz, 16-bit
external source such as a high performance sine-wave D/A XMC.
generator. Gate/trigger and sync signals can come from
Versions of the 7192 are also available as a PCIe half-
an external system source. In addition to the MMCX
length board (Model 7892), 3U VPX (Model 5292), 6U
connector, a reference clock can be accepted through the
VPX (Models 5792 and 5892 with dual density),
first front panel Sync output connector, allowing a
AMC (Model 5692), 6U cPCI (Models 7292 and 7492
single Cobalt or Onyx board to generate the clock for
dual density), and 3U cPCI (Model 7392).
all subsequent boards in the system.

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System Synchronizer and Distribution Board

Model 7893 - Half-length PCIe


Sample Clk /
Reference Clk In :N
Sample Clk A Clock Out 1
MUX CLK :N
IN
PLL :N
& Clock Out 2
:
DIVIDER N Sample Clk B
:N
REF
Sample Clk A CLK CONTROL Clock Out 3
IN VOLTAGE
Sample Clk B
Gate / Trig A
Gate / Trig B Clock Out 4
Sync / PPS A PROGRAM
Sync / PPS B VCXO
Timing Bus In
Timing Bus Out 1
Control Sample Clk A
USB Sample Clk B
USB USB Gate / Trig
INTERFACE Gate / Trig A
USB Sync / PPS Gate / Trig B
Sample Clk A Sync / PPS A
Sync / PPS B
Sample Clk B

MUX Gate / Trig A BUFFER


USB Gate / Trig Timing Bus Out 2
TTL &
MUX through
Gate / Trig In PROGRAM
Timing Bus Out 7
Model 7893
DELAYS
MUX Gate / Trig B PCIe
Timing Bus Out 8
USB Sync / PPS Sample Clk A
Sync / PPS A Sample Clk B
MUX
TTL Gate / Trig A
Sync / PPS A In Gate / Trig B
Sync / PPS A
Sync / PPS B Sync / PPS B
TTL MUX
Sync / PPS B In

Figure 85

Model 7893 System Synchronizer and Distribution The 7893 provides eight timing bus output connec-
Board synchronizes multiple Pentek Cobalt and Onyx tors for distributing all needed timing and clock signals
boards within a system. It enables synchronous sampling, to the front panels of Cobalt and Onyx boards via ribbon
playback and timing for a wide range of multichannel cables. The 7893 locks the Gate/Trigger and Sync/PPS
high-speed data acquisition, DSP and software radio signals to the systems sample clock. The 7893 also
applications. provides four front panel SMA connectors for distrib-
uting sample clocks to other boards in the system.
Up to eight boards can be synchronized using the
7893, each receiving a common clock up to 800 MHz The 7893 can accept a clock from either the front panel
along with timing signals that can be used for synchroniz- SMA connector or from the timing bus input connector. A
ing, triggering and gating functions. For larger systems, programmable on-board VCXO clock generator can be
up to eight 7893s can be linked together to provide synchro- locked to a user-supplied, 10 MHz reference.
nization for up to 64 Cobalt or Onyx boards.
The 7893 supports a wide range of products in the
The Model 7893 provides four front panel SMA Cobalt family including the 78620 and 78621 three-channel
connectors to accept LVTTL input signals from A/D 200 MHz transceivers, the 78650 and 78651 two-channel
external sources: two for Sync/PPS and one for Gate/ A/D 500 MHz transceivers, the 78660, 78661 and 78662
Trigger. In addition to the synchronization signals, a front four-channel 200 MHz A/Ds, and the 78690 L-Band RF
panel SMA connector accepts sample clocks up to 800 MHz Tuner. The 7893 also supports the Onyx 78760 four-
or, in an alternate mode, accepts a 10 MHz reference channel 200 MHz A/D and all complementary models
clock to lock an on-board VCXO sample clock source. in the Onyx family.

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High-Speed Clock Generator

Model 7194 - PMC/XMC

Clock Out 1
FREQUENCY
SYNTHESIZER
Clock Out 2
Reference REFERENCE SAMPLE POWER
Clock In CLOCK CLOCK
IN OUT SPLITTER
Clock Out 3
frequency set
by board option
Clock Out 4

OVEN Reference
STABlLIZED Clock Out
OSCILLATOR

Model 7194
PMC/XMC

Figure 86

Model 7194 High-Speed Clock Generator provides In addition to accepting a reference clock on the front
fixed-frequency sample clocks to Cobalt and Onyx panel, the 7194 includes an on-board 10 MHz
modules in multiboard systems. It enables synchronous reference clock. The reference is an OCXO (Oven-
sampling, playback and timing for a wide range of Controlled Crystal Oscillator), which provides an
multichannel high-speed data acquisition and software exceptionally precise frequency standard with excellent
radio applications. phase noise characteristics.
The Model 7194 uses a high-precision, fixed- The 7194 is a standard PMC/XMC module. The
frequency, PLO (Phase-Locked Oscillator) to generate module does not require programming and the PMC
an output sample clock. The PLO accepts a 10 MHz P14 or XMC P15 connector is used solely for power.
reference clock through a front panel SMA connector. The module can be optionally configured with a PCIe-
The PLO locks the output sample clock to the incoming style 6-pin power connector allowing it to be used in
reference. A power splitter then receives the sample clock virtually any chassis or enclosure.
and distributes it to four front panel SMA connectors.
Versions of the 7194 are also available as a PCIe half-
The 7194 is available with sample clock frequencies length board (Model 7894), 3U VPX (Model 5294),
from 1.4 to 2.0 GHz. 6U VPX (Models 5794 and 5894 with dual density),
AMC (Model 5694), 6U cPCI (Models 7294 and 7494
dual density), and 3U cPCI (Model 7394).

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High-Speed System Synchronizer Unit

Model 9192 - Rackmount


Rackmount
External Clk In

Clock Out 1
PROGRAMMABLE
VCXO Clock Out 2
Sample Clk /
Reference MUX CLOCK
Clk In Clock Out 3
Clk SPLITTER
MUX In through
Clock Out 11
PLL
:N
&
DIVIDER Clock Out 12
:N
Ref mSync 1
In Reference Clk In *
Model 9192 TWSI Control In
TWSI
CONTROL Gate / Trigger Out
USB Sync Out
USB-TO-TWSI Reference Clk Out
INTERFACE
mSync 2

Gate / Trigger Out


Sync Out
Clk Reference Clk Out
MUX Ref
In
Gate / Trigger In BUFFER
Trig/ & mSync 3
Gate PROGRAM through
Sync In
In
DELAYS mSync 11
Sync
In mSync 12

Gate / Trigger Out


Sync Out
* For 71640 A/D calibration Reference Clk Out
Figure 87

Model 9192 Rack-mount High-Speed System The 9192 provides four rear panel Sync output
Synchronizer Unit synchronizes multiple Pentek Cobalt or connectors, compatible with a range of high-speed Pentek
Onyx modules within a system. It enables synchronous Cobalt and Onyx boards. The Sync signals include a
sampling and timing for a wide range of multichannel reference clock, gate/trigger and sync signals and are distrib-
high-speed data acquisition, DSP, and software radio uted through matched cables, simplifying system design.
applications. Up to twelve boards can be synchronized
The 9192 features twelve calibration outputs
using the 9192, each receiving a common clock along
specifically designed to work with the 71640 or 71741
with timing signals that can be used for synchronizing,
3.6 GHz A/D modules and provides a signal reference
triggering and gating functions.
for phase adjustment across multiple D/As.
Model 9192 provides four rear panel SMA connec-
The 9192 allows programming of operation parameters
tors to accept input signals from external sources: two
including: VCXO frequency, clock dividers, and delays that
for clock, one for gate or trigger and one for a synchro-
allow the user to make timing adjustments on the gate and
nization signal. Clock signals can be applied from an
sync signals. These adjustments are made before they are sent
external source such as a high performance sine-wave
to buffers for output through the Sync connectors.
generator. Gate/trigger and sync signals can come from an
external system source. In addition to the SMA connector, The 9192 supports all high-speed models in the Cobalt
a reference clock can be accepted through the first rear family including the 71630 1 GHz A/D and D/A XMC, the
panel Sync output connector, allowing a single Cobalt 71640 3.6 GHz A/D XMC and the 71670 Four-channel
or Onyx board to generate the clock for all subsequent 1.25 GHz, 16-bit D/A XMC. The 9192 also supports high-
boards in the system. speed models in the Onyx family.

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Talon High-Speed Recording Systems: Flexible and Deployable Solutions
Recording
High-Speed Recording Systems Recording Systems Form Factors
Talon High-Speed Recording Systems eliminate the Penteks High-Speed Recording Systems are available as
time and risk associated with new technology system Lab Systems, Portable Systems, Rugged, and Extreme Systems.
development. With increasing pressure in both the defense
RTV and RTS Lab Systems are housed in a 19-in. rack-
and commercial arenas to get to the market first, todays
mountable chassis in a PC server configuration. They are
system engineers are looking for more complete off-the-shelf
designed for commercial applications in a lab or office environ-
system offerings.
ment.
Out of the box, these systems arrive complete with
a full-featured virtual operator control panel ready for
RTS Lab system
immediate data recording and/or playback operation.
Because they consist of modular COTS board-level
products and the flexible Pentek SystemFlow software, they
are easily scalable to larger multichannel data acquisition
and recording applications requiring aggregate recording RTR Portable Systems are available in a small briefcase-
rates of up to 5.0 GB/sec. sized enclosures with integral LCD display and keyboard.
They, too, provide a PC server configuration and are designed
Ready-to-Run Recording Systems for harsh environment field applications where size and weight is
of paramount importance.
Depending on model, the Pentek offerings are fully
integrated systems featuring a range of A/D and D/A
resources or digital I/O with high-speed disk arrays.
RTR Portable System
These systems are built on a Windows workstation
and they are presented in this section because they can
easily satisfy a broad spectrum of recording needs.
Furthermore, users can easily install postprocessing and RTR Rugged Rackmount Systems are housed in a 19-in.
analysis tools to operate on the recorded data which is rugged rack-mountable chassis. They are built to survive
stored in the familiar NTFS format. shock and vibration and they target operation in harsh
environments and remote locations that may be unsuitable
for humans.

RTR Rackmount
RTV Recording Systems are RTS Recording Systems are system
excellent value for under designed for commercial
$20,000 US applications

RTX Extreme Systems are available in a rackmount


chassis designed to military specs. They are designed to
RTR Recording Systems are RTX Recording Systems are operate under extreme environmental conditions using
designed for harsh designed for extreme forced-air or conduction-cooling to draw heat from system
environments environments components.
ANALOG RECORDERS
RTX Rackmount
system
DIGITAL RECORDERS

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Pentek SystemFlow Recording Sof


Recording tware for Analog R
Software ecorders
Recorders

Recorder Interface Hardware Configuration

Signal Viewer

Figure 88

The Pentek SystemFlow Recording Software for Analog contain limit-checking and integrated help to provide
Recorders provides a rich set of function libraries and tools an easier-to-use out-of-the-box experience.
for controlling all Pentek analog high-speed real-time
The SystemFlow Signal Viewer includes a virtual
recording systems. SystemFlow software allows developers
oscilloscope and spectrum analyzer for signal monitoring
to configure and customize system interfaces and behavior.
in both the time and frequency domains. It is extremely
The Recorder Interface shows a system block diagram useful for previewing live inputs prior to recording, and
and includes configuration, record, playback and status for monitoring signals as they are being recorded to help
screens, each with intuitive controls and indicators. The ensure successful recording sessions. The viewer can also
user can easily move between screens to set configuration be used to inspect and analyze the recorded files after the
parameters, control and monitor a recording, play back recording is complete.
a recorded signal and monitor board temperatures and
Advanced signal analysis capabilities include automatic
voltage levels.
calculators for signal amplitude and frequency, second
The Hardware Configuration screen provides a and third harmonic components, THD (total harmonic
simple and intuitive means for setting up the system distortion) and SINAD (signal to noise and distortion).
parameters. The configuration screen shown here, allows With time and frequency zoom, panning modes and dual
user entries for input source, center frequency, decimation, annotated cursors to mark and measure points of interest,
as well as gate and trigger information. All parameters the Signal Viewer can often eliminate the need for a separate
oscilloscope or spectrum analyzer in the field.

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Pentek SystemFlow Recording Sof


Recording tware for Digital R
Software ecorders
Recorders

Main Interface Hardware Configuration

Record Screen

Figure 89

The SystemFlow Main Interface for Digital Record- The Record screen allows you to browse a folder and
ers shows a block diagram of the system and provides the enter a file name for the recording. The length of the
user with a control interface for the recording system. It recording for each channel can be specified in megabytes
includes Configuration, Record, Playback, and Status or in seconds. Intuitive buttons for Record, Pause and
screens, each with intuitive controls and indicators. The Stop simplify operation. Status indicators for each
user can easily move between screens to set configuration channel display the mode, the number of recorded bytes,
parameters, control and monitor a recording, and play back and the average data rate. A Data Loss indicator alerts
a recorded stream. the user to any problem, such as a disk- full condition.
The Configure screen presents operational system By checking the Master Record boxes, any combina-
parameters including temperature and voltages. Parameters tion of channels in the lower screen can be grouped for
are entered for each input or output channel specifying synchronous recording via the upper Master Record screen.
UDP or TCP protocol, client or server connection, the The recording time can be specified, and monitoring
IP address and port number. All parameters contain limit- functions inform the operator of recording progress.
checking and integrated help to provide an easier-to-use
out-of-the-box experience.

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200 MS/sec RF/IF Rackmount V


Rackmount alue R
Value ecorder
Recorder

Model RTV 2601

Analog Gigabit
DIGITAL
Input Ethernet
DOWN-
200 MHz
CONVERTER USB
16-bit A/D INTEL
Decimation:
PROCESSOR
2 to 65,536
PS/2
Keyboard
DDR PS/2
SYSTEM DRIVE SDRAM Mouse
Analog
DIGITAL Video
Output
UP- Output
800 MHz
Model RTV 2601 16-bit D/A
CONVERTER
GPS
Decimation: HOST PROCESSOR
Antenna
2 to 65,536 RUNNING SYSTEMFLOW
(Optional)

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

4 TB DATA STORAGE
MODEL RTV 2601

Figure 90

The Talon RTV 2601 is a turnkey multiband a few kilohertz to 80 MHz. A digital upconverter and
recording and playback system used for recording and D/A produce an analog output matching the recorded
reproducing signals with bandwidths up to 80 MHz. IF signal frequency.
The RTV 2601 uses a 16-bit, 200 MHz A/D converter
The system includes a built-in sample clock
to provide real-time sustained recording rates to disk of
synthesizer programmable to any desired frequency
up to 400 MB/sec. The A/D is complemented with a
from 10 MHz to 200 MHz. This clock synthesizer can be
16-bit 800 MHz D/A that provides the ability to reproduce
locked to an external 10 MHz reference clock and has
signals captured in the field.
excellent phase noise characteristics. Alternately, the user
The RTV 2601 comes in a 4U 19 in. rackmount can supply an external sample clock to drive the A/D and
package that is 22.75 in. deep. Signal I/O is provided in D/A converters. The RTV 2601 also supports external
the rear of the unit, while the hot-swappable data drives triggering, allowing users to trigger a recording or playback
are available at the front. Air is pulled through the system on an external signal.
from front to back allowing it to operate at ambient
The RTV 2601 includes the Pentek SystemFlow record-
temperatures from 5 to 35 deg C.
ing software. SystemFlow features a Windows-based GUI
The RTV 2601 includes a programmable digital (Graphical User Interface) that provides a simple means to
downconverter so users can configure the system to capture configure and control the recorder. As an option, a GPS
signals with frequencies as low as 300 kHz and as high as or IRIG receiver card can be supplied with the system for
700 MHz. Corresponding signal bandwidths range from accurate time stamping of recorded data.

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Serial FPDP Rackmount V


Rackmount alue R
Value ecorder
Recorder

Model RTV 2602

Channels
In / Out Serial Gigabit
FPDP Ethernet

INTEL USB
PROCESSOR
Keyboard

DDR
SYSTEM DRIVE Mouse
SDRAM

Video
Output
Model RTV 2602
GPS
HOST PROCESSOR
Antenna
RUNNING SYSTEMFLOW
(Optional)

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

4 TB DATA STORAGE
MODEL RTV 2602

Figure 91

The Talon RTV 2602 Serial FPDP Value Recorder is mode, or multi-mode fiber, to accommodate all popular
designed to provide a low-cost solution to users looking to Serial FPDP interfaces. It is capable of both receiving and
capture and play back multiple Serial FPDP streams. It transmitting data over these links and supports real-time
can record up to four Serial FPDP channels to the built- data storage to disk.
in 4 TB RAID consisting of cost-effective, enterprise-class
Programmable modes include flow control in both
HDD storage. It is a complete turnkey recording system,
receive and transmit directions, CRC support, and copy/
ideal for capturing any type of streaming sources. These
loop modes. The system is capable of handling 1.0625,
include live transfers from sensors or data from other
2.125, 2.5, 3.125 and 4.25 GBaud link rates. Up to four
computers and is fully compatible with the VITA 17.1
channels can be recorded simultaneously with an aggregate
specification.
recording rate of up to 400 MB/sec.
The RTV 2602 comes in a 4U 19 in. rack-mount
As an option, a GPS or IRIG receiver card can be
package that is 22.75 in. deep. Signal I/O is provided in
supplied with the system providing accurate time stamping
the rear of the unit, while the hot-swappable data drives
of recorded data. Additionally, the GPS receiver delivers
are available in the front. Air is pulled through the system
GPS position information that can be recorded along with
from front to back to allow operation at ambient
the input signals.
temperatures from 5o to 35o C.
The RTV 2602 includes the Pentek SystemFlow
The RTV 2606 can be populated with up to four SFP
recording software which features a Windows-based GUI.
connectors supporting Serial FPDP over copper, single-

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200 MS/sec RF/IF Rugged PPor


Rugged or table R
ortable ecorder
Recorder

Model RTR 2726A

DIGITAL DOWN HIGH RESOLUTION Aux Video


Channels VIDEO DISPLAY
In 200 MHz CONVERTER VGA Output
16-bit A/D DEC: 2 to 64K
Gigabit
INTEL Ethernet
PROCESSOR
USB

DDR
Channels DIGITAL UP SYSTEM DRIVE SDRAM
Out 800 MHz CONVERTER
16-bit D/A INT: 2 to 512K
HOST PROCESSOR
RUNNING SYSTEMFLOW

Model RTR 2726A

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

RAID DATA STORAGE


MODEL RTR 2726

Figure 92

The Talon RTR 2726A is a turnkey, multiband recording the GUI-selectable system parameters, that provide fully-
and playback system that allows the user to record and programmable systems capable of recording and reproducing
reproduce high-bandwidth signals with lightweight, portable a wide range of signals.
and rugged packages. This model provides aggregate
Included with this system is Penteks SystemFlow
recording rates of up to 3.2 GB/sec and is ideal for the
recording software. Built on a Windows 7 Professional
user who requires both portability and solid perfor-
workstation with high performance Intel Core i7 processor, the
mance in a compact recording system.
system allows the user to install post-processing and
The RTR 2726A is supplied in a small footprint portable analysis tools to operate on the recorded data. They
package measuring only 16.0" W x 6.9" D x 13.0" H record data to the native NTFS file system, providing
and weighing just less than 30 pounds. immediate access to the data. Custom configurations
can be stored as profiles and later loaded when needed,
With measurements similar to small briefcases, this
so users can select preconfigured settings with a single click.
portable workstation includes Intel Core i7 processors,
high-resolution 17" LCD monitors, and up to 15.3 TB Versions of the RTR 2726A are also available as a
of SSD storage. Rackmount Lab unit (Model RTS 2706), Rugged Rackmount
(Model RTR 2746), and Extreme Rackmount
A/D sampling rate, DDC decimation and bandwidth,
(Model RTX 2766).
D/A sampling rate and DUC interpolation are among

81
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250 MS/sec RF/IF Rugged R


Rugged ackmount R
Rackmount ecorder
Recorder

Model RTR 2750

Gigabit
Ethernet
INTEL
PROCESSOR USB
Channels DIGITAL
In 250 MHz DOWN- PS/2
16-bit A/D CONVERTER Keyboard
Decimation: DDR PS/2
2 to 65536 SYSTEM DRIVE SDRAM Mouse
Video
Output
HOST PROCESSOR GPS Antenna
RUNNING SYSTEMFLOW (Optional)
Model RTR 2750

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

RAID DATA STORAGE


MODEL RTR 2750

Figure 93

The Talon RTR 2750 is a turnkey recording system under harsh conditions and allow for quick removal of mission-
that provides phase-coherent recording of 16 indepen- critical data.
dent input channels. Each input channel includes a 250
A/D sampling rates, DDC decimations and trigger settings
MHz 16-bit A/D and an FPGA-based digital down-
are among the selectable system parameters, providing a system
converter with programmable decimations from 2 to
that is simple to configure and operate. An optional GPS
65536, thereby providing the ability to capture RF
time and position stamping facility allows the user to time-
signals with bandwidths up to 100 MHz.
stamp each acquisition as well as track the location of a
With options for AC- or DC-coupled input channels, system in motion.
RF signals up to 700 MHz in frequency can be sampled
For users who wish to create a custom user interface
and streamed to disk in real-time at sustained aggregate
or to integrate the Talon recording system into a larger
recording rates up to 8 GB/sec in a 4U rackmount
application, a C-callable API is also provided as part of
solution.
SystemFlow. Source code and examples are supplied to
Designed to operate under conditions of vibration allow for a quick and simple integration effort.
and extended operating temperatures, the RTR 2750 is
Data can be off-loaded through gigabit Ethernet ports
ideal for military, airborne and field applications that
or USB 3.0 ports. Additionally, data can be copied to
require a rugged system. The hot-swappable solid state
optical disk, using the 8X double layer DVDR/RW drive.
storage drives provide the highest level of performance

82
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500 MS/sec RF/IF Rackmount LLab


Rackmount ab Recorder
Recorder

Model RTS 2707

500 MHz
12-bit A/D DIGITAL DOWN- Gigabit
Channels CONVERTER Ethernet
or
In DEC: 2 to 64K INTEL
400 MHz USB 2.0
PROCESSOR
14-bit A/D
Up to 4
PS/2
Channels Keyboard
DDR
SYSTEM DRIVE SDRAM PS/2
Mouse
Channels DIGITAL UP-
800 MHz Video
Out CONVERTER Output
16-bit D/A HOST PROCESSOR
INT: 2 to 64K
Up to 4 RUNNING SYSTEMFLOW
GPS Model RTS 2707
Channels Antenna
(Optional)

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

RAID DATA STORE


MODEL RTS 2707

Figure 94

The Talon RTS 2707 is a turnkey, multiband record- The RTS 2707 includes the SystemFlow Recording
ing and playback system for recording and reproducing Software. SystemFlow features a Windows-based GUI
high-bandwidth signals. The RTS 2707 uses 12-bit, that provides a simple means to configure and control the
500 MHz A/D converters and provides agregate recording recorder.
rates up to 1.6 GB/sec.
The RTS 2707 is configured in a 4U 19" rack-
The RTS 2707 uses Penteks high-powered Virtex-6- mountable chassis, with hot-swappable data drives, front
based Cobalt modules, that provide flexibility in channel panel USB ports and I/O connectors on the rear panel.
count, with optional digital downconversion capabilities. Systems are scalable to accommodate multiple chassis to
Optional 16-bit, 800 MHz D/A converters with digital increase channel counts and aggregate data rates.
upconversion allow real-time reproduction of recorded
Multiple RAID levels, including 0, 1, 5, 6, 10 and
signals.
50, provide a choice for the required level of redundancy.
A/D sampling rates, DDC decimations and band- The hot-swappable HDDs provide storage capacities of
widths, D/A sampling rates and DUC interpolations are up to 100 TB in a single 6U chassis.
among the GUI-selectable system parameters, providing
Versions of the RTS 2707 are available as Rugged
a fully-programmable system capable of recording and
Portable (Model RTR 2727), Rugged Rackmount (Model
reproducing a wide range of signals. Optional GPS time
RTR 2747), and Extreme Rackmount (Model RTX 2767).
and position stamping allows the user to record this
critical signal information.

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1 GS/sec RF/IF Rugged R


Rugged ackmount R
Rackmount ecorder
Recorder

Model RTR 2748

Channel Gigabit
1 GHz
In Ethernet
12-bit
A/D INTEL USB
PROCESSOR
Keyboard
Channel
1 GHz DDR
Out SYSTEM DRIVE Mouse
16-bit SDRAM
D/A Video
Output
GPS
HOST PROCESSOR Antenna
RUNNING SYSTEMFLOW (Optional)
Model RTR 2748
Channel
1 GHz
In
12-bit
A/D

DATA DRIVES DATA DRIVES


Channel
1 GHz
Out
16-bit DATA DRIVES DATA DRIVES
D/A
RAID DATA STORAGE
(Optional)

MODEL RTR 2748

Figure 95

The Talon RTR 2748 is a turnkey recording and playback Built on a Windows 7 Professional workstation,
system that allows users to record and reproduce signals the RTR 2748 allows the user to install post-processing
with bandwidths up to 500 MHz. The RTR 2748 can be and analysis tools to operate on the recorded data. The
configured as a one- or two-channel system to provide RTR 2748 records data to the native NTFS file system
real-time aggregate recording and playback rates up to that provides immediate access to the recorded data.
4.0 GB/sec to an array of solid-state drives.
Data can be off-loaded via gigabit Ethernet ports, or
The RTR 2748 uses Penteks high-powered Virtex-6- USB 2.0 and USB 3.0 ports. Additionally, data can be
based Cobalt boards that provide the data streaming copied to optical disk, using the 8X double layer
engine for the high-speed A/D converters. A built-in DVDR/RW drive.
synchronization module is provided to allow for multi-
Because SSDs operate reliably under conditions of shock
channel phase-coherent operation. GPS time and position
and vibration, the RTR 2748 performs well in ground, ship-
stamping is optionally available.
borne and airborne environments. The drives can be easily
The RTR 2748 includes the SystemFlow Recording removed or exchanged during a mission to retrieve the data.
Software. SystemFlow features a Windows-based GUI
Versions of the RTR 2748 are also available as a
that provides a simple means to configure and control
Rugged Portable (Model RTR 2728), and Extreme
the system. Custom configurations can be stored as profiles
Rackmount (Model RTX 2768).
and later loaded when needed, allowing the user to select
preconfigured settings with a single click.

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3.6 GS/sec Ultra W ideband RF/IF Extreme R


Wideband ackmount R
Rackmount ecorder
Recorder

Model RTX 2769

Gigabit
Ethernet
Channel 1
In 3.6 GHz USB
(1 Channel) INTEL
or PROCESSOR Keyboard
Channel 2 1.8 GHz
In (2 Channel)
12-Bit A/D Mouse
DDR
SYSTEM DRIVE SDRAM
Model RTX 2769 Video
Output
GPS
Antenna
HOST PROCESSOR (Optional)
RUNNING SYSTEMFLOW

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

RAID DATA STORAGE


MODEL RTX 2769

Figure 96

The Talon RTX 2769 is a turnkey system that is built to Built on a Windows 7 Professional workstation,
operate under harsh conditions. Designed to withstand the RTX 2769 allows the user to install post-processing
high vibration and operating temperatures, the RTX and analysis tools to operate on the recorded data. The
2769 is intended for military, airborne and UAV applications RTX 2769 records data to the native NTFS file system
requiring a rugged system. that provides immediate access to the recorded data.
Aimed at recording high-bandwidth signals, the RTX 2769 The Talon RTX 2769 uses a shock- and vibration-
uses 12-bit, 3.6 GHz A/D converters. It can be configured isolated inner chassis and solid-state drives to assure reliabil-
as a one- or two-channel system and can record sampled data, ity under harsh conditions. Developed by Pentek to enhance
packed as 8-bit- or 16-bit-wide consecutive samples the operation of Extreme recorders, up to four front-panel
(12-bit digitized samples residing in the 12 MSBs of the removable QuickPacTM drive canisters are provided, each
16-bit word). A high-speed RAID array provides an containing up to eight SSDs. Fastened with four thumbscrews,
aggregate streaming recording rate to disk of 4.8 GB/sec. each drive canister can hold up to 7.6 TB of data storage
and allows for quick and easy removal of mission-critical data
The RTX 2769 uses Penteks high-powered Virtex-7-
with a minimum of down time.
based Onyx boards that provide the data streaming engine
for the high-speed A/D converters. Channel and packing Versions of the RTX 2769 are available as a Rugged
modes as well as gate and trigger settings are among the Portable (Model RTR 2729A), and Rugged Rackmount
selectable system parameters, providing complete (Model RTR 2749).
control over this ultra wideband recording system.

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6 GHz RF/IF Sentinel Intelligent Signal Scanning Rackmount R


Rackmount ecorder
Recorder

Model RTS 2620

Gigabit
DIGITAL
RF In 6 GHz RF Ethernet
200 MHz DOWN-
DOWN- CONVERTER
16-bit A/D INTEL USB
CONVERTER Decimation:
PROCESSOR
2 to 65,536
Keyboard

DDR
SYSTEM DRIVE Mouse
Model RTS 2620 SDRAM
DIGITAL Video
RF Out 6 GHz RF UP-
UP- 800 MHz Output
CONVERTER
CONVERTER 16-bit D/A GPS
Decimation: HOST PROCESSOR
Antenna
2 to 65,536 RUNNING SYSTEMFLOW
(Optional)

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

RAID DATA STORAGE


MODEL RTS 2620

Figure 97

The Talon RTS 2620 combines the power of a Pentek The Pentek Model 78621 Cobalt board transceiver
Talon Recording System with those of an RF tuner and serves as the engine of the RTS 2620 and is coupled
RF upconverter hardware plus Penteks Sentinel Intelligent with a 6 GHz tuner to provide excellent dynamic range
Signal Scanner. The RTS 2620 provides SIGINT across the entire spectrum. The 200 MHz 16-bit A/D
engineers the ability to scan the 6 GHz spectrum for board provides 86 dB of spurious-free dynamic range
signals of interest and monitor or record bandwidths up to and 74 dB of SNR.
40 MHz wide once a signal band of interest is detected.
The Virtex-6-based DDC with selectable decimations
A spectral scan facility allows the user to sweep the of up to 64 k provides exceptional processing gain while
spectrum at 30 GHz/sec, while threshold detection allows allowing users to zoom into signals of varying bandwidths.
the system to automatically lock onto and record signal All system components are integrated into a rackmount
bands. Scan results are displayed in a waterfall plot and chassis that ranges in size from 3U to 6U depending on
can also be recorded to allow users to look back at some storage requirements. Front panel removable HDDs,
earlier spectral activity. configured as a RAID are hot-swappable and configurable.
Once a signal of interest is detected, the real-time An optional GPS receiver and built-in PLLs allow all
recorder can capture and store hundreds of terabytes of devices in the RF chain to be locked in phase and correlated
data to disk, allowing users to store days worth of data. to GPS time. GPS position information can optionally
The optional RF upconverter reproduces signals captured be recorded, allowing the recorders position to be tracked
at RF frequencies up to 6 GHz. while acquiring RF signals.

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6 GHz RF/IF Sentinel Intelligent Signal Scanning Rackmount R


Rackmount ecorder
Recorder

Model RTS 2620

Figure 98

Penteks SentinelTM recorders add intelligent signal analysis tools to complement the Sentinel hardware
monitoring and detection for Talon real-time recording resources.
systems. The intuitive GUI allows users to monitor the entire
As shown in the figure above, an RF Scanner GUI
spectrum or select a region of interest, while a selectable
allows complete control of the system through a single
resolution bandwidth allows the user to trade sweep rate for a
interface. Start and stop frequencies of a scan can be set by
finer resolution and better dynamic range. Scan settings can
the user as well as the resolution bandwidth. All user param-
be saved as profiles to allow for quick setup in the field.
eters can be saved as profiles for easy setup in the field.
RF energy in each band of the scan is detected and
Frequency slices from the waterfall display can be
presented in a waterfall display. Any RF band can be
selected and monitored, allowing the user to zoom into
selected for real-time monitoring or recording. In
bands of interest. Threshold triggering levels can be set to
addition to manually selecting a band for recording, a
record signals that exceed a specified energy. Recordings
recording can be automatically started by configuring
can also be manually started and stopped.
signal strength threshold levels to trigger it.
The Signal Viewer includes a virtual oscilloscope and
The Sentinel hardware resources are controlled through
spectrum analyzer for signal monitoring in both the
enhancements to Talons SystemFlow software package that
time and frequency domains. It is extremely useful for
includes a Virtual Oscilloscope, Virtual Spectrum Analyzer
previewing live inputs prior to recording, and for monitor-
and Spectrogram displays, providing a complete suite of
ing signals as they are being recorded.

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10- Gigabit Ethernet R


10-Gigabit ackmount R
Rackmount ecorder
Recorder

Model RTS 2715

Gigabit
Ethernet
Channels
In / Out USB
Ethernet
INTEL
PROCESSOR
PS/2
Keyboard

DDR PS/2
SYSTEM DRIVE SDRAM Mouse
Video
Output
GPS
HOST PROCESSOR Antenna
RUNNING SYSTEMFLOW (Optional) Model RTS 2715

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

RAID DATA STORAGE


MODEL RTS 2715

Figure 99

The Talon RTS 2715 is a turnkey rackmount lab record- loaded as needed, allowing the user to select preconfigured
ing system for storing one or two 10-gigabit Ethernet (10GbE) settings with a single click.
streams. It is ideal for capturing any type of streaming sources
Built on a server-class Windows 7 Professional
including live transfers from sensors or data from other computers
workstation, the RTS 2715 allows the user to install
and supports both TCP and UDP protocols. Using highly-
post-processing and analysis tools to operate on the
optimized disk storage technology, the system achieves
recorded data. The RTS 2715 records data to the native
aggregate recording rates up to 1.6 GB/sec.
NTFS file system, providing immediate access to the
Two rear panel SFP+LC connectors for 850 nm multi- data.
mode or single-mode fibre cables, or CX4 connectors for copper
The RTS 2715 is configured in a 4U or 5U 19" rack-
twinax cables accommodate all popular 10 GbE interfaces.
mountable chassis, with hot-swap data drives, front panel
Optional GPS time and position stamping accurately
USB ports and I/O connectors on the rear panel. Systems
identifies each record in the file header.
are scalable to accommodate multiple chassis to increase
The RTS 2715 includes the SystemFlow Recording channel counts and aggregate data rates.
Software. SystemFlow features a Windows-based GUI
Versions of the RTS 2715 are also available as Rugged
(Graphical User Interface) that provides a simple and
Rackmount (Model RTR 2755), and Extreme Rackmount
intuitive means to configure and control the system.
(Model RTX 2775).
Custom configurations can be stored as profiles and later

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Serial FPDP Rugged PPor


Rugged or table R
ortable ecorder
Recorder

Model RTR 2736A

Channels
In / Out Serial Gigabit
FPDP Ethernet

INTEL USB
PROCESSOR
PS/2
Keyboard
DDR PS/2
SYSTEM DRIVE SDRAM Mouse
Video
Output
GPS
HOST PROCESSOR Antenna
RUNNING SYSTEMFLOW (Optional)
Model RTR 2736A

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

MODEL RTR 2736 RAID DATA STORAGE

Figure 100

The Talon RTR 2736A is a complete turnkey record- The system includes the SystemFlow Recording
ing system designed to operate under conditions of shock Software. SystemFlow features a Windows-based GUI
and vibration. It records and plays back multiple serial that provides a simple and intuitive means to configure
FPDP data streams in a rugged, lightweight portable and control the system. Custom configurations can be
package. It is ideal for capturing any type of streaming stored as profiles and later loaded as needed, allowing the
sources including live transfers from sensors or data from user to select preconfigured settings with a single click.
other computers and is fully compatible with the VITA
The RTR 2736A is configured in portable, lightweight
17.1 specification. Using highly-optimized disk storage
chassis with hot-swap SSDs, front panel USB ports and
technology, this system achieves aggregate recording rates
I/O connections on the side panel. It is built in extremely
up to 3.2 GB/sec.
rugged, 100% aluminum alloy unit, reinforced with shock
The system can be populated with up to eight SFP absorbing rubber corners and impact-resistant protective
connectors supporting Serial FPDP over copper, single-mode, glass. Using vibration- and shock-resistant SSDs, the
or multi-mode fiber, to accommodate all popular serial FPDP system is designed to operate reliably as a portable field
interfaces. It is capable of receiving and transmitting data system in harsh environments.
over these links and supports real-time data storage to disk.
Versions of the RTR 2736A are also available as a
The system is capable of handling 1.0625, 2.125, 2.5,
Rackmount Lab unit (Model RTS 2716), Rugged
3.125 and 4.25 GBaud link rates supporting data transfer
Rackmount (Model RTR 2756), and Extreme Rackmount
rates of up to 420 MB/sec per serial FPDP link.
(Model RTX 2776).

89
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LVDS Digital I/O Extreme Rackmount R


Rackmount ecorder
Recorder

Model RTX 2778

Gigabit
32-bit Ethernet
Data In
32-bit
USB
Clock LVDS I/O
Record INTEL
Data Valid PROCESSOR
Interface Keyboard
Data Suspend

DDR Mouse
Model RTX 2778 SYSTEM DRIVE SDRAM
Video
Output
GPS
32-bit Antenna
HOST PROCESSOR
Data Out Optional (Optional)
RUNNING SYSTEMFLOW
32-bit
Clock
LVDS I/O
Data Valid Playback
Interface
Data Suspend

DATA DRIVES DATA DRIVES

DATA DRIVES DATA DRIVES

RAID DATA STORAGE


MODEL RTX 2778

Figure 101

The Talon RTX 2778 is a turnkey record and playback Built on a Windows 7 Professional workstation,
system that is built to operate under harsh conditions. the RTX 2778 allows the user to install post-processing
Designed to withstand high vibration and operating tempera- and analysis tools to operate on the recorded data. The
tures, the RTX 2778 is intended for military, airborne RTX 2778 records data to the native NTFS file system,
and UAV applications requiring a rugged system. providing immediate access to the recorded data.
The RTX 2778 records and plays back digital data The Talon RTX 2778 uses a shock- and vibration-
using the Pentek Model 78610 LVDS digital I/O board. isolated inner chassis and solid-state drives to assure reliabil-
Using highly optimized disk storage technology, the system ity under harsh conditions. Developed by Pentek to enhance
achieves aggregate recording rates of up to 1.0 GB/sec. the operation of Extreme recorders, up to four front-panel
removable QuickPacTM drive canisters are provided, each
The RTX 2778 utilizes a 32-bit LVDS interface
containing up to eight SSDs. Fastened with four thumbscrews,
that can be clocked at speeds up to 250 MHz. It includes
each drive canister can hold up to 7.6 TB of data storage
Data Valid and Suspend signals and provides the ability
and allows for quick and easy removal of mission-critical data
to turn these signals on and off as well as control their polarity.
with a minimum of down time.
The RTX 2778 includes the SystemFlow Record-
Versions of the RTX 2778 are also available as a
ing Software. SystemFlow features a Windows-based
Rackmount Lab unit (Model RTS 2718), Rugged
GUI (Graphical User Interface) that provides a simple
Portable (Model RTR 2738), and Rugged Rackmount
means to configure and control the system.
(Model RTR 2758).

90
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Software-Defined Radio Handbook

Applications

64- Channel Sof


64-Channel tware R
Software adio R
Radio ecording System
Recording

Input A
200 MHz
A/D
Input B
200 MHz
A/D FPGA 2 Gigabit
with
Input C Ethernet
200 MHz 4 banks of
A/D 8-Channel 6
USB 2.0
DDC
Input D INTEL
200 MHz x8 PCIe 2
PROCESSOR eSATA
A/D

PS/2
Pentek Cobalt 78622 PCIe Board DDR
SYSTEM DRIVE Keyboard
SDRAM
PS/2
Mouse
Video
Input A x8 PCIe
200 MHz HOST PROCESSOR Output
A/D GPS
Input B Antenna
200 MHz
A/D FPGA
with
Input C
200 MHz 4 banks of
A/D 8-Channel
DDC
Input D DATA DRIVES DATA DRIVES
200 MHz
A/D
DATA DRIVES DATA DRIVES
Pentek Cobalt 78622 PCIe Board
UP TO 20 TB RAID

Figure 102

Shown above is a 64-channel recording system utilizing Each DDC delivers a complex output stream consist-
two Pentek Cobalt 78662 PCIe boards. The 78662 ing of 24-bit I + 24-bit Q samples at a rate of s/N. Any
samples four input channels at up to 200 megasamples number of channels can be enabled within each bank,
per second, thereby accommodating input signals with selectable from 0 to 8. Each bank includes an output
up to 80 MHz bandwidth. sample interleaver that delivers a channel-multiplexed
stream for all enabled channels within a bank.
Factory-installed in the FPGA of each 78662 is a
powerful DDC IP core containing 32 channels. Each An internal timing bus provides all timing and synchro-
of the 32 channels has an independent 32-bit tuning nization required by the eight A/D converters. It includes
frequency setting that ranges from DC to s, where s a clock, two sync and two gate or trigger signals. An on-
is the A/D sampling frequency. All of the eight channels board clock generator receives an external sample clock.
within each bank share a common decimation setting This clock can be used directly by the A/D or divided by
that can range from 16 to 8192. For example, with a a built-in clock synthesizer circuit.
sampling rate of 200 MHz, the available output band-
Built on a Windows 7 Professional workstation with
widths range from 19.53 kHz to 10.0 MHz. Each 8-channel
high performance Intel Core i7 processor this system
bank can have its own unique decimation setting support-
allows the user to install post processing and analysis
ing a different bandwidth associated with each of the four
tools to operate on the recorded data. The system records
acquisition modules.
data to the native NTFS file system, providing immediate
The decimating filter for each DDC bank accepts access to the recorded data.
a unique set of user-supplied 18-bit coefficients. The 80%
Included with this system is Penteks SystemFlow
default filters deliver an output bandwidth of 0.8*s/N,
recording software. Optional GPS time and position
where N is the decimation setting. The rejection of
stamping allows the user to record this critical signal
adjacent-band components within the 80% output
information.
bandwidth is better than 100 dB.

91
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Software-Defined Radio Handbook

Applications

L-Band Signal PProcessing


rocessing System

Analog Digital
Analog Mixer
L-Band Analog Baseband I
LNA Lowpass A/D
Filter
Baseband Amps
VIRTEX-6
Analog Mixer
RF Input Analog FPGA
Lowpass Baseband Q
A/D
Filter
Q I
Analog Local
Oscillator Maxim
Synthesizer MAX2112 x8 PCIe

Pentek 78690 PCIe Board

WINDOWS
PC

Figure 103

The Cobalt Model 78690 L-Band RF Tuner targets The complex I and Q outputs are digitized by two
reception and processing of digitally-modulated RF 200 MHz 16-bit A/D converters operating synchronously.
signals such as satellite television and terrestrial wireless
The Virtex-6 FPGA is a powerful resource for
communications. The 78690 requires only an antenna
recovering and processing a wide range of signals
and a host computer to form a complete L-band SDR
while supporting decryption, decoding, demodula-
development platform.
tion, detection, and analysis. It is ideal for intercepting
This system receives L-Band signals between 925 MHz or monitoring traffic in SIGINT and COMINT
and 2175 MHz directly from an antenna. Signals above applications. Other applications that benefit include
this range such as C Band, Ku Band and K band can be mobile phones, GPS, satellite terminals, military telem-
downconverted to L-Band through an LNB (Low Noise etry, digital video and audio in TV broadcasting satellites,
Block) downconverter installed in the receiving antenna. and voice, video and data communications.
The Maxim Max2112 L-Band Tuner IC features a This L-Band signal processing system is ideal as a
low-noise amplifier with programmable gain from 0 to front end for government and military systems. Its small
65 dB and a synthesized local oscillator programmable size adderesses space-limited applications. Ruggedized
from 925 to 2175 MHz. The complex analog mixer options are also available from Pentek with the Models
translates the input signals down to DC. Baseband 71690 XMC module and the 53690 OpenVPX board to
amplifiers provide programmable gain from 0 to 15 dB address UAV applications and other severe environments.
in steps of 1 dB. The bandwidth of the baseband lowpass
Development support for this system is provided by
filters can be programmed from 4 to 40 MHz . The
the Pentek ReadyFlow board support package for Windows,
Maxim IC accommodates full-scale input levels of -50 dBm
Linux and VxWorks. Also available is the Pentek GateFlow
to +10 dbm and delivers I and Q complex baseband outputs.
FPGA Design Kit to support custom algorithm development.

92
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Applications

8- Channel OpenVPX Beamforming System


8-Channel

VPX P1
Slot 1 VPX
Model 53661 4X Sum In BACKPLANE
AURORA EP01
BEAMFORM
4X Sum Out
SUMMATION
EP02
4X Aurora
200 MHz DDC 1 FP C
RF Tuner 16-bit A/D G + Phase
x4 PCIe x4 PCIe
200 MHz DDC 2 DP01
RF Tuner 16-bit A/D G + Phase x4
PCIe
200 MHz DDC 3
RF Tuner I/F
16-bit A/D G + Phase

200 MHz DDC 4 VPX P1


RF Tuner 16-bit A/D G + Phase VPX P1
Slot 3 CPU
Slot 2

Model 53661 4X Sum In


AURORA EP01 FP A
BEAMFORM 4X Sum Out
SUMMATION
EP02 FP B
OpenVPX
CPU
200 MHz DDC 1 FPC DP02 Board
RF Tuner 16-bit A/D G + Phase
x4 PCIe x4 PCIe
200 MHz DDC 2 DP01 DP01
RF Tuner 16-bit A/D
x4
G + Phase
PCIe
200 MHz DDC 3 I/F
RF Tuner 16-bit A/D G + Phase

200 MHz DDC 4


RF Tuner 16-bit A/D G + Phase

Figure 104

Two Model 53661 boards are installed in slots 1 and The first four signal channels are processed in the
2 of an OpenVPX backplane, along with a CPU board upper left 53661 board in VPX slot 1, where the 4-channel
in slot 3. Eight dipole antennas designed for receiving beamformed sum is propagated through the 4X Aurora
2.5 GHz signals feed RF Tuners containing low noise Sum Out link across the backplane to the 4X Aurora Sum
amplifiers, local oscillators and mixers. The RF Tuners In port on the second 53661 in slot 2. The 4-channel local
translate the 2.5 GHz antenna frequency signal down summation from the second 53661 is added to the propa-
to an IF frequency of 50 MHz. gated sum from the first board to form the complete 8-channel
sum. This final sum is sent across the x4 PCIe link to the
The 200 MHz 16-bit A/Ds digitize the IF signals
CPU card in slot 3.
and perform further frequency downconversion to baseband,
with a DDC decimation of 128. This provides I+Q complex Assignment of the three OpenVPX 4X links on the
output samples with a bandwidth of about 1.25 MHz. Phase Model 53661 boards is simplified through the use of a
and gain coefficients for each channel are applied to crossbar switch which allows the 53661 to operate with
steer the array for directionality. a wide variety of different backplanes.
The CPU board in VPX slot 3 sends commands Because OpenVPX does not restrict the use of serial
and coefficients across the backplane over two x4 PCIe protocols across the backplane links, mixed protocol
links, or OpenVPX fat pipes. architectures like the one shown are fully supported.

93
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software-Defined Radio Handbook

Applications

8- Channel OpenVPX Beamforming Demo system


8-Channel

Beamforming Demo Control Panel Theoretical 7-lobe Beamforming Patern Real-Life Beamforming Patern

Figure 105

Beamforming Demo System sensitivity across arrival angles from 90O to +90O
perpendicular to the plane of the array.
The beamforming demo system is equipped with a
Control Panel that runs under Windows on the CPU The classic 7-lobe pattern for an ideal 8-element
board. It includes an automatic signal scanner to detect array for a signal arriving at 0O angle (directly in front of
the strongest signal frequency arriving from a test the array) is shown above. Below the lobe pattern is a
transmitter. This frequency is centered around the polar plot showing a single vector pointing to the
50 MHz IF frequency of the RF downconverter. Once computed angle of arrival. This is derived from identify-
the frequency is identified, the eight DDCs are set ing the lobe with the maximum response.
accordingly to bring that signal down to 0 Hz for
summation. An actual plot of a real-life transmitter is also shown
for a source directly in front of the display. In this case
The control panel software also allows specific the perfect lobe pattern is affected by physical objects,
hardware settings for all of the parameters for the eight reflections, cable length variations and minor differences
channels including gain, phase, and sync delay. in the antennas. Nevertheless, the directional information
is computed quite well. As the signal source is moved left
An additional display shows the beam-formed pattern of
and right in front of the array, the peak lobe moves with
the array. This display is formed by adjusting the phase
it, changing the computed angle of arrival.
shift of each of the eight channels to provide maximum
This demo system is available online at Pentek. If
you are interested in viewing a live demonstration, please
let us know of your interest by clicking on this link:
Beamforming Demo.

94
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com

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