University of Texas at Austin

Electrical Engineering Department

BME 303, Introduction to Computing, Fall 2013

Exam 1
October, 3 2013; 5:00-6:15

Directions There are 7 problems worth a total of 100 points. The number of points for each question
is indicated. Make sure that you show all work since partial credit will be given. This exam is
closed book, closed notes, and no calculators are allowed. You may not communicate in any
way with anyone other than exam proctors during the exam time. Dont forget to put your name
down on the first page. You may use the back of the sheets if you need extra space to do scratch work.

You have 75+5 mins to finish the exam

Name:

Points possible Score

Problem 1 18
Problem 2 6
Problem 3 6
Problem 4 6
Problem 5 18
Problem 6 25
Problem 7 21
Total 100

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1. (18 points) Answer the following

(a) (6 points) What is the decimal value of xAA, if it represents

i. An unsigned number

xAA= 10101010 has a decimal value of 160+610= 170

ii. A signed number in signed magnitude representation

xAA = 10101010 is a negative number with a magnitude of 42.

Which gives the result, -42
iii. A signed number in 1s complement

xAA = 10101010 is a negative number with a magnitude of (0101010)2 = 10101012 =

85.
which gives the result, -85
(b) (6 points) If we use n bits for representing a number, what is the range of values that can be
represented in these two cases:
i. Unsigned numbers:
[0, 2n 1]
ii. Signed numbers in 2s Complement:
[2n , 2n 1]
(c) (4 points) Evaluate the following expression and give the answer in hex:
(xABBA) NOR (xB0B0)

xABBA NOR xB0B0 = [1010 1011 1011 1010] NOR [1011 0000 1011 0000]
= [0101 0100 0100 0101] = x5445
(d) (2 points) With 12 bits, we can represent uniquely:
i. exactly 12 distinct items
ii. X exactly 4096 distinct items.
iii. exactly 2 times 12, or 24 distinct items
iv. as many distinct items as we wish to.

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2. (6 points) Consider the following logic circuit using a 2-to-1 MUX, where the A input is also used
as the select line. What logic operation does this circuit implement. Hint: Fill out the truth table.

A B Z
0 0
0 1
1 0
1 1

A B Z
0 0 0
0 1 0 The OR gate
1 0 0
1 1 1

3. (6 points) Using only 2-input NAND gates implement a 3-input OR gate. No other gates are allowed.

Z = A + B + C = A.B + C = A.B.C = N OT (N OT (A N AN D B) N AN D N OT (C))

which gives the required circuit with all NAND gates.

4. (6 points) Given a 22 4 memory, where the following sequence of 6 operations were performed.

0101 was read from address 10

1001 was read from address 11
1001 was written to address 00
1111 was read from address 01
0101 was written to address 11
0001 was written to address 00

What are the contents of memory at the end of the these 6 operations?

00 0 0 0 1
01 1 1 1 1
10 0 1 0 1
11 0 1 0 1

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5. (18 points) A 1-bit comparator circuit has inputs A and B and three outputs G (Greater than), E
(Equal) and L (Less than):
where, G is 1 if A > B, 0 otherwise; E is 1 if A = B, 0 otherwise; L is 1 if A < B, 0 otherwise.
(Hint: This problem is similar to the Full Adder, only simpler)

A B G E L

(a) (6 points) Give the truth table for the comparator:

A B G E L
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
(b) (8 points) Give a non-decoder based logic circuit for the the three outputs from the truth-table.

The logic expressions are

G = A.B
E = A.B + A.B
L = A.B
You can draw the circuit from this expression.
(c) (4 points) Using the 1-bit comparator as a basic building block, construct a 4-bit Equality
checker, such that the output EQUAL is 1 if A[3:0] = B[3:0], 0 otherwise. That is all four bits
must be equal for the output to be 1. (Hint: A single 4-input gate will do)

An AND gate with all four E outputs connected to it will realize the logic

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6. (25 points) The following decoder-based design for the circuit for an FSM was derived from a Truth
Table which in turn was derived from a State Transition Graph (STG). Your task is to show the
truth table and corresponding STG

(a) (15 points) Complete the following truth-table that the above FSM circuit was built from.
Note:You are being provided two tables so you fill in the second if you need space.
We need three states, one to indicate that the car is on track, the second
to indicate that the car is off to the left and the third to indicate that
it is off to the right. so we need two bits S1 S2 to represent them.
Inputs Cur St. Next St. Outputs
I C2 C1 N2 N1 X
0 0 0 0 1 0
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 0 0 1
1 0 0 0 0 0
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 1 1 1
(b) (10 points) Give the State transition graph for the FSM. Give names (of your choosing) to each
of the states.
Note: You may not need all circles.

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7. (21 points) Answer the following:

(a) (3 points) The MAR for a memory is n bits and the MDR is m bits. What is the capacity of
the memory (in bits)?

Capacity is 2k m bits, which is 2k m/8 bytes

(b) (3 points) You can build any combinational or sequential logic circuit, with sufficient number
of this basic logic gate:

Capacity is 2k m bits, which is 2k m/8 bytes

(c) (2 points) How many NAND gates is a D-Latch composed of?

4 NAND gates
(d) (2 points) If a decoder has 2k output lines, how many input lines will it need?

Decoder needs log2 (2k ) = k input lines

(e) (2 points) Given A, B are single bits and AB is 1, we can say that A is equal to B. [True/False]
(f) (2 points) It is possible for a 3:8 decoder to have 3 out of the eight outputs be 1. [True/False]
(g) (2 points) We clear an R-S latch by momentarily setting the R input to 0. [True/False]
(h) (2 points) When the gate is supplied with 0v the p type transistor acts as a closed circuit.
[True/ False]
(i) (2 points) For the number A[15 : 0] = 0110110010001111, A[14 : 13] is A[3 : 2].
i. less than
ii. greater than
iii. the same as X
iv. cannot be determined
(j) (1 point) Tell me something about yourself in less than 17 syllables.