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BR10ML MP Build(A01) 2011.03.14 EE DATE POWER DATE INVENTEC DRAWER DESIGN CHECK TITLE BR10ML RESPONSIBLE
BR10ML
MP Build(A01)
2011.03.14
EE
DATE
POWER
DATE
INVENTEC
DRAWER
DESIGN
CHECK
TITLE
BR10ML
RESPONSIBLE
SIZE =
VER :
SIZE
CODE
DOC. NUMBER
REV
FILE NAME :
A3
CS
P/N
SHEET
1
OF
52

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TABLE OF CONTENTS PAGE PAGE PAGE 31.ICH9-1 1.COVER PAGE 32.ICH9-2 2.INDEX 33.ICH9-3 3.BLOCK DIAGRAM 4.POWER
TABLE OF CONTENTS
PAGE
PAGE
PAGE
31.ICH9-1
1.COVER PAGE
32.ICH9-2
2.INDEX
33.ICH9-3
3.BLOCK DIAGRAM
4.POWER SEQUENCE BLOCK
5-12.SYSTEM POWER
13.CLOCK GENERATOR
34.ICH9-4
35.ICH9-5
14.PENRYN-1
15.PENRYN-2
36.SATA HDD CONN
37.ODD CONN
38.USB CONN
39. T/P Board
16.PENRYN-3
40.KBC
17.PENRYN-4
41.
K/B & TP/B CONN
18.FAN & THERMAL CONTROLLER
19.CANTIGA-1
20.CANTIGA-2
21.CANTIGA-3
22.CANTIGA-4
23.CANTIGA-5
24.CANTIGA-6
25.CANTIGA-7
42.Audio Codec
43.Audio AMP/MIC/Speaker
44.LAN CONTROLLER
45.RJ45 & TRANSFORMER
46.USB Card Reader
47.WLAN /Debug
48.LED(M/B) & HOTKEY/B CONN
49.HALL SENSOR
26.DDR3 DIMM0
50.
Power Board
27.DDR3 DIMM1
51.EMI
28.BLANK
52.Screw
29.CRT CONN
30.LCM CONN
INVENTEC
TITLE
BR10ML
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
24-Dec-2010
SHEET
2
OF
52

www.vinafix.vn

Penryn (uFCPGA) Clock generator Socket P ICS9LPRS365 FSB 677/800/1067 DDR III_SODIMM0 DDR III_SODIMM1 800 MHz/
Penryn
(uFCPGA)
Clock generator
Socket P
ICS9LPRS365
FSB
677/800/1067
DDR III_SODIMM0
DDR III_SODIMM1
800 MHz/ 1066 MHz
800 MHz/ 1066 MHz
LCM
DDR3 Interface
CRT
Cantiga
DDR3 Interface
SATA_1
HDD
DMI
SATA_5
ODD
ICH9-M
REALTEK
MINI CARD
RTL8105E
Wireless LAN
3.3V, AZALIA
RJ45
REALTEK
ANT
ANT
ALC269Q
BATTERY
MIC
JACK
WINBOND
NPCE781LA0DX
System Charger &
SPEAKER
DC/DC System power
BIOS
(IMVP-6
VR)
SPI EEROM
INVENTEC
HP JACK
TITLE
BR10ML
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
3-Jan-2011
SHEET
3
OF
52
USB0
CONN
USB1
RESERVED
USB2
CONN
USB3
RESERVE
USB4
RESERVE
USB5
WLAN
USB6
RESERVE
USB7
CAMERA
USB8
CARDREADER
USB9
RESERVE
3.3V, LPC_Interface,33MHz

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+V3LA_(11362mA) +V3A_(997mA) +V3A_LAN_(399mA) PC6014 PC6014 AM4825P 0.01 Adapter +V3S_(10229.3mA) (90W) PC6014
+V3LA_(11362mA)
+V3A_(997mA)
+V3A_LAN_(399mA)
PC6014
PC6014
AM4825P
0.01
Adapter
+V3S_(10229.3mA)
(90W)
PC6014
ADP_PRES
KBC_PW_ON
+V3_(35mA)
AM4825P
5/3.3V
PC6014
(TPS51125)
+VPACK
0.01
+V5A_(10064mA)
+V5S_(3802mA)
CHARGER
PC6014
BATT_CLK
SCL
+V1.8A_(6404mA)
+V0.9S_(900mA)
ACOK
ACIN#
BATT_DATA
SDA
G2997
VO
SLP_S4#_3R
EN_PSV
+V1.5S_(3384.114mA)
TPS51117
APL5913
+VCCP_(12192mA)
VO
SLP_S3#_5R
EN_PSV
TPS51117
+VCC_CORE_(47A)
VCCDRE_EN
VR_ON
VOUT
H_VID [ 0 : 6 ]
VID [ 0 : 6 ]
CLK_EN#
IMVP_CKEN#
INVENTEC
DPRSLPVR
PM_DPRSLPVR
TITLE
BR10ML
TPS51620RHAR
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
4
OF
52

www.vinafix.vn

+VADPTR L6001 FUSE6000 4 8A_125V NFE31PT222Z1E9L 5- CN6000 1 2 1 2 1 1 2
+VADPTR
L6001
FUSE6000
4
8A_125V
NFE31PT222Z1E9L
5-
CN6000
1
2
1
2
1
1
2
2
C7000
3
C6033
4
3
1
1
G1
G
3
G2
G
4
4
2
0402_OPEN
2
10pF_50V
ACES_50315_0047N_002_4P
FUSE6000
65W-75W 8A(6036A0003401)
90W 10A(6036A0002901)
120W 12A(6036A0006001)
+VBAT
+VADPTR
R6000
+VPACK
1
2
6-,7-,8-,9-,11-,30-,51-
5-
4.7K_5%
6-
0.1uF_25V
Q6003
Q6002
Q6005
R6020
8
1
1
8
8
1
D
S
S
D
1
2
D
S
7
2
2
7
7
2
3
4
1
2
3
3
3
6
C6024
0.01_1%
6 5
4
4
5
6 5
4
G
G
G
AM4410NC
AM4410NC
TPCA8065_H
1
C6007
C6018
1 1
C6014
C6010
C6013
0.1uF_25V
0.1uF_25V
2 2
2
68uF_25V
1
2
1
2
2200pF_50V
0.1uF_25V
1
R6023
+VADPTR
1
2
C6012
+V3LA
3
1M_5%
5-
5-,6-,7-,12-,18-,31-,38-,40-,41-,48-,49-
1
2
1 1
D6000
0.1uF_16V
D6001
1 R6012
R6006
R6007
2
DIODE_BAV99
20.5K_1%
1
2
4.3K_5%
4.3K_5%
1
2 2
2 R6008
10K_5%
3
BAT54C_30V_0.2A
C6002
C6005
1
1
C6001
1
1
C6000
2
2
2
2
2 0805_OPEN
5
6
7
8
470pF_50V
4.7uF_25V
4.7uF_25V
1
40-
D
ACPRES
R6015
Q6000
G
AON7410
10_5%
S
U6000
2
C6015
TI_BQ24725RGRR_QFN_20P
R7000
1uF_25V
1
2
4
3
2
1
21
0603_OPEN
TML
1
2
20
EMI
( 2.63V )
6 ACDET
VCC
G_Charger_P
40-
19
HW_I_ADC
7 IOUT
PHASE
G_Charger_H
18
8 SDA
HIDRV
C6006
L6000
R6001
17
1
2
1
2
9 SCL
BTST
16
1
2
3
4
PCMC063T_4R7MN
10 ILIM
REGN
0.047uF_16V
0.01_1%
1 C6026
C6008
1
3
1
2
100pF_50V
2 100pF_50V
5
6
7
8
R6004
2
1
C6016
C6019
C6004
C6023
0603_OPEN
D
2
1 1
1
1
D6002
Q6001
G
1 C6017
C6022
BAT54C_30V_0.2A
2 2
2
2
AON7410
S
1
2
1
C6009
4.7uF_25V
0805_OPEN
2 1uF_10V
0.1uF_16V
4
3
2
1
2
0402_OPEN
4.7uF_25V
4.7uF_25V
1 C6028
R6013
1
C6029
C6027
1
1
3.32K_1%
2
0603_OPEN
G_Charger_L
2
0402_OPEN
2
2
0402_OPEN
C6020
1
1 C6021
0.1uF_25V
2
+V3LA
2 0.1uF_25V
18-,40-
EC_SMB2_DATA
5-,6-,7-,12-,18-,31-,38-,40-,41-,48-,49-
18-,40-
EC_SMB2_CLK
1
1 R6009
20_5%
2
R6014
1 R6010
20_5%
2
110K_5%
2
0X14
1 R6016
0X15
2
4.3K_5%
8.4V : 40D0h
512mA : 0200h_512mA
12.6V : 3140h
1.5A : 0600h_1.54A
1
1 C6011
16.8V : 41A0h
3A : 0C00h_3.07A
R6011
INVENTEC
30K_5%
2 0.1uF_16V
2
TITLE
BR10ML
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
5
OF
52
BATDRV
ACOK
11
5
SRN
ACDRV
12
4
SRP
CMSRC
13
3
GND
ACP
14
2
LODRV
ACN
15
1

www.vinafix.vn

+VPACK FUSE6100 LITTLEFUSE_R451015_15A_65V 5- 1 2 +V3LA 1 C6106 5-,7-,12-,18-,31-,38-,40-,41-,48-,49- CN6100 2
+VPACK
FUSE6100
LITTLEFUSE_R451015_15A_65V
5-
1
2
+V3LA
1 C6106
5-,7-,12-,18-,31-,38-,40-,41-,48-,49-
CN6100
2 1000pF_50V
SYN_200045GR009G15JZR_9P
1
9
R6110
R6109
R6108
BATT+
1
2
1
2
1
2
2
BATT+
3
1M_5%
0_5%
220K_5%
ID
4
R6100
B-I
1
2
40-
1K_5%
5
BATT_IN
TS
40-
R6101
1 2
33_5%
6
G1
EC_SMB1_DATA
SMD
G
40-
R6102
1 2
33_5%
7
G2
EC_SMB1_CLK
SMC
G
8
G3
GND
G
1
1
9
G4
GND
G
D6100
D6101
EZJZ0V500AA
EZJZ0V500AA
2
2
D6103
1
2
PHP_PESD5V0S1BB_SOD523_2P_OPEN
D6104
1
2
PHP_PESD5V0S1BB_SOD523_2P_OPEN
D6105
1
2
PHP_PESD5V0S1BB_SOD523_2P_OPEN
D6102
BAT54_30V_0.2A_OPEN
3
1
+V5LA
+V5LA
+VBAT
7-,18-
7-,18-
1
5-,7-,8-,9-,11-,30-,51-
R6105
1
10K_5%
R6104
U6100
2
510K_1%
18-
5
1
7-,40-
THRM_SHUTDWN#
+V5AUXON
MR
RESET
2
2
GND
4
3
VSEN
VCC
1
GMT_G686LT11U_SOT23_5P
R6103
1 C6107
100K_1%
2 0.1uF_16V
2
INVENTEC
TITLE
BR10ML
SELECT & BATTERY CONN
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
6
OF
52

www.vinafix.vn

+V3A +V5LA +V3LA +V15A +V3LA 6-,7-,18- 5-,6-,7-,12-,18-,31-,38-,40-,41-,48-,49-
+V3A
+V5LA
+V3LA
+V15A
+V3LA
6-,7-,18-
5-,6-,7-,12-,18-,31-,38-,40-,41-,48-,49-
5-,6-,7-,12-,18-,31-,38-,40-,41-,48-,49-
31-,32-,33-,34-,40-,44-
7-,12-
Q6200
PAD6205
6
4
D
S
5
R6223
1
1 R6212
1
POWERPAD_2_0610
2
R6201
1
100K_5%_OPEN
100K_5%
3
G
100K_5%
AO6402AL
2
2
2
R6200
1
40-
1
2
EC_PW_ON#
R6202
0_5%
200_5%
Q6202
3
2
R6224
D
1
2
1 G
C6211
C6215
1
1
0_5%
S
2
SSM3K7002FU
2
2
Q6201
2200pF_50V
0402_OPEN
3
D
1 G
SSM3K7002FU S 2
SKIPSEL
>>VRE3 OR VRE5=OOA
>>VREF=ASKIP
>>GND=PWM
>>VRE5=365/460
Q6203
>>VRE3=300/375
3
1
C6223
D
1
TONSEL >>VREF=245/305
1 G
R6210
>>GND=200/250
120K_1%
2
0.047uF_16V
2
SSM3K7002FU S 2
+VBAT
5-,6-,7-,8-,9-,11-,30-,51-
+VBAT
1
5-,6-,7-,8-,9-,11-,30-,51-
R6209
100K_1%
2
1 C6209
C6203
1 1
C6201
1
C6205 1
1
C6204
2 0.22uF_6.3V
5
6
7
8
2 2
2
2
2
8
7
6
5
4.7uF_25V
4.7uF_25V
4.7uF_25V
D
4.7uF_25v
D
G
Q6206
C6214
G
AON7410
4.7uF_25V
+V5A
S
S
24
C6212
+V3LA
7 VO2
VO1
C6213
7-,8-,9-,11-,12-,30-,34-,38-,51-
23
4
3
2
1
Q6204
8 VREG3
PGOOD
5-,6-,7-,12-,18-,31-,38-,40-,41-,48-,49-
1
2
3
4
22
AON7410
9 VBST2
VBST1
2
1
V5A_HG
V3LA_HG
U6200
21
1
2
10 DRVH2
DRVH1
L6200
0.1uF_25v
V5A_SW
V3LA_SW
20
0.1uF_25v
1
2
11 LL2
LL1
V3LA_LG
19
V5A_LG
PCMC063T_3R3MN
L6201
12 DRVL2
DRVL1
1
2
PCMC063T_3R3MN
5
6
7
8
1 R6218
1
+V5A
R6214
D
0603_OPEN
R6205
8
7
6
5
2
1
R6217
G
1
0_5%_OPEN
2
TI_TPS51123RGER_QFN_24P
15.4K_1%
1
7-,8-,9-,11-,12-,30-,34-,38-,51-
0603_OPEN
D
2
2
C6221 1
G
1
2
R6207
S
R6215
1
1
2
0402_OPEN
2
6.8K_1%
2
C6225
3
4
3
2
1
S
2
C6216
D6202
10K_5%
1
0402_OPEN
1 C6202
Q6207
0.1uF_16V
Q6205
1 DIODE_BAV99
2
1
1
2
3
4
AON7702L
2
1
2 330uF_4V
AON7702L
+V3LDO
C6200
R6206
C6224
330uF_6.3V
2
10K_1%
12-
0402_OPEN
2
1
1
R6204
1
R6208
C6206
1 C6208
1
R6213
10K_1%
0402_OPEN
1
0_5%
2
2
2
2 2.2uF_25v
2
+V5LA
1uF_6.3V
2
2
C6218
6-,7-,18-
0.1uF_16V
1
2
+V15A
3
C6217
7-,12-
D6203
0.1uF_16V
1
DIODE_BAV99
1 C6220
R6216
1
2 6-,40-
1 C6207
+V5AUXON
0_5%
2 1uF_25V
2 10uF_6.3V
INVENTEC
TITLE
BR10ML
SYSTEM POWER(3V/5V/12V)
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
7
OF
52
TML
25
EN0
TRIP2
13
6
SKIPSEL
VFB2
14
5
GND
TONSEL
15
4
VIN
VREF
16
3
VREG5
VFB1
17
2
ENC
TRIP1
18
1

www.vinafix.vn

+VBAT 5-,6-,7-,9-,11-,30-,51- +V1.5 8-,12-,19-,23-,24-,26-,27- 1 +V5A R6314 7-,8-,9-,11-,12-,30-,34-,38-,51- 5 6
+VBAT
5-,6-,7-,9-,11-,30-,51-
+V1.5
8-,12-,19-,23-,24-,26-,27-
1
+V5A
R6314
7-,8-,9-,11-,12-,30-,34-,38-,51-
5
6
7
8
10K_5%
2
1 C6303
1
C6300
D
+V1.5
G
2
4.7uF_25V
TI_TPS51218DSCR_SON_10P
2 4.7uF_25V
8-,12-,19-,23-,24-,26-,27-
U6302
S
Q6300
R6301
C6305
19-
1
10
SM_PWROK
PGOOD
VBST
AON7410
1
2
1
2
4
3
2
1
9
2.2_5%
0.1uF_25v
2 TRIP
DRVH
R6302
L6300
8-,32-,40-
1
2
8
1
2
SLP_S5#_3R
3 EN
SW
0_5%
PCMC063T_1R0MN
1
7
5
6
7
8
4 VFB
V5IN
R6300
1
D
6
0603_OPEN
1
5 RF
DRVL
G
2
R6304
C6301
1 R6311
11.5K_1%
2 110K_1%
S
0402_OPEN
1 C6302
C6309
1
1
2
2
4
3
2
1
R6310
Q6301
1 C6304
2 1uF_10V
2
AON7702L
0603_OPEN
200K_1%
2 560uF_2.5V
2
1
R6303
10K_1%
2
+V5A
+V1.5
+V0.75S
7-,8-,9-,11-,12-,30-,34-,38-,51-
8-,12-,19-,23-,24-,26-,27-
12-,26-,27-
8-,32-,40-
U6300
SLP_S5#_3R
11
1
TML
VDDQSNS
10
2
VIN
VLDOIN
9-,12-,32-,40-
9
3
SLP_S3#_3R
S5
VTT
8
4
GND
PGND
7
5
S3
VTTSNS
19-,26-,27-
6
M_VREF
VTTREF
GMT_G2997F6U_MSOP10_10P
1 C6308
C6307
1 C6306
1 C6311
1
2
22uF_6.3v
2 22uF_6.3v
2 0.1uF_16V
2 1uF_10v
+V5A
7-,8-,9-,11-,12-,30-,34-,38-,51-
+V3S
+V1.8S
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
L6340
C6340
1
R6341
1
R6340
1
U6340
10_5%
10K_5%
9
2
10uF_6.3V
TML
1
2
8
7
VIN
LX
2
2
LTF5022T_2R2N3R2_LC
1 C6343
1
1
4
VCC
FB
R6342
2 0402_OPEN
1
C6344
1 R6344
5
2
13K_1%
EN
REF
200_5%_OPEN
2
2
22uF_6.3v
1
2
1 C6341
C6345
1 C6342
1
0402_OPEN
2 0.1uF_16V
0.1uF_16V
2
2 R6343
Q6340
3
10K_1%
D
12-
1 G
2
SLP_S3_3R
S
2
SSM3K7002FU_OPEN
GMT_AT1530F11U_SOP8_8P
INVENTEC
TITLE
BR10ML
SYSTEM POWER(+V1.8/+V1.25S)
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
8
OF
52
6
PGND
3
GND
11
GND

www.vinafix.vn

+VBAT 5-,6-,7-,8-,11-,30-,51- +V3S
+VBAT
5-,6-,7-,8-,11-,30-,51-
+V3S
8-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
1
+V5A
R6403
7-,8-,11-,12-,30-,34-,38-,51-
10K_5%
5
6
7
8
2
C6408
C6409
C6405
1
1
1
+VCCP
D
2
4.7uF_25V 2
4.7uF_25V 2
4.7uF_25V
TI_TPS51218DSCR_SON_10P
G
11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
U6400
R6401
C6400
40-
10
S
VCCP_PG
Q6401
1 PGOOD
VBST
1
2
1
2
TPCA8065_H
9
2.2_5%
0.22uF_25V
4
3
2
1
2 TRIP
DRVH
L6400
R6409
1
2
8-,12-,32-,40-
8
1
2
SLP_S3#_3R
3 EN
SW
5
6
7
8
3
4
100K_5%
7
4 VFB
V5IN
D
PCMC104T_1R0MN
G
6
5 RF
DRVL
1
C6412
1
1
R6402
S
C6404
1
100K_1%
R6406
1uF_10V
2
1 C6401
1
4
3
2
1
2
10K_1%
2
0402_OPEN
R6423
2 1uF_10V
Q6400
2
470K_1%
TPCA8A02_H
2
1
C6410
2
560uF_2.5V
1
R6408
20K_1%
2
INVENTEC
TITLE
GRAPHIC POWER (+VGFX_CORE)
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
9
OF
52
11
GND

www.vinafix.vn

BLANK INVENTEC TITLE BR10ML SYSTEM POWER(+VCCP/+V1.5S) SIZE CODE DOC. NUMBER REV A3 CS CHANGE by
BLANK
INVENTEC
TITLE
BR10ML
SYSTEM POWER(+VCCP/+V1.5S)
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
10
OF
52

www.vinafix.vn

+VBAT +VBAT_CPU 11- 5-,6-,7-,8-,9-,30-,51- PAD6600 POWERPAD_2_0610 4.7uF_25V 4.7uF_25V 4.7uF_25V C6604 C6610
+VBAT
+VBAT_CPU
11-
5-,6-,7-,8-,9-,30-,51-
PAD6600
POWERPAD_2_0610
4.7uF_25V
4.7uF_25V
4.7uF_25V
C6604
C6610
C6611
C6612
C6631
1 1
C6605
1
C6609
1 1
1 1
C6630
1
2 2
2
2 2
2 2
2
0.01uF_50V
0.01uF_50V
4.7uF_25V
4.7uF_25V
4.7uF_25V
+V3S
+V5A
8-,9-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
7-,8-,9-,12-,30-,34-,38-,51-
R6610
1
18-,32-,40-
2
11-
VR_PWRGD
CSN1
R6601
10K_5%
+VBAT_CPU
19-,32-
1
2
PM_DPRSLPVR
R6613 1
11-
499_1%
C6622
2
IMVP_CKEN#
1
2
11-
10K_5%
CSP1
40-
VCORE_EN
5
6
7
8
0.01uF_50V
R6633
D
1
2
TP6600
G
200K_1%
Q6601
R6614
R6615
R6616
S
1
2
1
2
1
2
TPCA8065_H
R7001
+VCC_CORE
1
2
R6659
42.2K_1%
220K_5%
63.4K_1%
124K_1%
4
3
2
1
1
2
0_5%
16-,51-
L6601
1
C6627
2.2uF_6.3V
R6604
2
1
1
2
0402_OPEN
3
4
2
5
6
7
8
1
PAN_ETQP4LR36WFC_4P
D
1
G
R6612
Q6600
0603_OPEN
TPCA8057_H
S
2
D6602
2
1
C6626
1
4
3
2
1
1 R6603
SBR3U40P1_OPEN
470pF_50V
2 R6657
0.22uF_6.3v
2 0_5%
R6629
11-
1
2
2
1 4.75K_1%
CSP1
C6608
C6628
1
30
330_5%
2
1 DROOP
DRVH1
1
2
29
2
0402_OPEN
2 VREF
VBST1
C6621
47pF_50v
1 C6617
28
3 GND
LL1
1 C6606
27
1
1
1
4 CSP1
DRVL1
2 47pF_50v
5 U6961
26
CSN1
V5IN
2 2.2uF_6.3V
1
2
6 TI_TPS51620RHAR_QFN_40P
25
C6635
C6634
C6633
CSN2
PGND
2
3
2
3
2
3
C6620
470uF_2V
470uF_2V
470uF_2V
47pF_50v
24
R6628
7 CSP2
DRVL2
1
2
23
CSN1
8 GNDSNS
LL2
11-
22
330_5%
9 VSNS
VBST2
2
0402_OPEN
1
2
10
21
THERM
DRVH2
1
C6607
R6625
R6624
20K_1%
SBR3U40P1_OPEN
1
2
11-
CSN2
330_5%
4
3
2
1
D6601
1
1
2
2
C6618
S
R6611
47pF_50v
1 C9402
+VCCP
TPCA8057_H
0603_OPEN
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
Q6602
G
2 47pF_50v
1
2
1
2
D
C6616
47pF_50v
R6623
5
6
7
8
L6600
11-
1
2
CSP2
1
1
1
2
330_5%
R6652
R6620
3
4
0402_OPEN
56_5%
C6614
1
2
2
PAN_ETQP4LR36WFC_4P
R7002
1
2
2
0402_OPEN
4
3
2
1
TPCA8065_H
0_5%
Q6603
R6617
R6618
R6619
S
2
1
1
2
1
2
15-,19-,31-
H_DPRSTP#
1 R6621
16-
2
15-
VSSSENSE
PSI#
42.2K_1%
220K_5%
63.4K_1%
G
0_5%
C6613
1
H_VID6
R6632
16-
D
1
2
H_VID5
16-
2
0402_OPEN
200K_1%
1 R6622
H_VID4
2
16-
VCCSENSE
H_VID3
16-
5
6
7
8
0_5%
H_VID2
16-
C6623
16-
1
2
11-
CSP2
H_VID1
16-
C6615
1
H_VID0
0.01uF_50V
16-
11-
2
0402_OPEN
1 C6691
1 C6690
+VBAT_CPU
CSN2
11-
2 0402_OPEN
2 0402_OPEN
INVENTEC
TITLE
BR10ML
CPU POWER(VCC_CORE)
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
11
OF
52
41
PwPd
11
40
VR_TT#
V5FILT
12
39
DPRSTP#
ISLEW
13
38
PSI#
OSRSEL
14
37
VID6
TONSEL
15
36
VID5
TRIPSEL
16
35
VID4
PWRMON
17
34
VID3
VR_ON
18
33
VID2
CLK_EN#
19
32
VID1
DPRSLPVR
20
31
VID0
PGOOD
R6984 1
R6630
C4154
1
2
2
2
1
1
2
C6625
0.1uF_25v
2.2_5%
2.2_5%
0.1uF_25v

www.vinafix.vn

+V1.5S +V1.5 16-,24-,34-,47-,51- 8-,19-,23-,24-,26-,27- PAD6704 POWERPAD_2_0610 Q6719 6 4 D S 5 2 1 3
+V1.5S
+V1.5
16-,24-,34-,47-,51-
8-,19-,23-,24-,26-,27-
PAD6704
POWERPAD_2_0610
Q6719
6
4
D
S
5
2
1
3
G
R6739
AO6402AL
1
2
1 C6738
220K_5%
2 680pF_50v
1
R6740
200_5%
+V5A
2
7-,8-,9-,11-,30-,34-,38-,51-
Q6711
Q6715
+V5S
3
6
4
D
S
D
5
8-,12-
1
G
SLP_S3_3R
2
18-,29-,30-,32-,34-,36-,37-,40-,41-,42-,51-
S
1
3
2
G
SSM3K7002FU
AO6402AL
PAD6707
POWERPAD_2_0610
Q6712
6
4
D
S
5
2
1
3
G
R6735
AO6402AL
1
2
1 C6744
220K_5%
+V3S
2 680pF_50v
1
+V3LA
R6736
8-,9-,11-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
200_5%
5-,6-,7-,18-,31-,38-,40-,41-,48-,49-
2
PAD6705
+V15A
POWERPAD_2_0610
7-
Q6743
Q6716
3
D
6
4
D
S
8-,12-
1 G
SLP_S3_3R
1
5
470K_5%
2
1
3
SSM3K7002FU S 2
1
1
R6733
G
C6729
C6730
R6732
AO6402AL
2
22uF_6.3V
22uF_6.3V
1
2
C6737
2
2
1
Q6728
220K_5%
3
D
2
8-,12-
1
680pF_50v
SLP_S3_3R
G
2200pF_50V
1
S
2
C6731
R6734
SSM3K7002FU
200_5%
2
Q6710
3
D
1
8-,12-
1 G
SLP_S3_3R
S
2
2
SSM3K7002FU
+V0.75S
+V3LDO
8-,26-,27-
7-
1
R6745
1
200_5%_OPEN
R6780
10K_5%
2
2
8-,12-
SLP_S3_3R
Q6780
Q6723
3
3
D
D
8-,9-,32-,40-
1 G
1
SLP_S3#_3R
G
SSM3K7002FU S 2
SSM3K7002FU_OPEN S 2
INVENTEC
TITLE
BR10ML
POWER(SLEEP)
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
12
OF
52

www.vinafix.vn

+VCCP +VCCP_CLKGEN 9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51- +V3S +V3S_CLKGEN
+VCCP
+VCCP_CLKGEN
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
+V3S
+V3S_CLKGEN
8-,9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
Layout note: All decoupling 0.1uF disperse closed to pin
L4001
FBM_11_160808_121T
8-,9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
1
C4017
1
C4011
1
C4016
1
C4014
1
C4010
1
C4009
1
C4008
1
C4012
Layout note: All decoupling 0.1uF disperse closed to pin
8-,9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
2
2
2
2
2
2
2
2
L4000
10uF_10V
10uF_10V
0.1uF_16V
0.1uF_16V
0.1uF_16V
0.1uF_16V
0.1uF_16V
0.1uF_16V
FBM_11_160808_121T
+V3S
+V3S
C4021
1 1
C4018
C4013
1 1
C4019
1
C4020
+VCCP
2 2
10uF_10V
2 2
2
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
0.1uF_16V 0.1uF_16V 0.1uF_16V 0.1uF_16V
R4016
1
R4011
1
R4010
1K_5%
8-,9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
1
1
10K_5%_OPEN
10K_5%_OPEN
R4000 2
+V3S
R4006
1
15-,19-
CPU_BSEL0
R4007
U4001
2.2K_5%
2
2
10K_5%
10K_5%
26
48
2
2
VDDSRC_IO
NC
45
Stuff
OPEN
Card reader
VDDSRC_IO
36
38
32-
PCI_STOP#
PCISTOP#_3
VDDSRC_IO
12
37
32-
R967
22
1%
OPEN
CPUSTOP#_3
VDD96_IO
CPU_STOP#
39
VDDSRC_IO
CLK_NBCLK
R6029
22_1%
33_5%
61
51
21-
VDDREF
CPUT1_F
CLK_NBCLK
CLK_NBCLK#
20
50
21-
CLK_NBCLK#
+VCCP
VDDPLL3_IO
CPUC1_F
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
R4026
2 R4020
R4014
49
VDDCPU_IO
1
R4001
1
2
22_1%
CLK_CPUBCLK
46-
54
14-
CLK_R_CARD48
CPUT0
CLK_CPUBCLK
CLK_CPUBCLK#
53
14-
CLK_CPUBCLK#
CPUC0
R4027
32-
1
2
22_1%
CLK_R_SB48
2
9
47
VDD48
CPUT2_ITP_SRCT8
1 10K_5%
10K_5%
10K_5%
2
46
VDDPCI
CPUC2_ITP_SRCC8
55
2
VDDCPU
1
R4024
CLKREQ_LAN#
475_1%
16
33
1
2
R4003
44-
CLKREQ_R_LAN#
VDD
SRCT11_CR#_H
0402_OPEN
1K_5%
CLKREQ_WLAN#
475_1% 1
2
32
R4004
47-
SRCC11_CR#_G
CLKREQ_R_WLAN#
R4013
34
CLK_PCIE_LAN
44-
2
1
CLK_PCIE_LAN
SRCT10
CPU_BSEL0_USB48
10
35
CLK_PCIE_LAN#
44-
SUB_48MHZ_FSLA
SRCC10
CLK_PCIE_LAN#
15-,19-
57
CPU_BSEL1
FSLB_TEST_MODE
15-,19-
10K_5% 1
2
R4023
CLK_SB14
62
30
CLK_PCIE_WLAN
47-
CPU_BSEL2
CLK_PCIE_WLAN
REF0_FSLC_TEST_SEL
SRCT9
31
CLK_PCIE_WLAN#
47-
SRCC9
CLK_PCIE_WLAN#
R4019
32-
1
2
39_5%
32-
R4017
2
1
475_1%
CLKREQ_SATA#
1
CLK_R_SB14
CLKREQ_R_SATA#
PCI0_CR#_A
R4015
1
2
475_1%
19-
CLKREQ_MCH#
3
44
CLKREQ_R_MCH#
PCI1_CR#_B
SRCT7_CR#_F
40-
R4018
1
2
33_5%
CLK_KBPCI
4
43
CLK_R_KBPCI
PCI2_TME
SRCC7_CR#_E
5
2
PCI3
CLK_PCIE_SB
41
32-
CLK_PCIE_SB
SRCT6
1K_5%
CLK_PCIE_SB#
56
40
32-
CK_PWRGD_PD#
SRCC6
CLK_PCIE_SB#
1
R4021
R4022
CLK_3S_MINICARD2
64
6
33_5%
1
2
R4008
47-
1
R4025
0402_OPEN
SCLK
PCI4_27_Select
CLK_R_PCI_DEBUG
0402_OPEN
CLK_3S_ICHPCI
63
7
33_5% 1
2
R4002
33-
SDTAT
PCI_F5_ITP_EN
CLK_R_ICHPCI
2
60
27
CLK_PEG_MCH
19-
X1
SRCT4
CLK_PEG_MCH
32-
28
CLK_PEG_MCH#
19-
CLK_PWRGD
SRCC4
CLK_PEG_MCH#
59
X2
26-,27-,32-
24
ICH_3S_SMCLK
SRCT3_CR#_C
26-,27-,32-
8
25
ICH_3S_SMDATA
GNDPCI
SRCC3_CR#_D
11
GND48
15
21
CLK_SATA
31-
SRCT2_SATAT
CLK_SATA
GND
19
22
CLK_SATA#
31-
GND
SRCC2_SATAC
CLK_SATA#
23
GNDSRC
29
17
CLKSS1_DREF
19-
GNDSRC
27MHz_NonSS_SRCT1_SE1
CLKSS1_DREF
42
18
CLKSS1_DREF#
19-
X4000
27MHz_SS_SRCC1_SE2
CLKSS1_DREF#
GNDSRC
58
14.31818MHZ
GNDREF
CLK_DREF
52
13
19-
GNDCPU
SRCC0_DOTT_96
CLK_DREF
1
2
14
CLK_DREF#
19-
FSA
FSB
FSC
FSB CLOCK
HOST CLOCK
SRCT0_DOTC_96
CLK_DREF#
1 C4022
FREQUENCY
FREQUENCY
C4023
1
ICS_ICS9LPRS365BGLFT_A_TSSOP_64P
30PPM
2
1
1
0
667
166
27pF_50V
2 27pF_50V
0
1
0
800
200
8-,9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
Please place close to CLKGEN within 500mils
0
0
0
1066
266
+V3S
R4012
1
2
Byte6: bit7=0, disable CR#_E; 1,enable CR#_E
R4005
1
0402_OPEN
*CLKREQ# pin controls SRC Table.
CR#_E
10K_5%
1
R4009
2
2
SRC6
Byte5: bit6 =0(PWD)
Byte5: bit6 =1
Byte5: bit4 =0(PWD)
Byte5: bit4 =1
10K_5%
CR#_A
SRC0
SRC2
Byte6: bit6=0, disable CR#_F; 1,enable CR#_F
CR#_B
SRC1
SRC4
27_Select=0
LCD_SST 100MHz
CR#_F
27_Select=1
Byte5: bit7=0, disable CR#_A; 1,enable CR#_A
Byte5: bit5=0, disable CR#_B; 1,enable CR#_B
SRC8
27MHz NON-SPREAD CLOCK
Byte6: bit5=0, disable CR#_G; 1,enable CR#_G
CR#_G
Byte5: bit2 =0(PWD)
Byte5: bit2 =1
Byte5: bit0 =0(PWD)
Byte5: bit0 =1
SRC9
INVENTEC
Byte6: bit4=0, disable CR#_H; 1,enable CR#_H
CR#_C
SRC0
SRC2
SRC1
SRC4
CR#_D
TITLE
BR10ML
CR#_H
CLOCK_GENERATOR
Byte5: bit3=0, disable CR#_C; 1,enable CR#_C
Byte5: bit1=0, disable CR#_D; 1,enable CR#_D
SRC10
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
13
OF
52
1
2
1
2
2
1
2
1
1
2

www.vinafix.vn

21- CN4500-1 H_A#(35:3) H_A#(3) J4 H1 21- A3# ADS# H_ADS# +VCCP H_A#(4) L5 E2 21-
21-
CN4500-1
H_A#(35:3)
H_A#(3)
J4
H1
21-
A3#
ADS#
H_ADS#
+VCCP
H_A#(4)
L5
E2
21-
H_BNR#
A4#
BNR#
H_A#(5)
L4
G5
21-
A5#
BPRI#
H_BPRI#
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
H_A#(6)
K5
A6#
1
R4500
H_A#(7)
M3
H5
21-
H_DEFER#
A7#
DEFER#
56_5%
H_A#(8)
N2
F21
21-
A8#
DRDY#
H_DRDY#
CLOSED TO CPU
H_A#(9)
J1
E1
21-
A9#
DBSY#
H_DBSY#
H_A#(10)
N3
2
A10#
H_A#(11)
P5
F1
21-
A11#
BR0#
H_BREQ#0
H_A#(12)
P2
A12#
H_A#(13)
L2
D20
A13#
IERR#
H_A#(14)
P4
B3
31-
A14#
INIT#
H_INIT#
+VCCP
H_A#(15)
P1
51 ohm +/-1% pull-up to +VCCP
A15#
H_A#(16)
R1
H4
21-
A16#
LOCK#
H_LOCK#
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
R4502
1
(VCCP) if ITP is implemented
21-
M1
2
H_ADSTB#0
ADSTB0#
21-
C1
21-
21-
H_REQ#(4:0)
H_CPURST# 0402_OPEN
H_RS#(2:0)
RESET#
H_REQ#(0)
K3
F3
H_RS#(0)
REQ0#
RS0#
H_REQ#(1)
H2
F4
H_RS#(1)
REQ1#
RS1#
H_REQ#(2)
K2
G3
H_RS#(2)
REQ2#
RS2#
H_REQ#(3)
J3
G2
21-
REQ3#
TRDY#
H_TRDY#
H_REQ#(4)
L1
REQ4#
G6
21-
H_HIT#
HIT#
H_A#(17)
Y2
E4
21-
A17#
HITM#
H_HITM#
H_A#(18)
U5
A18#
H_A#(19)
R3
AD4
A19#
BPM0#
H_A#(20)
W6
AD3
A20#
BPM1#
H_A#(21)
U4
AD1
A21#
BPM2#
H_A#(22)
Y5
AC4
A22#
BPM3#
H_A#(23)
U1
AC2
A23#
PRDY#
H_A#(24)
14-
R4
AC1
A24#
PREQ#
H_BPM5_PREQ#
H_A#(25)
T5
AC5
14-
A25#
TCK
H_TCK
H_A#(26)
T3
AA6
14-
A26#
TDI
TDI_FLEX
H_A#(27)
W2
AB3
A27#
TDO
H_A#(28)
W5
AB5
14-
A28#
TMS
H_TMS
H_A#(29)
Y4
A29#
TRST#
AB6
H_A#(30)
U2
C20
32-
XDP_DBRESET#
A30#
DBR#
H_A#(31)
V4
A31#
1
R4507
H_A#(32)
W3
A32#
54.9_1%
H_A#(33)
AA4
+VCCP
THERMAL
PROCHOT#
A33#
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
H_A#(34)
AB2
A34#
H_A#(35)
AA3
D21
R4501
1
2
68_5%
2
A35#
PROCHOT#
10mils/10mils
18-
21-
V1
A24
H_ADSTB#1
H_THERMDA
ADSTB1#
THERMDA
B25
18-
THERMDC
THERM_MINUS
31-
H_A20M#
A20M#
31-
C7
18-,19-,31-
H_FERR#
FERR#
THERMTRIP#
PM_THRMTRIP#
31-
H_IGNNE#
IGNNE#
31-
H_STPCLK#
STPCLK#
31-
H CLK
H_INTR
LINT0
31-
B4
A22
13-
H_NMI
CLK_CPUBCLK
LINT1
BCLK0
31-
A3
A21
13-
H_SMI#
SMI#
BCLK1
CLK_CPUBCLK#
M4
RSVD01
N5
RESERVED
RSVD02
T2
RSVD03
+VCCP
V3
RSVD04
B2
RSVD05
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
C3
RSVD06
D2
RSVD07
R4503
1
2
14-
D22
RSVD08
H_BPM5_PREQ#
D3
RSVD09
54.9_1%
F6
RSVD010
R4504
1
2
14-
TDI_FLEX
54.9_1%
R4505
FOX_PZ4782A_274M_41_478P
1
2
14-
H_TMS
54.9_1%
R4506
1
2
14-
H_TCK
+VCCP
54.9_1%
GMCH
CPU
ICH9
INVENTEC
TITLE
BR10ML
PM_THRMTRIP# should be T at CPU
PENRYN-1
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
14
OF
52
ICH
ADDR GROUP 1
ADDR GROUP 0
XDP/ITP SIGNALS
CONTROL

www.vinafix.vn

15-,21- CN4500-2 15-,21- H_D#(63:0) H_D#(63:0) H_D#(0) E22 Y22 H_D#(32) D0# D32# H_D#(1) F24 AB24 H_D#(33)
15-,21-
CN4500-2
15-,21-
H_D#(63:0)
H_D#(63:0)
H_D#(0)
E22
Y22
H_D#(32)
D0#
D32#
H_D#(1)
F24
AB24
H_D#(33)
D1#
D33#
H_D#(2)
E26
V24
H_D#(34)
D2#
D34#
H_D#(3)
G22
V26
H_D#(35)
D3#
D35#
H_D#(4)
F23
V23
H_D#(36)
D4#
D36#
H_D#(5)
G25
T22
H_D#(37)
D5#
D37#
H_D#(6)
E25
U25
H_D#(38)
D6#
D38#
H_D#(7)
E23
U23
H_D#(39)
D7#
D39#
H_D#(8)
K24
Y25
H_D#(40)
D8#
D40#
H_D#(9)
G24
W22
H_D#(41)
D9#
D41#
H_D#(10)
J24
Y23
H_D#(42)
D10#
D42#
H_D#(11)
J23
W24
H_D#(43)
D11#
D43#
H_D#(12)
H22
W25
H_D#(44)
D12#
D44#
H_D#(13)
F26
AA23
H_D#(45)
D13#
D45#
H_D#(14)
K22
AA24
H_D#(46)
D14#
D46#
H_D#(15)
H23
AB25
H_D#(47)
D15#
D47#
21-
J26
Y26
21-
H_DSTBN#0
H_DSTBN#2
DSTBN0#
DSTBN2#
21-
H26
AA26
21-
H_DSTBP#0
DSTBP0#
DSTBP2#
H_DSTBP#2
21-
H25
U22
21-
H_DINV#0
DINV0#
DINV2#
H_DINV#2
15-,21-
15-,21-
H_D#(63:0)
H_D#(63:0)
H_D#(16)
N22
AE24
H_D#(48)
D16#
D48#
H_D#(17)
K25
AD24
H_D#(49)
D17#
D49#
H_D#(18)
P26
AA21
H_D#(50)
D18#
D50#
H_D#(19)
R23
AB22
H_D#(51)
D19#
D51#
H_D#(20)
L23
AB21
H_D#(52)
D20#
D52#
H_D#(21)
M24
AC26
H_D#(53)
D21#
D53#
H_D#(22)
L22
AD20
H_D#(54)
D22#
D54#
H_D#(23)
M23
AE22
H_D#(55)
D23#
D55#
H_D#(24)
P25
AF23
H_D#(56)
D24#
D56#
H_D#(25)
P23
AC25
H_D#(57)
D25#
D57#
H_D#(26)
P22
AE21
H_D#(58)
D26#
D58#
H_D#(27)
T24
AD21
H_D#(59)
D27#
D59#
H_D#(28)
R24
AC22
H_D#(60)
+VCCP
D28#
D60#
H_D#(29)
L25
AD23
H_D#(61)
D29#
D61#
H_D#(30)
T25
AF22
H_D#(62)
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
D30#
D62#
H_D#(31)
N25
AC23
H_D#(63)
1 R4510
D31#
D63#
21-
L26
AE25
21-
H_DSTBN#1
DSTBN1#
DSTBN3#
H_DSTBN#3
1K_1%
21-
M26
AF24
21-
H_DSTBP#1
DSTBP1#
DSTBP3#
H_DSTBP#3
21-
N24
AC20
21-
H_DINV#1
H_DINV#3
DINV1#
DINV3#
2 GTLREF
AD26
R26
R4512
1
2
27.4_1%
Note: COMP1 & COMP3 5-mil wide
GTLREF
COMP0
U26
R4513
1
2
54.9_1%
COMP0 & COMP2 18-mil wide
1 R4511
COMP1
C23
AA1
R4514
1
2
27.4_1%
TEST1
COMP2
2K_1%
D25
Y1
R4515 1
2
54.9_1%
Layout note: Zo=55 ohm,
TEST2
COMP3
C24
TEST3
MISC
AF26
E5
CLOSED TO CPU
2 0.5" max for GTLREF.
TEST4
DPRSTP#
H_DPRSTP#
11-,19-,31-
AF1
B5
31-
TEST5
DPSLP#
H_DPSLP#
A26
D24
21-
TEST6
DPWR#
H_DPWR#
D6
31-
PWRGOOD
H_PWRGD
13-,19-
B22
D7
21-
CPU_BSEL0
H_CPUSLP#
BSEL0
SLP#
13-,19-
B23
AE6
11-
CPU_BSEL1
BSEL1
PSI#
PSI#
13-,19-
C21
CPU_BSEL2
BSEL2
1
R4516
FOX_PZ4782A_274M_41_478P
0402_OPEN
2
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
INVENTEC
TITLE
BR10ML
PENRYN-2
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
15
OF
52
GRP 1 DATA GRP 0DATA
GRP 3 DATA GRP 2DATA

www.vinafix.vn

+VCC_CORE +VCC_CORE 11-,16-,51- 11-,16-,51- CN4500-3 A7 AB20 VCC001 VCC068 A9 AB7 VCC002 VCC069 A10 AC7
+VCC_CORE
+VCC_CORE
11-,16-,51-
11-,16-,51-
CN4500-3
A7
AB20
VCC001
VCC068
A9
AB7
VCC002
VCC069
A10
AC7
VCC003
VCC070
A12
AC9
VCC004
VCC071
C6653
C6652
C6651
C6650
A13
AC12
1
1
1
1
VCC005
VCC072
A15
AC13
VCC006
VCC073
A17
AC15
2
22uF_6.3V
2
22uF_6.3V
2
22uF_6.3V
2
22uF_6.3V
VCC007
VCC074
A18
AC17
VCC008
VCC075
A20
AC18
VCC009
VCC076
B7
AD7
VCC010
VCC077
B9
AD9
VCC011
VCC078
B10
AD10
VCC012
VCC079
B12
AD12
VCC013
VCC080
B14
AD14
VCC014
VCC081
B15
AD15
VCC015
VCC082
B17
AD17
VCC016
VCC083
B18
AD18
VCC017
VCC084
B20
AE9
VCC018
VCC085
C9
AE10
VCC019
VCC086
C10
AE12
VCC020
VCC087
C12
AE13
VCC021
VCC088
C6657
C6656
C6655
C6654
C13
AE15
1
1
1
1
VCC022
VCC089
C15
AE17
VCC023
VCC090
C17
AE18
2
10uF_6.3V
2
10uF_6.3V
2
10uF_6.3V
2
10uF_6.3V
VCC024
VCC091
C18
AE20
VCC025
VCC092
D9
AF9
VCC026
VCC093
D10
AF10
VCC027
VCC094
D12
AF12
VCC028
VCC095
+VCCP
D14
AF14
PLACE THESE INSIDE SOCKET
CAVITY ON L8 (NORTH SIDE
VCC029
VCC096
D15
AF15
SECONDARY)
VCC030
VCC097
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
D17
AF17
VCC031
VCC098
D18
AF18
VCC032
VCC099
+VCCP
E7
AF20
VCC033
VCC0100
E9
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
VCC034
E10
G21
VCC035
VCCP01
E12
V6
1
C4503
1
C4504
1
C4505
1
C4506
VCC036
VCCP02
1
C4507
1
C4508
E13
J6
VCC037
VCCP03
1
E15
K6
2
2
2
2
2
2
VCC038
VCCP04
C4509
C6661
C6660
C6659
C6658
E17
M6
0.1uF_16V
0.1uF_16V
0.1uF_16V
0.1uF_16V
0.1uF_16V
0.1uF_16V
1
1
1
1
VCC039
VCCP05
E18
J21
VCC040
VCCP06
2
E20
K21
220uF_2V
2
10uF_6.3V
2
10uF_6.3V
2
10uF_6.3V
2
10uF_6.3V
VCC041
VCCP07
F7
M21
VCC042
VCCP08
F9
N21
VCC043
VCCP09
F10
N6
VCC044
VCCP10
F12
R21
VCC045
VCCP11
F14
R6
VCC046
VCCP12
F15
T21
VCC047
VCCP13
F17
T6
+V1.5S
VCC048
VCCP14
F18
V21
VCC049
VCCP15
F20
W21
VCC050
VCCP16
12-,24-,34-,47-,51-
AA7
VCC051
AA9
B26
VCC052
VCCA01
AA10
C26
VCC053
VCCA02
AA12
VCC054
AA13
AD6
11-
VCC055
VID0
H_VID0
C6667
C6666
C6665
C6664
C6663
C6662
AA15
AF5
11-
VCC056
VID1
H_VID1
1
1
1
1
1
1
+VCC_CORE
AA17
AE5
11-
VCC057
VID2
H_VID2
AA18
AF4
11-
2
0805_OPEN
2
0805_OPEN
2
0805_OPEN
2
0805_OPEN
2
0805_OPEN
2
0805_OPEN
VCC058
VID3
H_VID3
11-,16-,51-
1
1
C4502
AA20
AE3
11-
C4501
VCC059
VID4
H_VID4
1
0.01uF_50V
10uF_6.3V
AB9
AF3
11-
VCC060
H_VID5
2
VID5
2
AC10
AE2
11-
R4518
VCC061
VID6
H_VID6
AB10
100_1%
VCC062
AB12
2
VCC063
LAYOUT NOTE:
AB14
AF7
11-
VCC064
VCCSENSE
VCCSENSE
PLACE C2461 NEAR PIN B26
AB15
VCC065
AB17
VCC066
AB18
AE7
11-
VCC067
VSSSENSE
VSSSENSE
FOX_PZ4782A_274M_41_478P
1
R4517
100_1%
2
LAYOUT NOTE:
ROUTE VCCSENSE AND VSSSENSE TRACE AT
24.7 OHM WITH 50 MIL SPACEING
PLACE PU AND PD WITHIN I INCH OF CPU
INVENTEC
TITLE
BR10ML
PENRYN-3
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
16
OF
52

www.vinafix.vn

CN4500-4 A4 P6 VSS001 VSS082 A8 P21 VSS002 VSS083 A11 P24 VSS003 VSS084 A14 R2
CN4500-4
A4
P6
VSS001
VSS082
A8
P21
VSS002
VSS083
A11
P24
VSS003
VSS084
A14
R2
VSS004
VSS085
A16
R5
VSS005
VSS086
A19
R22
VSS006
VSS087
A23
R25
VSS007
VSS088
AF2
T1
VSS008
VSS089
B6
T4
VSS009
VSS090
B8
T23
VSS010
VSS091
B11
T26
VSS011
VSS092
B13
U3
VSS012
VSS093
B16
U6
VSS013
VSS094
B19
U21
VSS014
VSS095
B21
U24
VSS015
VSS096
B24
V2
VSS016
VSS097
C5
V5
VSS017
VSS098
C8
V22
VSS018
VSS099
C11
V25
VSS019
VSS100
C14
W1
VSS020
VSS101
C16
W4
VSS021
VSS102
C19
W23
VSS022
VSS103
C2
W26
VSS023
VSS104
C22
Y3
VSS024
VSS105
C25
Y6
VSS025
VSS106
D1
Y21
VSS026
VSS107
D4
Y24
VSS027
VSS108
D8
AA2
VSS028
VSS109
D11
AA5
VSS029
VSS110
D13
AA8
VSS030
VSS111
D16
AA11
VSS031
VSS112
D19
AA14
VSS032
VSS113
D23
AA16
VSS033
VSS114
D26
AA19
VSS034
VSS115
E3
AA22
VSS035
VSS116
E6
AA25
VSS036
VSS117
E8
AB1
VSS037
VSS118
E11
AB4
VSS038
VSS119
E14
AB8
VSS039
VSS120
E16
AB11
VSS040
VSS121
E19
AB13
VSS041
VSS122
E21
AB16
VSS042
VSS123
E24
AB19
VSS043
VSS124
F5
AB23
VSS044
VSS125
F8
AB26
VSS045
VSS126
F11
AC3
VSS046
VSS127
F13
AC6
VSS047
VSS128
F16
AC8
VSS048
VSS129
F19
AC11
VSS049
VSS130
F2
AC14
VSS050
VSS131
F22
AC16
VSS051
VSS132
F25
AC19
VSS052
VSS133
G4
AC21
VSS053
VSS134
G1
AC24
VSS054
VSS135
G23
AD2
VSS055
VSS136
G26
AD5
VSS056
VSS137
H3
AD8
VSS057
VSS138
H6
AD11
VSS058
VSS139
H21
AD13
VSS059
VSS140
H24
AD16
VSS060
VSS141
J2
AD19
VSS061
VSS142
J5
AD22
VSS062
VSS143
J22
AD25
VSS063
VSS144
J25
AE1
VSS064
VSS145
K1
AE4
VSS065
VSS146
K4
AE8
VSS066
VSS147
K23
AE11
VSS067
VSS148
K26
AE14
VSS068
VSS149
L3
AE16
VSS069
VSS150
L6
AE19
VSS070
VSS151
L21
AE23
VSS071
VSS152
L24
AE26
VSS072
VSS153
M2
A2
VSS073
VSS154
M5
AF6
VSS074
VSS155
M22
AF8
VSS075
VSS156
M25
AF11
VSS076
VSS157
N1
AF13
VSS077
VSS158
N4
AF16
VSS078
VSS159
N23
AF19
VSS079
VSS160
N26
AF21
VSS080
VSS161
P3
A25
VSS081
VSS162
AF25
VSS163
FOX_PZ4782A_274M_41_478P
INVENTEC
TITLE
BR10ML
PENRYN-4
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
17
OF
52

www.vinafix.vn

12-,29-,30-,32-,34-,36-,37-,40-,41-,42-,51- +V5S +V5S_FAN PAD4300 POWERPAD1x1m C4307 C4301 1 L4300 C4302 1 1 1
12-,29-,30-,32-,34-,36-,37-,40-,41-,42-,51-
+V5S
+V5S_FAN
PAD4300
POWERPAD1x1m
C4307
C4301 1
L4300
C4302
1
1
1
2
KC_FBM_11_160808_101A20T_2P_OPEN
2
2
0.1uF_16V
2
0805_OPEN
4.7uF_6.3V
+V3S
8-,9-,11-,12-,13-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
1
R4300
CN4300
10K_5%
1
1
2
2
G1
2
G
3
G2
FAN_TACH1
3
G
40-
4
+V3S
4
1
1
C4300
C4305
ACES_50271_0040N_001_4P
8-,9-,11-,12-,13-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
0402_OPEN 2
2
220pF_50V
1 R4306
10K_5%
2
R4305
40-
1
2
FAN1_PWM
0_5%
C4306
1
2
FAN CN
0402_OPEN
11-,32-,40-
VR_PWRGD
1
R4451
6-,18-
THRM_SHUTDWN#
2M_5%
+V5LA
2
6-,7-
Q4451
3
D
1 G
S
U4440
2
R4440
R4441
SSM3K7002FU
1
2
5
1
1
2
VCC
SET
150_5%
37.4K_1%
Q4450
C
2
1 C4450
GND
R4450
C
14-,19-,31-
1
2
B
B
PM_THRMTRIP#
1
4
3
6-,18-
THRM_SHUTDWN#
330_5%
E
2 0402_OPEN
C4440
HYST
OT
E
MMBT4401
2
GMT_G708T1U_SOT23_5P
0.1uF_16V
+V3LA
5-,6-,7-,12-,31-,38-,40-,41-,48-,49-
Thermal shoutdown at 86.1C +/-3C from 60C to 100C
RSET=0.0012*T - 0.9308*T+96.147
2
1
C4451
2
Hysteresis is 30C
0.1uF_16V
C4452
100pF_50v
1
2
U4450
5-,40-
1
8
EC_SMB2_CLK
VDD
SCL
14-
5-,40-
2
7
EC_SMB2_DATA
H_THERMDA
D+
SDA
14-
3
6
THERM_MINUS
D-
ALERT
6-,18-
4
5
THRM_SHUTDWN#
T_CRIT_A
GND
WINB_W83L771AWG_TSSOP_8P
Thermal Sensor For CPU
INVENTEC
LAYOUT NOTES: PUT THE THERMAL SENSOR CLOSE TO CPU
TITLE
BR10ML
THERMAL&FAN CONTROLLER
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
18
OF
52

www.vinafix.vn

MCH_CFG(9) LOW=DMIx2 MCH_CFG(7) LOW=RSVD LOW=Reverse Lane MCH_CFG(5) PCIE Graphics HIGH=DMIx4 (CPU Strap)
MCH_CFG(9)
LOW=DMIx2
MCH_CFG(7)
LOW=RSVD
LOW=Reverse Lane
MCH_CFG(5)
PCIE Graphics
HIGH=DMIx4
(CPU Strap)
HIGH=Mobile CPU
HIGH=Normal operation
Lane
NOTE : USE 4K-OHM RESISTOR WHEN INSTALLING
PULL-UP/PULL-DOWN RESISTOR ON ANY
MCH-CFG CONNECTION/PINS.
LOW=Dynamic ODT
LOW=TPM
MCH_CFG(13:12)
00=PARTIAL CLOCK GATING DISABLE
01=XOR MODE ENABLE
10=ALL-Z MODE ENABLE
11=NORMAL OPERATION
MCH_CFG(16)
MCH_CFG(6)
Disable
Enable
(FSB Dynamic
HIGH=Dynamic ODT
HIGH=TPM
XOR/ALLZ
ODT)
Enable
Disable
U4500-2
M36
RSVD1
N36
AP24
26-
8-,9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
RSVD2
SA_CK_0
MA_CLK_DDR1
NOTE: CFG[2:0] STRP : 010b : 800 MT/S
011b : 667 MT/S
R33
AT21
26-
+V3S
RSVD3
SA_CK_1
MA_CLK_DDR2
T33
AV24
27-
RSVD4
SB_CK_0
MB_CLK_DDR1
AH9
AU20
27-
RSVD5
SB_CK_1
MB_CLK_DDR2
19-
AH10
MCH_CFG(5)
RSVD6
+V1.5
19-
AH12
AR24
26-
MCH_CFG(6)
RSVD7
SA_CK#_0
MA_CLK_DDR1#
19-
AH13
AR21
26-
MCH_CFG(7)
RSVD8
SA_CK#_1
MA_CLK_DDR2#
8-,12-,19-,23-,24-,26-,27-
19-
K12
AU24
27-
MCH_CFG(9)
RSVD9
SB_CK#_0
MB_CLK_DDR1#
AL34
AV20
27-
MB_CLK_DDR2#
1
R4519
1 R4520
1
R4521
1 R4522
1
R4523
1 R4524
RSVD10
SB_CK#_1
AK34
RSVD11
2.2K_1%
0402_OPEN
0402_OPEN
0402_OPEN
0402_OPEN
0402_OPEN
AN35
BC28
26-
RSVD12
SA_CKE_0
MA_CKE0
R4533
AM35
AY28
26-
RSVD13
SA_CKE_1
MA_CKE1
80.6_1%
2
2
2
2
2
2
T24
AY36
27-
RSVD14
SB_CKE_0
MB_CKE0
27-
SB_CKE_1
MB_CKE1
B31
BB36
RSVD15
AJ6
BA17
26-
19-
RSVD16
SA_CS#_0
MA_CS0#
SM_RCOMP
19-
M1
AY16
26-
MCH_CFG(19)
RSVD17
SA_CS#_1
MA_CS1#
AV16
27-
19-
SB_CS#_0
MB_CS0#
SM_RCOMP#
19-
AR13
27-
MCH_CFG(20)
SB_CS#_1
MB_CS1#
19-
AY21
MCH_CFG(10)
RSVD20
19-
BD17
26-
MCH_CFG(12)
SA_ODT_0
MA_ODT0
R4532
19-
AY17
26-
MCH_CFG(13)
SA_ODT_1
MA_ODT1
80.6_1%
19-
A47
BF15
27-
MCH_CFG(16)
RSVD21
SB_ODT_0
MB_ODT0
BG23
AY13
27-
MB_ODT1
R4538
R4539
1
R4541
SB_ODT_1
1
1
1 R4540
RSVD22
R4535 1
2 1K_5%
13-,15-
BF23
RSVD23
0402_OPEN
0402_OPEN
0402_OPEN
0402_OPEN CPU_BSEL0
BH18
BG22
19-
SM_RCOMP
SM_RCOMP
R4536 1
RSVD24
1K_5%
13-,15-
2
BF18
BH21
19-
CPU_BSEL1
RSVD25
SM_RCOMP#
SM_RCOMP#
2
2
2
2
R4537
1K_5%
1
2
13-,15-
BF28
19-
CPU_BSEL2
SM_RCOMP_VOH
SM_RCOMP_VOH
BH28
19-
SM_RCOMP_VOL
SM_RCOMP_VOL
T25
CFG_0
R25
AV42
8-,26-,27-
CFG_1
SM_VREF
M_VREF
19-
P25
AR36
8-
MCH_CFG(17:3)
CFG_2
SM_PWROK
SM_PWROK
MCH_CFG(3)
P20
BF17
R4534
1
2
499_1%
CFG_3
SM_REXT
MCH_CFG(4)
P24
BC36
TP4500
26-,27-
1
CFG_4
SM_DRAMRST#
SM_DRAMRST#
C4515
MCH_CFG(5)
C25
+V3S
CFG_5
MCH_CFG(6)
N24
B38
13-
2
CFG_6
DPLL_REF_CLK
CLK_DREF
0.1uF_16V
MCH_CFG(7)
M24
A38
13-
8-,9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
CFG_7
DPLL_REF_CLK#
CLK_DREF#
MCH_CFG(8)
E21
E41
13-
CFG_8
DPLL_REF_SSCLK
CLKSS1_DREF
MCH_CFG(9)
C23
F41
13-
CFG_9
DPLL_REF_SSCLK#
CLKSS1_DREF#
MCH_CFG(10)
C24
CFG_10
1
2
19-,26-
MCH_CFG(11)
N21
F43
PM_EXTTS#0
CFG_11
PEG_CLK
CLK_PEG_MCH
R4525
10K_5%
MCH_CFG(12)
P21
E43
13-
CFG_12
PEG_CLK#
CLK_PEG_MCH#
1
2
19-,27-
MCH_CFG(13)
T21
32-
PM_EXTTS#1
CFG_13
DMI_TXN(3:0)
R4526
10K_5%
MCH_CFG(14)
R20
AE41
DMI_TXN(0)
CFG_14
DMI_RXN_0
MCH_CFG(15)
M20
AE37
DMI_TXN(1)
CFG_15
DMI_RXN_1
MCH_CFG(16)
L21
AE47
DMI_TXN(2)
CFG_16
DMI_RXN_2
TP4501
H21
AH39
DMI_TXN(3)
CFG_17
DMI_RXN_3
TP4502
P29
32-
CFG_18
DMI_TXP(3:0)
19-
R28
AE40
DMI_TXP(0)
MCH_CFG(19)
CFG_19
DMI_RXP_0
19-
T28
AE38
DMI_TXP(1)
MCH_CFG(20)
CFG_20
DMI_RXP_1
AE48
DMI_TXP(2)
DMI_RXP_2
AH40
DMI_TXP(3)
DMI_RXP_3
32-
DMI_RXN(3:0)
32-
R29
AE35
DMI_RXN(0)
PM_SYNC#
PM_SYNC#
DMI_TXN_0
+VCCP
11-,15-,31-
B7
AE43
DMI_RXN(1)
H_DPRSTP#
PM_DPRSTP#
DMI_TXN_1
R4531
19-,26-
PM_EXTTS#0
N33
AE46
DMI_RXN(2)
PM_EXTTS#0
PM_EXT_TS#_0
0_5%_OPEN
19-,27-
PM_EXTTS#1
P32
AH42
DMI_RXN(3)
PM_EXTTS#1
PM_EXT_TS#_1
32-
2
AT40
32-
VR_PWRGD_CK505
PWROK
DMI_TXN_2
DMI_TXN_3
1
DMI_RXP(3:0)
1
R4542
R4530
1
2
100_5%
33-,40-
AT11
AD35
DMI_RXP(0)
PLT_RST#
+V1.5
RSTIN#
DMI_TXP_0
1K_1%
19-,32-,40-
14-,18-,31-
T20
AE44
DMI_RXP(1)
PM_PWROK
PM_THRMTRIP#
THERMTRIP#
DMI_TXP_1
11-,32-
R32
AF46
DMI_RXP(2)
8-,12-,19-,23-,24-,26-,27-
PM_DPRSLPVR
DPRSLPVR
DMI_TXP_2
AH43
DMI_RXP(3)
2
DMI_TXP_3
1
R4527
B33
GFX_VID_0
1
1K_1%
C4516
BG48
B32
NC_1
GFX_VID_1
BF48
G33
2
R4543
NC_2
GFX_VID_2
BD48
F33
2
499_1%
NC_3
GFX_VID_3
0.1uF_16V
19-
BC48
E33
SM_RCOMP_VOH
NC_4
GFX_VID_4
BH47
1 R4529
NC_5
C4511
C4512
BG47
1
1
NC_6
3K_1%
BE47
NC_7
BH46
C34
2
2
NC_8
GFX_VR_EN
2 2.2uF_6.3V
0.01uF_50V
BF46
NC_9
4 mils/ 7mils
BG45
NC_10
BH44
AH37
32-
NC_11
CL_CLK
CL_CLK0
BH43
AH36
32-
NC_12
CL_DATA
CL_DATA0
BH6
AN36
19-,32-,40-
NC_13
CL_PWROK
PM_PWROK
iHDMI enable : stuff
19-
BH5
AJ35
32-
SM_RCOMP_VOL
NC_14
CL_RST#
CL_RST#0
iHDMI disnable : no stuff
BG4
AH34
1 R4528
NC_15
CL_VREF
1 C4514
C4513
BH3
1
NC_16
1K_1%
BF3
N28
NC_17
DDPC_CTRLCLK
BH2
M28
2
NC_18
DDPC_CTRLDATA
2 0.01uF_50V
2 2.2uF_6.3V
BG2
G36
NC_19
SDVO_CTRLCLK
BE2
E36
NC_20
SDVO_CTRLDATA
BG1
K36
13-
NC_21
CLKREQ#
CLKREQ_R_MCH#
R7087
BF1
H36
32-
NC_22
ICH_SYNC#
MCH_ICH_SYNC#
2
1
BD1
NC_23
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
+VCCP
BC1
NC_24
0_5%
iHDMI enable : no stuff
56_5%
R7086
F1
B12
NC_25
TSATN
iHDMI disnable : stuff
INVENTEC
B28
MCH_CFG(20)
HDA_BCLK
B30
TITLE
HDA_RST#
DIGITAL DISPLAY
LOW=ONLY DIGITAL DISPLAY PORT
(SDVO/DP/iHDMI)OR PCIEIS OPERATIONAL
HIGH= DIGITAL DISPLAY PORT
(SDVO/DP/iHDMI)AND PCIE ARE OPERATING
VIA THE PEG PORT
BR10ML
MCH_CFG(19)
B29
LOW=NORMAL
HDA_SDI
C29
PORT(SDVO/DP/iHDMI)
(DMI LANE
HDA_SDO
CANTIGA-1
A28
HIGH=LANES REVERSED
HDA_SYNC
REVERSAL)
SIZE
CODE
DOC. NUMBER
REV
CONCURRENT WITH PCIE
ITL_CANTIGA_GM_FCBGA_1329P
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
19
OF
52
2
1
12
12
12

9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-

www.vinafix.vn

+V3S 8-,9-,11-,12-,13-,18-,19-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51- R7064 R7068 10K_5%
+V3S
8-,9-,11-,12-,13-,18-,19-,24-,26-,27-,29-,30-,31-,32-,33-,34-,40-,41-,42-,43-,44-,46-,47-,51-
R7064
R7068
10K_5%
10K_5%
+VCCP
9-,11-,13-,14-,15-,16-,19-,21-,23-,24-,31-,34-,51-
U4500-3
R7060
0_5%
1
2
30-,40-
L32
INV_PWM_3
L_BKLT_CTRL
R7069
30-,40-
G32
T37
1
2
LCM_BKLTEN
L_BKLT_EN
PEG_COMPI
M32
T36
L_CTRL_CLK
PEG_COMPO
49.9_1%
1
R7054
M33
L_CTRL_DATA
100K_1%
30-
K33
H44
LVDS_DDC_CLK
L_DDC_CLK
PEG_RX#_0
2
30-
J33
J46
LVDS_DDC_DATA
L_DDC_DATA
PEG_RX#_1
L44
PEG_RX#_2
L40
PEG_RX#_3
30-
M29
N41
LCM_3S_VDDEN
L_VDD_EN
PEG_RX#_4
C44
P48
LVDS_IBG
PEG_RX#_5
B43
N44
LVDS_VBG
PEG_RX#_6
1
1
E37
T43
LVDS_VREFH
PEG_RX#_7
R7058
R7059
E38
U43
LVDS_VREFL
100K_1%
2.4K_1%
30-
C41
Y43
LVDS_TXCLN
LVDSA_CLK#
PEG_RX#_9
2
2
30-
C40
PEG_RX#_8
Y48
LVDS_TXCLP
LVDSA_CLK
B37
LVDSB_CLK#
PEG_RX#_10
Y36
PEG_RX#_11
A37
AA43
LVDSB_CLK
PEG_RX#_12
AD37
PEG_RX#_13
30-
H47
AC47
LVDS_TXDL0N
LVDSA_DATA#_0
PEG_RX#_14
30-
E46
AD39
LVDS_TXDL1N
LVDSA_DATA#_1
PEG_RX#_15
30-
G40
LVDS_TXDL2N
LVDSA_DATA#_2
A40
H43
LVDSA_DATA#_3
PEG_RX_0
J44
PEG_RX_1
30-
H48
L43
LVDS_TXDL0P
LVDSA_DATA_0
PEG_RX_2
30-
D45
L41
LVDS_TXDL1P
LVDSA_DATA_1
PEG_RX_3
30-
F40
N40
LVDS_TXDL2P
LVDSA_DATA_2
PEG_RX_4
B40
P47
LVDSA_DATA_3
PEG_RX_5
N43
PEG_RX_6
A41
T42
LVDSB_DATA#_0
PEG_RX_7
H38
U42
LVDSB_DATA#_1
PEG_RX_8
G37
Y42
LVDSB_DATA#_2
PEG_RX_9
J37
W47
LVDSB_DATA#_3
PEG_RX_10
Y37
PEG_RX_11
B42
AA42
LVDSB_DATA_0
PEG_RX_12
G38
AD36
LVDSB_DATA_1
PEG_RX_13
F37
AC48
LVDSB_DATA_2
PEG_RX_14
K37
AD40
LVDSB_DATA_3
PEG_RX_15
J41
PEG_TX#_0
M46
PEG_TX#_1
R7065
1 2
75_1%
F25
M47
TVA_DAC
PEG_TX#_2
R7066
1 2 75_1%
H25
M40
TVB_DAC
PEG_TX#_3
R7067
1 2
75_1%
K25
M42
TVC_DAC
PEG_TX#_4
R48
PEG_TX#_5
H24
N38
TV_RTN
PEG_TX#_6
T40
PEG_TX#_7
U37
PEG_TX#_8
U40
PEG_TX#_9
C31
Y40
TV_DCONSEL_0
PEG_TX#_10
E32
AA46
TV_DCONSEL_1
PEG_TX#_11
AA37
PEG_TX#_12
AA40
PEG_TX#_13
AD43
PEG_TX#_14
AC46
R7055
PEG_TX#_15
2
1
20-,29-
CRT_R
20-,29-
E28
J42
150_1%
CRT_B
CRT_BLUE
PEG_TX_0
Trace Wd: 11mil(to R)
L46
R7056
PEG_TX_1
2
1
20-,29-
20-,29-
G28
M48
CRT_G
Trace Wd: 4mil(to Conn)
CRT_G
CRT_GREEN
PEG_TX_2
150_1%
20-,29-
J28
M39
PEG_TX_3
M43
CRT_R
R7057
CRT_RED
PEG_TX_4
2
1
20-,29-
R47
CRT_B
PEG_TX_5
G29
N37
150_1%
CRT_IRTN
PEG_TX_6
T39
PEG_TX_7
CLOSE TO CALISTOGA
29-
H32
U36
CRT_DDCCLK
CRT_DDC_CLK
PEG_TX_8
29-
J32
U39
CRT_DDCDATA
CRT_DDC_DATA
PEG_TX_9
R7062
1
2
CRT_H
29-
J29
Y39
CRT_HSYNC
CRT_HSYNC
PEG_TX_10
30_5%
E29
Y46
CRT_TVO_IREF
PEG_TX_11
29-
1
R7063
2
CRT_V
L29
AA36
CRT_VSYNC
CRT_VSYNC
PEG_TX_12
30_5%
AA39
PEG_TX_13
AD42
PEG_TX_14
AD46
PEG_TX_15
R7061
1.02K_0.5%
ITL_CANTIGA_GM_FCBGA_1329P
Close GMCH and away form any signal (spacing>30mil)
INVENTEC
TITLE
BR10ML
CANTIGA-2
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
20
OF
52
12
12
12

www.vinafix.vn

15- 14- H_D#(63:0) H_A#(35:3) U4500-1 A14 H_A#(3) H_A#_3 H_D#(0) H_A#(4) F2 C15 H_D#_0 H_A#_4 H_D#(1)
15-
14-
H_D#(63:0)
H_A#(35:3)
U4500-1
A14
H_A#(3)
H_A#_3
H_D#(0)
H_A#(4)
F2
C15
H_D#_0
H_A#_4
H_D#(1)
H_A#(5)
G8
F16
H_D#_1
H_A#_5
H_D#(2)
F8
H13
H_A#(6)
H_D#_2
H_A#_6
H_D#(3)
H_A#(7)
E6
C18
H_D#_3
H_A#_7
H_D#(4)
G2
M16
H_A#(8)
H_D#_4
H_A#_8
H_D#(5)
H_A#(9)
H6
J13
H_D#_5
H_A#_9
H_D#(6)
H_A#(10)
H2
P16
H_D#_6
H_A#_10
H_D#(7)
F6
R16
H_A#(11)
H_D#_7
H_A#_11
H_D#(8)
H_A#(12)
D4
N17
H_D#_8
H_A#_12
H_D#(9)
H_A#(13)
H3
M13
H_D#_9
H_A#_13
H_D#(10)
M9
E17
H_A#(14)
H_D#_10
H_A#_14
H_D#(11)
H_A#(15)
M11
P17
H_D#_11
H_A#_15
H_D#(12)
H_A#(16)
J1
F17
H_D#_12
H_A#_16
H_D#(13)
J2
G20
H_A#(17)
H_D#_13
H_A#_17
H_D#(14)
H_A#(18)
N12
B19
H_D#_14
H_A#_18
H_D#(15)
H_A#(19)
J6
J16
H_D#_15
H_A#_19
H_D#(16)
P2
E20
H_A#(20)
H_D#_16
H_A#_20
H_D#(17)
H_A#(21)
L2
H16
H_D#_17
H_A#_21
H_D#(18)
H_A#(22)
R2
J20
H_D#_18
H_A#_22
H_D#(19)
N9
L17
H_A#(23)
H_D#_19
H_A#_23
H_D#(20)
H_A#(24)
L6
A17
H_D#_20
H_A#_24
H_D#(21)
H_A#(25)
M5
B17
H_D#_21
H_A#_25
H_D#(22)
J3
L16
H_A#(26)
H_D#_22
H_A#_26
H_D#(23)
H_A#(27)
N2
C21
H_D#_23
H_A#_27
H_D#(24)
R1
J17
H_A#(28)
H_D#_24
H_A#_28
H_D#(25)
H_A#(29)
N5
H20
H_D#_25
H_A#_29
H_D#(26)
H_A#(30)
N6
B18
H_D#_26
H_A#_30
H_D#(27)
P13
K17
H_A#(31)
+VCCP
H_D#_27
H_A#_31
H_D#(28)
H_A#(32)
N8
B20
H_D#_28
H_A#_32
H_D#(29)
H_A#(33)
L7
F21
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
H_D#_29
H_A#_33
H_D#(30)
N10
K21
H_A#(34)
H_D#_30
H_A#_34
1
H_D#(31)
H_A#(35)
M3
L20
H_D#_31
H_A#_35
R4566
H_D#(32)
Y3
H_D#_32
H_D#(33)
AD14
H12
14-
221_1%
H_D#_33
H_ADS#
H_ADS#
2
H_D#(34)
Y6
B16
14-
H_D#_34
H_ADSTB#_0
H_ADSTB#0
21-
H_D#(35)
Y10
G17
14-
MCH_HSWING
H_D#_35
H_ADSTB#_1
H_ADSTB#1
H_D#(36)
Y12
A9
14-
H_D#_36
H_BNR#
H_BNR#
1
1
H_D#(37)
Y14
F11
14-
H_D#_37
H_BPRI#
H_BPRI#
C4517
R4565
H_D#(38)
Y7
G12
14-
H_D#_38
H_BREQ#
H_BREQ#0
2
H_D#(39)
W2
E9
14-
100_1%
H_D#_39
H_DEFER#
H_DEFER#
0.1uF_16V
2
H_D#(40)
AA8
B10
14-
H_D#_40
H_DBSY#
H_DBSY#
H_D#(41)
Y9
AH7
13-
H_D#_41
HPLL_CLK
CLK_NBCLK
H_D#(42)
AA13
AH6
13-
H_D#_42
HPLL_CLK#
CLK_NBCLK#
H_D#(43)
AA9
J11
15-
H_D#_43
H_DPWR#
H_DPWR#
H_D#(44)
AA11
F9
14-
H_D#_44
H_DRDY#
H_DRDY#
H_D#(45)
AD11
H9
14-
H_D#_45
H_HIT#
H_HIT#
H_D#(46)
AD10
E12
14-
H_D#_46
H_HITM#
H_HITM#
H_D#(47)
AD13
H11
14-
H_D#_47
H_LOCK#
H_LOCK#
H_D#(48)
AE12
C9
14-
H_D#_48
H_TRDY#
H_TRDY#
H_D#(49)
AE9
H_D#_49
H_D#(50)
AA2
H_D#_50
H_D#(51)
AD8
H_D#_51
H_D#(52)
AA3
H_D#_52
H_D#(53)
AD3
J8
15-
H_D#_53
H_DINV#_0
H_DINV#0
R4564
1
2
24.9_1%
21-
H_D#(54)
AD7
L3
15-
MCH_HRCOMP
H_D#_54
H_DINV#_1
H_DINV#1
H_D#(55)
AE14
Y13
15-
H_D#_55
H_DINV#_2
H_DINV#2
H_D#(56)
AF3
Y1
15-
H_D#_56
H_DINV#_3
H_DINV#3
H_D#(57)
AC1
H_D#_57
H_D#(58)
AE3
L10
15-
H_D#_58
H_DSTBN#_0
H_DSTBN#0
H_D#(59)
AC3
M7
15-
H_D#_59
H_DSTBN#_1
H_DSTBN#1
H_D#(60)
AE11
AA5
15-
H_D#_60
H_DSTBN#_2
H_DSTBN#2
H_D#(61)
AE8
AE6
15-
H_D#_61
H_DSTBN#_3
H_DSTBN#3
Layout notes:
H_D#(62)
AG2
H_D#_62
H_D#(63)
AD6
L9
15-
Trace need be 10 mils wide with 20 mils
H_D#_63
H_DSTBP#_0
H_DSTBP#0
M8
15-
H_DSTBP#_1
H_DSTBP#1
AA6
15-
14-
H_DSTBP#_2
H_DSTBP#2
H_REQ#(4:0)
21-
C5
AE5
15-
MCH_HSWING
H_SWING
H_DSTBP#_3
H_DSTBP#3
21-
E3
MCH_HRCOMP
H_RCOMP
B15
H_REQ#(0)
H_REQ#_0
K13
H_REQ#(1)
H_REQ#_1
F13
H_REQ#(2)
H_REQ#_2
B13
H_REQ#(3)
14-
H_REQ#_3
H_RS#(2:0)
14-
C12
B14
H_REQ#(4)
H_CPURST#
H_CPURST#
H_REQ#_4
15-
E11
H_CPUSLP#
H_CPUSLP#
B6
H_RS#(0)
H_RS#_0
F12
H_RS#(1)
H_RS#_1
C8
H_RS#(2)
H_RS#_2
A11
+VCCP
H_AVREF
B11
H_DVREF
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,51-
ITL_CANTIGA_GM_FCBGA_1329P
1
R4567
1K_1%
2
1
R4568
1 C4518
2K_1%
2 0.1uF_16V
2
INVENTEC
TITLE
BR10ML
CANTIGA-3-HOST
SIZE
CODE
DOC. NUMBER
REV
A3
CS
CHANGE by
Chou, Stanly
9-Dec-2010
SHEET
21
OF
52

www.vinafix.vn

MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1
MB_DATA(63:0) MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1

MB_DATA(63:0)

MA_DATA(63:0) 27- U4500-4 AJ38 BD21 26- SA_DQ_0 SA_BS_0 MA_BA0 AJ41 BG18 26- SA_DQ_1 SA_BS_1 MA_BA1
MA_DATA(63:0)
27-
U4500-4
AJ38
BD21
26-
SA_DQ_0
SA_BS_0
MA_BA0
AJ41
BG18
26-
SA_DQ_1
SA_BS_1
MA_BA1
AN38
AT25
26-
SA_DQ_2
SA_BS_2
MA_BA2
AM38
SA_DQ_3
AJ36
BB20
26-
SA_DQ_4
SA_RAS#
MA_RAS#
AJ40
BD20
26-
SA_DQ_5
SA_CAS#
MA_CAS#
AM44
AY20
26-
SA_DQ_6
SA_WE#
MA_WE#
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
26-
SA_DQ_10
MA_DM(7:0)
AT38
AM37
MA_DM(0)
SA_DQ_11
SA_DM_0
AN41
AT41
MA_DM(1)
SA_DQ_12
SA_DM_1
AN39
AY41
MA_DM(2)
SA_DQ_13
SA_DM_2
AU44
AU39
MA_DM(3)
SA_DQ_14
SA_DM_3
AU42
BB12
MA_DM(4)
SA_DQ_15
SA_DM_4
AV39
AY6
MA_DM(5)
SA_DQ_16
SA_DM_5
AY44
AT7
MA_DM(6)
SA_DQ_17
SA_DM_6
BA40
AJ5
MA_DM(7)
SA_DQ_18
SA_DM_7
BD43
26-
SA_DQ_19
MA_DQS(7:0)
AV41
AJ44
MA_DQS(0)
SA_DQ_20
SA_DQS_0
AY43
AT44
MA_DQS(1)
SA_DQ_21
SA_DQS_1
BB41
BA43
MA_DQS(2)
SA_DQ_22
SA_DQS_2
BC40
BC37
MA_DQS(3)
SA_DQ_23
SA_DQS_3
AY37
AW12
MA_DQS(4)
SA_DQ_24
SA_DQS_4
BD38
BC8
MA_DQS(5)
SA_DQ_25
SA_DQS_5
AV37
AU8
MA_DQS(6)
SA_DQ_26
SA_DQS_6
AT36
AM7
MA_DQS(7)
26-
SA_DQ_27
SA_DQS_7
MA_DQS#(7:0)
AY38
AJ43
MA_DQS#(0)
SA_DQ_28
SA_DQS#_0
BB38
AT43
MA_DQS#(1)
SA_DQ_29
SA_DQS#_1
AV36
BA44
MA_DQS#(2)
SA_DQ_30
SA_DQS#_2
AW36
BD37
MA_DQS#(3)
SA_DQ_31
SA_DQS#_3
BD13
AY12
MA_DQS#(4)
SA_DQ_32
SA_DQS#_4
AU11
BD8
MA_DQS#(5)
SA_DQ_33
SA_DQS#_5
BC11
AU9
MA_DQS#(6)
SA_DQ_34
SA_DQS#_6
BA12
AM8
MA_DQS#(7)
26-
SA_DQ_35
SA_DQS#_7
MA_A(14:0)
AU13
SA_DQ_36
AV13
BA21
MA_A(0)
SA_DQ_37
SA_MA_0
BD12
BC24
MA_A(1)
SA_DQ_38
SA_MA_1
BC12
BG24
MA_A(2)
SA_DQ_39
SA_MA_2
BB9
BH24
MA_A(3)
SA_DQ_40
SA_MA_3
BA9
BG25
MA_A(4)
SA_DQ_41
SA_MA_4
AU10
BA24
MA_A(5)
SA_DQ_42
SA_MA_5
AV9
BD24
MA_A(6)
SA_DQ_43
SA_MA_6
BA11
BG27
MA_A(7)
SA_DQ_44
SA_MA_7
BD9
BF25
MA_A(8)
SA_DQ_45
SA_MA_8
AY8
AW24
MA_A(9)
SA_DQ_46
SA_MA_9
BA6
BC21
MA_A(10)
SA_DQ_47
SA_MA_10
AV5
BG26
MA_A(11)
SA_DQ_48
SA_MA_11
AV7
BH26
MA_A(12)
SA_DQ_49
SA_MA_12
AT9
BH17
MA_A(13)
SA_DQ_50
SA_MA_13
AN8
AY25
MA_A(14)
SA_DQ_51
SA_MA_14
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
ITL_CANTIGA_GM_FCBGA_1329P
 

U4500-5

AK47

SB_DQ_0

SB_BS_0

AH46

SB_DQ_1

SB_BS_1

AP47

SB_DQ_2

SB_BS_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

SB_RAS#