FORMAT : QP10 KCE / DEPT.

OF ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

ME VLSI DESIGN

SUBJECT : VLSI DESIGN LABORATORY I

SEMESTER : I

LAB MANUAL (VL 5111)

(Version : 1)

PREPARED BY
Mr. P.RAJA PIRIAN, AP/ECE

ADC 1 KCE / ECE / II YR / ADC

FORMAT : QP10 KCE / DEPT. OF ECE
VL5111 VLSI DESIGN LABORATORY I LTPC
0042
LIST OF EXPERIMENTS

LIST OF EXPERIMENTS:
1. Understanding Synthesis principles. Back annotation.
2. Test vector generation and timing analysis of sequential and combinational logic design
realized using HDL languages.
3. FPGA real time programming and I/O interfacing.
4. Interfacing with Memory modules in FPGA Boards.
5. Verification of design functionality implemented in FPGA by capturing the signal in DSO.
6. Real time application development.
7. Design Entry Using VHDL or Verilog examples for Digital circuit descriptions using HDL
languages sequential, concurrent statements and structural description.

TOTAL: 60 PERIODS

SIGNATURE OF STAFF INCHARGE HOD/ECE

Mr.P.Raja Pirian

ADC 2 KCE / ECE / II YR / ADC

FORMAT : QP10 KCE / DEPT. OF ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ME VLSI DESIGN

COURSE PLAN

Sub. Code : VL5111 Branch / Year / Sem : M.E VLSI DESIGN / I/I
Sub.Name : VLSI DESIGN LAB I Batch : 2017-2019
Staff Name : Mr.P.Raja Pirian Academic Year : 2017-18 (ODD)

COURSE OBJECTIVE

The laboratory based study for the entire program is clubbed under three categories.
1. Study the FPGA based design methodology;
2. Learn the simulation of analog building blocks,and analog and digital CAD design flow.
3. Study how the FPGAs are important platform used throughout the industry both in
their own right in building complete systems.
4. Learn from high level design entry in the form VHDL/Verilog codes, the students will
be carrying out complete hardware level FPGA validation of important digital
algorithms.
5. Perform exercises on the SPICE simulation of the basic CMOS analog building blocks
will be carried out.

LEARNING OUTCOME
Upon the completion of this lab, students should be able to

Analyse the digital system specification,

Should be able to map it onto FPGA platform and carry out a series of validations design
starting from design entry to hardware testing.
Simulate the time domain and frequency domain simulations of simple analog building
blocks.
Analyse the pole zero behaviors of feedback based circuits and compute the input/output
impedances.

PRE-REQUISITE

Knowledge about Basic VLSI Design.

EQUIPMENTS / COMPONENTS / SOFTWARE REQUIRMENT

Hardware:
XILINX 9.2
SPICE
FPGA
DSO

ADC 3 KCE / ECE / II YR / ADC

FORMAT : QP10 KCE / DEPT. OF ECE

No. of Cumulative
Planned
Ex.No Title of the Experiment Hrs. No. of
Date
required periods

CYCLE : I

1. Understanding Synthesis principles. Back

annotation. 10

Test vector generation and timing analysis of

2. sequential and combinational logic design realized
10
using HDL languages.

3. FPGA real time programming and I/O interfacing.

5

4. Interfacing with Memory modules in FPGA Boards.

5

CYCLE : II

Verification of design functionality implemented in

5. FPGA by capturing the signal in DSO. 10

Real time application development.

6. 10

1Design Entry Using VHDL or Verilog examples for

Digital circuit descriptions using HDL languages
7. 10
sequential, concurrent statements and structural
description.

CONTENT BEYOND SYLLABUS

Design a two channel real-time data acquisition system.

Prepared by Verified By
(Mr.P.Raja Pirian) HOD/ECE

Approved by
PRINCIPAL

ADC 4 KCE / ECE / II YR / ADC

FORMAT : QP10 KCE / DEPT. OF ECE

GUIDELINES FOR AWARD OF INTERNALS

Observation : 05
Completion of Mark to be
experiment awarded
On Scheduled 10
date
Within 3 days 8
after
scheduled
date
Avg. of observation marks obtained to be converted to 5 at the end.

Record : 05
Submission of Mark to be
record awarded
notebook /
sheets
On 10
Subsequent
lab slot
Within 3 days 8
after
scheduled
date
Avg. of record marks obtained to be converted to 5 at the end.

Attendance : 05

Model : 05

------
Total 20 Marks
------

ADC 5 KCE / ECE / II YR / ADC