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Abstract: Input ripple analysis of ve-phase pulse width modulated (PWM) inverters is presented. The analytical
expressions for the rms value of the input current and voltage ripples as a function of the PWM reference signal
are derived. Similar to three-phase PWM inverters, the input current ripple does not depend on the employed
reference signal, so the ripple cannot be minimised by changing the shape of reference signal. On the other
hand, different from three-phase PWM inverters, it is shown that a pure sinusoidal signal is the optimum
reference signal that produces a minimum input voltage ripple in ve-phase PWM inverters. Input voltage
ripples under several modulation techniques are compared. Experimental results are included to verify the
proposed analysis method.
716 IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 716 723
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-pel.2009.0129
www.ietdl.org
5
i d = kIl cos w (6)
2 2
Figure 1 Five-phase PWM inverter The sinusoidal output line currents can be written as
where bar and tilde indicate the average and ripple where u vt, and v 2pf is the angular frequency of
components, respectively. The average current through the the fundamental output current.
dc capacitor is zero. The ripple components on the LHS
and RHS of (2) must be the same and, therefore, the ripple
component of the capacitor current is The relationship among the dc side current, switching
states and the ac side currents of the inverter can be written as
i C = i L i d (3)
IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 716 723 717
doi: 10.1049/iet-pel.2009.0129 & The Institution of Engineering and Technology 2010
www.ietdl.org
written as
vr1 = k sin u + s0
2p
vr2 = k sin u + s0
5
r 4p
v3 = k sin u + s0
5 (9)
6p
vr4 = k sin u + s0
5
8p
vr5 = k sin u + s0
5
0 for t0 t t1 4T2
= vr5 vr2 (13)
i1 for t1 t t2 Ts
i1 + i5 for t2 t t3 4T3
= vr2 vr4 (14)
Ts
i3 i4 for t3 t t4
4T4
i3 for t4 t t5 = vr4 vr3 (15)
Ts
id = 0 for t5 t t7 (10)
4T5
= 1 + vr5 (16)
i3 for t7 t t8
Ts
i3 i4 for t8 t t9
where the amplitude of the carrier signal has been assumed as
i1 + i5 for t9 t t10
unity.
i1 for t10 t t11
The mean square value of the inverter input current over
0 for t11 t t12 one carrier period can be calculated as
t0 +Ts
From Fig. 3, the relationships between time intervals T0 , T1 , 1
T2 , T3 , T4 and T5 to Ts can be dened as Id2 = id2 dt (17)
Ts t0
4T0
= 1 vr1 (11) Substituting (10) into (17) and performing the integration,
Ts the following is obtained
4T1 2T1 2T 2T 2T
= vr1 vr5 (12) Id2 = i12 + (i1 + i5 )2 2 + (i3 + i4 ) 3 + i32 4 (18)
Ts Ts Ts Ts Ts
718 IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 716 723
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-pel.2009.0129
www.ietdl.org
Substituting (7), (9) and (12) (15) into (18), the following This result is the same as the input current ripple of
expression is obtained (see (19)) three-phase PWM inverters. This expression is useful
to determine the ripple current rating of the dc lter
The average value of this current over the interval A of Fig. 2 capacitor.
can be calculated as
p/2 4 Input voltage ripple
2 5
Id,av = Id2 du The ripple component of dc lter capacitor voltage can be
p 3p/10
determined by solving (5) using (6) and (10). The
5 4 2p p 2 p 2p waveform of dc lter capacitor voltage ripple over one
= kIl2 cos2 w sin + sin + 2sin sin
p 3 5 5 3 5 5 carrier period is Fig. 3d. The expression of this waveform
(20) over one-half carrier period is (see (22))
Because of symmetrical operation, the results over the other The expression over another half carrier period is the mirror
36 degrees periods are the same. Finally, the rms value of of (22). The mean square value of the capacitor voltage ripple
the ripple component of the dc side current can be over one switching period can be calculated as integration of
calculated as (see (21)) its square value over the period t0 to t12 , that is
t0 +Ts
Equation (21) shows that the rms value of the input 2 1
V d = v2d dt (23)
current ripple is not inuenced by s0 or by the shape of Ts t0
reference signal, and thus it cannot be minimised by
changing the shape of reference signal. As the input Substituting (22) into (23) and performing the integration
current ripple is not inuenced by the switching frequency, results in the following expression (see (24))
this expression also shows that the input current ripple
cannot be reduced by increasing the switching frequency. where fs is the switching or carrier frequency.
1 p
p
p
1 2p
sin 3u + 2w + sin u + sin u + + sin u + 2w + sin u + 2w
2 5 5 5 2 5
Id2 = kIl2
(19)
1 3p 1 2p
+ sin (u 2w) cos u + 2w + sin 3u + 2w
2 10 2 5
2 k 2 20 2p p 25p 10 p 2p
I d = Id,av
2
i d = Il cos w sin + sin k + 2 sin sin (21)
p 3 5 5 8 3 5 5
i d (t t0 ) for t0 t t1
T0i d (i1 i d )(t t1 ) for t1 t t2
1 T0i d (i1 i d )T1 (i1 + i5 i d )(t t2 ) for t2 t t3
vd = (22)
Cd
T5i d (i3 + i d )T4 + (i3 + i4 + i d )(t t4 ) for t3 t t4
T5i d (i3 + i d )(t t5 ) for t4 t t5
i d (t t6 ) for t5 t t6
25 cos2 w 3k2
2
+ 3so + 1
4 4
2 2
2p p 2p
2 k Il 15k cos w 8 cos sin( w 3u ) 4 sin cos( w 3u ) + 2 sin w 3 u
V d = + 5 5 5 (24)
2 2
96Cd fs 8 p
+4 sin w u 2 sin
2p p
cos(w u) + 5 sin (w u) + 6 cos sin(w u)
5 5 5
p p
2p 3p p p
+32k sin sin u 2w sin 3
4 sin 2
3 + sin 3
1 + 6 cos
10 2 5 10 5 5
IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 716 723 719
doi: 10.1049/iet-pel.2009.0129 & The Institution of Engineering and Technology 2010
www.ietdl.org
2
dV d
=0 (25)
ds0
so = 0 (26)
1/2
kIl 25 599 25 2 19
Vd,av = k+ k cos2 w + k
Cd fs 384 1690p 512 14268p
(28) Figure 5 Input voltage ripples under 0.8 load power-factor
For comparison purpose, the expressions of inverter input among the results, however, are so small and can be
voltage ripples under several modulation techniques are recognised only when the modulation indexes are high.
shown in Table 1. These expressions are plotted in Figs. 4 Under zero load power-factor, the input voltage ripples are
and 5 for unity and 0.8 load power-factors, respectively. the same for all PWM techniques. It should be noted that
This gure shows that the inverter input voltage ripple the maximum modulation index under sinusoidal PWM is
under a pure sinusoidal signal is the lowest. The differences unity. Under other modulation techniques, however, the
720 IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 716 723
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-pel.2009.0129
www.ietdl.org
5 Experimental results
In order to verify the proposed analysis method, a small
experimental system using ve-phase MOSFET inverter
with a star connected load was constructed. The experiments
were done with static R 2 L loads, thus e 0. Under static
load, we can easily change the modulation index without
changing the fundamental output frequency. The values of
load resistance and inductance per phase are L 5.8 mH
and R 5.5 V, respectively. In this experiment, the dc
voltage source, Ed 50 Vdc is obtained by using a three- Figure 7 Output current waveforms under sinusoidal and
phase diode bridge rectier as shown in Fig. 6. The dc discontinuous signals when the modulation index is 0.8
voltage is maintained at a constant value by adjusting the
a Sinusoidal
variable ac (VARIAC) transformer. To reduce the effect of b Discontinuous
the rectier output harmonics on the investigated inverter, a Ver: 2.5 A/div Hor: 2.5 ms/div
large smoothing capacitor (10 000 mF) is directly connected
in parallel to the rectier output. A large inductance
(78 mH) is connected in series to reduce the output current
ripple of rectier. By using this method, it is expected that
the inverter input voltage ripple is mainly because of the
inverter input current ripple. In this experiment, a small
capacitor of 220 mF is directly connected in parallel to the
input of inverter. The inverter was operated at a low
switching frequency (2000 Hz) to reduce the dead-time
effects in the experimental results. The output frequency of
the inverter was set to 50 Hz.
IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 716 723 721
doi: 10.1049/iet-pel.2009.0129 & The Institution of Engineering and Technology 2010
www.ietdl.org
signal. This gure shows clearly the agreement between the modes. Once again, a good agreement between the
calculated and experimental results. As the results are the calculated and experimental results can be appreciated from
same, inverter input current ripples under other modulation these gures.
techniques are not shown in this paper.
6 Conclusion
Figs. 10 13 show the calculated and experimental results
In this paper, analysis of input ripples of ve-phase PWM
of inverter input voltage ripples under sinusoidal, sinusoidal
inverters has been presented and veried by experimental
plus fth harmonic, discontinuous and space vector
results. Different to three-phase PWM inverters, it has
reference signals. During discontinuous PWM operation,
been shown that the optimum reference signal that results
the switching frequency was increased by 20% so that the
in minimum input voltage ripple of ve-phase PWM
average switching frequency is equal to other operating
inverter is pure sinusoidal signal. Similar to three-phase
PWM inverters, the rms value of the input current ripple
of ve-phase PWM inverters is not inuenced by the shape
of reference signal and switching frequency. Inverter input
voltage ripples under several PWM techniques have been
compared and shows the superiority of sinusoidal PWM
technique. The results are very useful to determine the
required dc lter electrolytic capacitor. Extension of this
work to other phase numbers is under investigation.
Figure 10 Experimental and calculated results of the input
voltage ripple as a function of modulation index under 7 References
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IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 716 723 723
doi: 10.1049/iet-pel.2009.0129 & The Institution of Engineering and Technology 2010