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Cadence OrCAD FPGA System Planner

FPGA-PCB co-design with automated device-rules-accurate pin assignment

The Cadence OrCAD FPGA System Planner addresses the challenges that engineers encounter
when designing large-pin-count FPGAs on the PCB boardwhich includes creating the initial pin
assignment, integrating with the schematic, and ensuring that the device is routable on the board.
By replacing manual, error-prone processes with automatic pin assignment synthesis, this unique
placement-aware solution eliminates unnecessary physical design iterations while shortening the
time required to create optimum pin assignment.

Designing large-pin-count
Integrating todays FPGAswith Differential
their many different types of assign- User IO
ment rules and user-configurable
pinson PCBs is time consuming and
extends design cycles. Often the pin
assignment for these FPGAs is done Configurable
manually at a pin-by-pin level in an
environment that is unaware of the
placement of critical PCB components
that are connected to FPGAs. Without Clock
understanding the impact to PCB Power

routing, FPGA-based design projects

are forced to choose between two
poor options: live with suboptimal pin
assignment, which can increase the
number of layers on a PCB design;
or deal with several unnecessary
iterations at the tail end of the design Figure 1: Color-coded map of the I/Os of a multi-bank FPGA with different types of
cycle. Even with several iterations, configurable pins
this manual and error-prone approach
can result in unnecessary PCB design ing the trade-offs would mean assignment. FPGA pin assignment
re-spins. that users would have to do two proj- is synthesized automatically based
With the added time required to ects in parallel with no design reuse of on user-specified, interface-based
generate pin assignments for FPGAs any kind between the two. connectivity (design intent), as well
using manual approaches, users are as FPGA pin assignment rules (FPGA-
The Cadence OrCAD FPGA System
unable to do trade-offs between the rules), and actual placement of FPGAs
Planner provides a complete, scal-
different FPGA devices available and on PCB (relative placement). With
able solution for FPGA-PCB co-design
the cost of devices used in an FPGA automatic pin assignment synthe-
that allows users to create an opti-
sub-system. This is because perform- sis, users avoid manual error-prone
mum correct-by-construction pin
processes while shortening the time to
Cadence OrCAD FPGA System Planner

create initial pin assignment that accounts

for FPGA placement on the PCB (place-
ment-aware pin assignment synthesis).
This unique placement-aware pin assign-
ment approach eliminates unnecessary
physical design iterations that are inherent
in manual approaches.

The OrCAD FPGA System Planner is inte-

grated with both OrCAD Capture and
OrCAD PCB Editor. It reads and creates
Capture schematics and symbols. In
addition, a floorplan view uses existing
footprint libraries from OrCAD PCB Editor.
Should placement change during layout,
pin optimization using FPGA System
Planner can be accessed directly from
OrCAD PCB Editor.

Benefits Figure 2: Placement/Floorplan view of the OrCAD FPGA System Planner provides users relative
placement of critical components for optimum pin assignment synthesis
Scalable, cost-effective FPGA-PCB
co-design solution from OrCAD to all, there is no online rules-checking to thereby extending the time it takes to
Allegro GXL ensure that the right pin types are being integrate todays complex, large-pin-
used for the signals that are assigned to count FPGAs on a PCB.
Shortens time for optimum initial pin the FPGA pins. As a result, users have
assignment, accelerating PCB design Specifying Design Intent
to make several iterations between the
schedules spreadsheet-based tools and the tools The OrCAD FPGA System Planner comes
from FPGA vendors. Often this adds an with an FPGA device library to help with
Accelerates integration of FPGAs
increased number of iterations between selection of devices to be placed. It uses
with OrCAD PCB design creation
the PCB layout designer who cannot OrCAD PCB Editor footprints for the
route the signals from FPGA pins on floorplan view and allows users to quickly
Eliminates unnecessary, frustrating available layers and the FPGA designer create relative placement of the FPGA
design iterations during the PCB layout who has to accept paper-based or verbal system components.
process pin-assignment suggestions from the
PCB layout designer. Once a change is The OrCAD FPGA System Planner allows
Eliminates unnecessary physical users to specify connectivity between
made to the pin assignment by the FPGA
prototype iterations due to FPGA pin components within the FPGA sub-system
designer, the pin assignment change
assignment errors at a higher level through interface defini-
has to be made in the schematic design
Reduces PCB layer count through by the hardware designer. Such itera- tions. Users can create interfaces such as
placement aware pin assignment and tions add several days if not weeks to the DDR2, DDR3, and PCI Express, and use
optimization design cycle and possibly a great deal of these to specify connectivity between an
frustration for the team members. Since FPGA and a memory DIMM module or
Features this is a manual process, mistakes that are between two FPGAs. The OrCAD FPGA
not detected can also cause expensive System Planner understands differential
OrCAD FPGA System Planner physical prototype iterations. signals, and power signals, as well as
Technology clock signals.
While it may help to automate the
An FPGA system is defined as a subset of synchronization of changes made to the FPGA Device Rules
the PCB design that includes one or more pin assignment by the FPGA designer, The OrCAD FPGA System Planner comes
FPGA and non-FPGA components that are hardware designer, or PCB layout with a library of device-accurate FPGA
connected to FPGAs. designer, it doesnt reduce the root cause models that incorporate pin assignment
Traditional approaches to pin assignment of these iterations. Pin assignment that rules and electrical rules specified by
are typically manual and often based is not guided by all three aspectsFPGA FPGA device vendors. These FPGA models
on a spreadsheet. Tools such as these resource availability, FPGA vendor pin are used by the synthesis engine to ensure
require users to do pin assignment with- assignment rules, and routability of FPGA that the vendor-defined electrical usage
out taking into consideration the place- pins on a PCBrequires many iterations rules of the FPGAs are strictly adhered to.
ment of other components and routability at the tail end of the design process, These rules dictate such things as clock
of the interfaces and signals. Above

www.cadence.com 2
Cadence OrCAD FPGA System Planner

for FPGA in OrCAD Capture symbol

libraries. If the user desires, the FPGA
System Planner products can create split
FPGA OrCAD OrCAD OrCAD symbols for FPGA based on the connec-
Vendor FPGA Capture/CIS PCB
Tools System Planner Designer tivity or one split symbol per bank.

Integration with FPGA

Vendor Tools
In addition to integration with OrCAD
OrCAD PCB design tools, the OrCAD FPGA
Part Library System Planner communicates seamlessly
with FPGA design tools. It generates
Symbols, Footprints
and reads supported FPGA vendors pin
Figure 3: The OrCAD FPGA System Planner uses symbols and footprints from existing libraries assignment constraint files. This capabil-
ity enables the FPGA designer to evaluate
pin assignments against the functional
and clock region selection, bank alloca- Pin assignment algorithms are optimized needs of the FPGA. Any changes made
tion, SSO budgeting, buffer driver utili- to assign interface signals to a group of by the FPGA designer to account for
zation, I/O standard voltage reference pins, thereby minimizing net crossovers these requirements can be imported into
levels,etc. During synthesis, the OrCAD and improving routability on the PCB. to the OrCAD FPGA System Planner so
FPGA System Planner automatically that the complete set of pin assignments
Tight Integration with Cadence
checks hundreds of combinations of these remain in sync.
rules to ensure that the FPGA pins are Design Creation
optimally and accurately utilized. The OrCAD FPGA System Planner gener-
ates OrCAD Capture, schematics for the
Placement Aware Pin
FPGA sub-system. It uses existing symbols
Assignment Synthesis
The OrCAD FPGA System Planner provides
users a way to create an FPGA system
placement view using OrCAD PCB foot-
prints. Users specify connectivity between
components in the placement view and
the FPGA at a high level using interfaces
such as DDRx, PCI Express, SATA, Front
Side Bus, etc. that connect FPGAs and
other components in the design, shorten-
ing the time to specify design intent for
the FPGA system.

Once the connectivity of the FPGA to

other components in the sub-system is
defined, the OrCAD FPGA System Planner
then synthesizes the pin assignment
based on the users design intent, avail-
able FPGA resources, component place-
ment around the FPGA, and the FPGA
vendors pin assignment rules.

The OrCAD FPGA System Planner has a

built-in DRC engine that incorporates the
rules provided by FPGA vendors for pin
assignment, reference voltages, and termi-
nations. This rules-based engine prevents
PCB physical prototype iterations as the
FPGAs are always correctly connected.

Figure 4: OrCAD FPGA System Planner optimization

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Cadence OrCAD FPGA System Planner

Pre-Route Pin Assignment Scalability Sales, Technical Support, and

The OrCAD and Allegro FPGA System
The initial pin assignmentthat accounts Planner technology is available in the The OrCAD product line is owned by
for placement and routability of the FPGA following product offerings: Cadence Design Systems, Inc., and
on a PCBgoes a long way toward supported by a worldwide network of
Allegro FPGA System Planner GXL
reducing costly design iterations between Cadence Channel Partners (VARs). For
for synthesizing and optimizing pin
FPGA designer, PCB layout designer, and sales, technical support, or training,
assignment of more than four FPGAs at
hardware designer. Once the PCB layout contact your local Cadence Channel
a time. Suitable for companies that use
designer starts to plan the routing of inter- Partner. For a complete list of authorized
FPGAs to prototype ASICs
faces and signals on FPGA, it is possible Cadence Channel Partners, visit
to further refine the FPGA pin assignment Allegro FPGA System Planner XLfor www.cadence.com/Alliances/channel_
based on route intent, layer constraints, concurrent pin assignment, synthesis, partner.
and fanout chosen for the FPGA. The and post-placement optimization of up
OrCAD FPGA System Planner offers users a to four FPGAs at a time
way to optimize FPGA pin assignment after
Allegro FPGA System Planner Lfor pin
placement and during routing of the inter-
assignment synthesis and post-placement
faces and signals on an FPGA.
optimization of a single FPGA

OrCAD FPGA System Plannerfor

optimum initial pin assignment
synthesis of a single FPGA.

Allegro 2 FPGA Allegro 4 FPGA

OrCAD FPGA System Allegro ASIC
System Planner System Planner
Planner Prototyping Option
Option Option
1 FPGA or Multiple 2 FPGAs or Multiple 4 FPGAs or Multiple
Concurrent device
FPGAs totaling 1,000 FPGAs totaling 2,000 FPGAs totaling 4,000 Unlimited FPGAs
max pins max pins max pins
Yes Yes Yes Yes
Reuse symbols and
Yes Yes Yes Yes
Allegro Design Entry CIS Allegro Design Entry CIS Allegro Design Entry CIS
Symbols and
OrCAD Capture / Allegro Design Entry / Allegro Design Entry / Allegro Design Entry
schematic generation
No Yes Yes Yes
Schematic power
No Yes Yes Yes

Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com

2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, and OrCAD are registered trademarks of Cadence
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