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Most circuit electronics assumes a fairly casual attitude about power dissipation. For levels of power
which are small we obligingly ignore their impact on the circuit and concentrate instead on the transfer
characteristics. We assume that devices are ideal and they are able to handle levels of
any challenge, mV to kV and A to kA.

But when confronted by significant levels of power, our philosophy must change. High levels of
power are accompanied by a certain degree of risk, and we must adopt caution if we are to ensure that
the power is directed to the application rather than to the circuit. We also have to be aware of the fact
that large power levels feature large voltage current swings and so smallsignal analysis is inadequate.
Our mission, should we choose to accept it, is to investigate the ways in which we design a circuit
topology equal to conditions of large power and large amplitudes, and accommodate physical
limitations of the devices and the ability of the environment to absorb our excesses.

Power electronics is a focus on

(1) linear power amplifiers: for signal drive of a large output transducer
(2) power converters: to achieve levels of I,V required from available I,V .

In these and other cases where large levels of power must be handled by electronic devices, several
concepts become of considerable importance. They are:

(1) Efficiency
(2) Thermal derating
(3) Distortion

The efficiency is the fraction of the supplied power that is actually delivered to the load. An efficiency
close to 100% is desired but not very likely. Chances are that some power will be wasted along its
route to the load and be dissipated within the circuit. Power dissipated within the circuit manifests
itself in the form of heat that degrades the circuit capabilities and operational lifetime. In order to keep
the transistors out of trouble, their powerhandling capability must always be derated by the ability of
the cooling system to cool the fevered brow of the junctions, and these constraints must be factored
into the design. Since transistors are not necessarily linear over their conduction region, and since the
circuit itself has compliance limits, the signal is subject to considerable distortion unless we employ
symmetric design techniques.

Elementary heat transfer principles and common sense tell us that temperature difference is
proportional to the heat, as is generated by dissipated power. Most of the dissipated power is
released at the vicinity of the junction of a transistor or diode, or within the channel if the component
is a FET. Assuming that the junction temperature is of magnitude TJ and the ambient temperature is
TA, then we can make the identification

T J T A = JA PD (20.11)

where PD is the power dissipated in the device. The constant of proportionality JA is defined as the
thermal resistance between junction and the ambient medium. Thermal resistance is given in terms of
C/W. The lower the thermal resistance, the more heat can be conducted away from the junction.
Cooler junctions are happier junctions, and live longer.

Transistors have a maximum rated junction temperature, TJ(max), on the order of 150 to 300 oC.
TJ(max) should not be exceeded, or device meltdown, distortion of the spacetime continuum, or
something else equally undesirable will take place. One of the design concerns of power electronics
circuits is that TJ be kept less than TJ(max).

Figure 20.11 Thermal resistances.

Temperatures can be kept within reasonable limits if the transistor has a good thermal conduction path
from the junction to the ambient medium. Since the ambient environment is usually air, the exterior
part of the thermal path will usually be in the form of a heatsink radiator, usually little more than a
metal plate with fins. As indicated by figure 20.11, the thermal resistance JA between the junction
and the ambient medium consists of a series path of heatconducting layers or elements, each of which
have their own thermal resistance, so that

JA = JC + CS + SA

where JC , CS, and SA are the thermal resistances of the various layers between the junction and the
ambient, consisting of junctiontocase, the casetosink, and the sinktoambient, layers (or
elements) respectively.

Junctiontocase thermal resistance, JC , is defined by the power rating of the transistor. Transistor
power ratings, PD(max), are usually defined in terms of a standard reference case temperature TC =
25oC accomplished by emplacing the transistor on a massive heat sink. If we then know the maximum
rated temperature of the junction, TJ(max), the junctiontocase thermal resistance is

(TJ (max) 25)

JC = (20.12)
PD (rated )

The junctiontocase resistance, JC is typically on the order of 1 to 20 oC/W, depending on the power
rating of the transistor.

Thermal resistance CS is the contact resistance between the case of the device and the heat sink,
usually kept small by a (modest) use of heat sink grease, typically on the order of 0.2 to 0.5 oC/W.
The sinktoambient or heat sink resistance, SA , depends on construction and size of the heat sink. A
heat sink with radiative fins should have a reasonably low thermal resistance per length. Doubling of
the size of the heat sink will approximately halve its thermal resistance.

Consider the following example:

EXAMPLE 20.11: A pair of 25W transistors, used for a classA amplifier, dissipate a total of 12W.
Assuming TJ(max) = 175 oC and heat sink grease such that CS = 0.4 oC/W,

(a) what thermal resistance of heat sink for each transistor is needed to keep the junction
temperature below TJ = 125 oC and
(b) what size heatsink is needed, assuming that a 2 cm length of heatsink has SA = 16 oC/W?

SOLUTION: Assuming that the transistors are referenced to TC =25 oC, which is default, then the
internal thermal resistance

JC = (175 25) 25 = 6 oC/W

Each transistor must dissipate 6W, and therefore, in order to meet junction requirement T J 125 oC

JA = (125 25) 6 = 16.67 oC/W

Therefore (a) a heatsink of thermal resistance

SA = JA ( JC + JS ) = 16.67 6.4 = 10.27 oC/W

is required for each transistor. (b) Using the heat sink stock cited, which is 16 oC/W for each 2 cm,
each heat sink must be of length

L= 2cm = 3.12cm
For extra margin, we might cut off a 4 cm piece of stock for each transistor.

In other cases, we might define a limit on the power that can be dissipated by a given transistor or
device, in terms of PD < PD(max). Note that, since PD = I D V D for which ID is the current through
the device and VD is the voltage across the device, this represents hyperbola in the I vs V domain.

The power hyperbolas for BJT and FET devices are represented by Figure 20.12. Electrical
properties of a device are represented by IC vs VCE for the BJT and by ID vs VDS for the FET. For
circuit design, these graphics also are used in conjunction with load lines, etc. If we overlay a power
limit on the device characteristics it is then represented by the hyperbolic (constraint)
PD (max, derated ) = I D V D . PD(max, derated) includes the derating effect of the heatsink.
Figure 20.12 Maximum power hyperbolae for power transistors

It should be noted that it is usually not possible to expect a 25W transistor to dissipate 25W, because
of thermal derating.


In most applications involving signal amplification the final stage of the circuit is an output driver to a
large transducer, usually electromechanical or radiative. One of the more typical transducers is the
audio speaker, which is effectively an electromagnetic air piston. Load transducers like the audio
speaker come in various sizes ranging from little pipsqueaks to giants capable of defoliating trees
along the roadway. So in like manner power circuits must be constructed in various sizes matched to
the demands of the output transducer. For simplicity we generalize the load transducer as (load)
resistance RL.

It should be noted that the power that an amplifier delivers to an output transducer is drawn directly
from the power supply rails. The amplifier circuit acts to channel power to the output load, and is
little more than a pair of power transistors deployed between load and the power rails. Most of the
time we assume that the control signal is sinusoidal and that the transistors will therefore pass a
sinusoid current to the load. In some topologies we let the transistors act as switches with an output
that is a railtorail squarewave.

Assuming sinusoidal signals the power delivered to a transducer of resistance RL by the drive
transistors cannot be any more than 2V S2 R L , (per one of the topologies on the menu) where rails of
opposite polarity VS are assumed. Therefore the first step in analyzing a linear power amplifier is to
determine the power supply requirements needed to support the output transducer at the desired load

For purposes of matching application to circuit form, power amplifiers are usually identified by a
classification system. Classification is defined by the duty cycle of the drive transistors. A circuit for
which the drive transistors are always conducting (100% duty cycle) is called a class A amplifier.
Class A amplifiers provide a nearly undistorted output signal, but do so at miserable efficiency. Most
casual circuits are of type class A, since they operate about an operating point level. For the class A
amplifier the efficiency and the level of power dissipated in the transistors are at their worst when the
amplitude of the input signal is zero, since then all of the power will then be dissipated in the circuit.

We improve the efficiency dramatically if we use a circuit topology which is non-conducting when the
signal level is zero. We can accomplish this easily if we employ a pair of complementary transistors to
drive the load. Ideally, each of the drive transistors conducts only for half of the cycle and are off the
other half cycle. This type circuit is called a class-B amplifier. Each of the drive transistors in a class B
amplifer have duty cycle of 50%. When the signal is at zero amplitude no device is conducting and no
power is consumed

If the circuit is modified so that the drive transistors have a duty cycle slightly more than 50%, then
the circuit is called class AB. Class AB circuits have an efficiency slightly less than the class B
amplifer. Class AB amplifiers resolve a zerocrossing distortion problem that afflicts class B

Class C amplifiers operation uses drive transistors biased below cutoff, which conduct only for a small
fraction of a cycle and therefore have a duty cycle less than 50%. They are used only for tuned
circuits. Typical applications are as the modulation circuit for an RF receiver or transmitter. They
have an efficiency that is usually greater than class B, and can approach 100% for a highly resonant

A type amplifier that does not quite fit the dutycycle classification pattern is the class D amplifier.
Class D amplifiers are switching amplifiers, and their efficiency can approach 100%. The class D
amplifier must include a modulator at the frontend to translate the waveform into highfrequency
pulse widths and a filter network at the back end to remove the highfrequency pulses from the
amplified output. Usually the filter network is of a simple, lossless RL or RC form.

Table 20.21 summarizes the different types of common power amplifers and the way in which the
signal is handled.
Table 20.21. Power amplifier classes


Power transistors are the big strong slow members of the transistor kingdom. They usually live in their
own separate packages with a tab or plate designed to have contact with a heatsink. They are not
formed in the same way as their integratedcircuit cousins. Therefore power transistors are not
usually included in an integrated circuit, since most IC fabrication technologies are dedicated to high
density, mildtemperature applications. This exclusive situation is not a law, and developments of
new technologies have allowed us to embed large transistors in integrated circuits, with some
Whether in separate or integrated form, we should think of power transistors and power diodes as the
heavy lifters of the semiconductor kingdom, designed to handle great power levels, and packaged to
dissipate great levels of heat.

In order for us to design for these capabilities to best performance and operating lifetime, it is in order
for us to take a critical look at their operating and performance characteristics.

In the first place, we expect power transistors to have relatively large crosssectional area. Naturally,
if all they had to do was handle larger currents, we would form a large transistor of the usual type. But
higher levels of power also imply that we need to control higher voltage levels without a breakdown
disaster. So, in general, power transistors are constructed with a different semiconductor layering,
usually including one or more lightlydoped regions which have the ability to accommodate higher
voltage levels without suffering breakdown. Power transistors and diodes are thus characterized by:

(a) greater crosssectional area

(b) a relatively thick, lightlydoped junction layer, for reduced level of Efield

There are other, more subtle things that we may do as well, such as heavy doping with gold or copper
to speedup the recombination processes. For MOS devices, thicker oxide layers are necessary to
protect the device from overvoltages which causes the threshold, VTH, to be higher.

These modifications will compromise some of the other characteristics that we covet, such as low
resistance and fast response. Lightly doped regions result in significant intrinsic resistance along the
current path. Greater areas imply larger capacitances. Larger current levels imply higher levels of
injected and stored charge. These effects are all bad for switching speed and internal power

Power transistors are therefore characterized by the following performance limitations:

(c) higher VTH , lower F

(d) slower switching speeds
(e) greater VCE(sat), VDS (sat)
(f) greater intrinsic resistance in the conducting path

We will take a short look at each of the most common types of power transistors and components, and
assess them as candidates for our power electronics circuits.

pin junctions
The p-i-n junction is a pn junction with a layer in the middle that is intrinsic or nearlyintrinsic
semiconductor. To the semiconductor world it probably looks like an ice-cream sandwich, with the
(vanilla) core being nearly clean of impurities. Actually, the core is always slightly doped, so we
usually call the junction a p--n if the intrinsic layer is slightly ptype, or a p--n junction if the
intrinsic layer is slightly ntype. Figure 20.31 shows a representative pin junction and Efields
Figure 20.31 The pin junction: (a) Crosssection (b) Potentials and Efields in reversebias (c)
Injected carrier levels in forward bias

The figure shows that, in reverse-bias, the Efield is relatively low, since the intrinsic layer can be
made of thickness much larger than the usual micron thickness depletion depth of the typical pn
junction. The Efield is approximately

E VJ / W (20.31)

where VJ is the junction reversebias and W is the thickness of the intrinsic layer. Junction breakdown
typically takes place at 20 to 40 V/m, so a reversebias of 100 V across an intrinsic layer thickness of
10m still has a comfortable safety margin..

However in forward bias, we are faced with an intrinsic region across the main current path that has a
miserable conductivity, = qN i for which Ni is the (low) doping density and is carrier mobility.
For crosssectional area Ai and layer thickness Wi, this leaves the device with series resistance

Ri = (20.32)
qN i Ai

EXAMPLE 20.31: What is the intrinsic resistance for a silicon pn junction of crosssectional
area Ai = 1.0 cm2, doping of the intrinsic layer Ni = 2 x 1014 #/cm3 and layer thickness Wi = 30 m.
Assume n = 1250 cm2/Vs.

Wi 30 10 4
SOLUTION: Ri = = = 75m
qN i Ai (1.6 10 19 ) 1250 (2 10 14 ) 1.0

As resistances go, this doesnt sound too bad, until you realize that this junction may be conducting
100 A over a 50% duty cycle, in which case it must dissipate
PD = 0.5 100 2 75m = 375W

At this level of internal power dissipation this had better be one tough junction.


In forward bias we also have something of a speed problem, due to the fact that the intrinsic region is
flooded with charge carriers. And as a result of the low doping levels, we will not necessarily have a
fast recombination time constant since recombination time depends on the density of impurity sites.
Gold or copper is usually added to enhance recombination, but this type of doping causes other
complications. When bias voltage is swung from forward to reverse, current will continue to flow with
time constant determined (approximately) by the diffusion capacitance per area,

C D = J D R (20.33)

where JD is the forward current density and R is the recombination time constant, which is usually on
the order of s. Adding to our grief, we also will usually have largearea ( and consequently large
capacitance) junctions.

Power BJTs

The power BJT is little more than a conventional BJT with a collector junction of the form of a p-i-n
junction rather than the usual simple pn junction. We see this represented by figure 20.32.

Sometimes we can get away with a normal BJT construction and simply have a mildlyreduced
doping level for the collector material. As long as we dont have any reverse junction biases in excess
of 100V, this will probably work OK, but we do have to make the device with a larger than normal
basewidth (layer thickness) to avoid punchthrough problems. Transistors of this species will
usually have a F somewhat less than the traditional BJT, on the order of 25 to 50.

Higherpower BJT transistors, which must be able to withstand reverse junction biases in excess of
200 V, are typically of the form represented by figure 20.32. This figure shows a BJT with an n+-p-
n-n+ construction. The lightlydoped region is usually called the driftregion since the carriers must
drift across this region before they get collected at the n+ collector. Transistors of this type are
lucky to have forward current gain F as good as 25. They are also characterized by a large quasi
saturation region of operation, corresponding to partial forwardbias conditions in the lightlydoped
drift region, as represented by figure 20.32(c)
Figure 20.32 The highvoltage power BJT: (a) crosssections (b) forwardbias characteristics (c)
excess carrier distributions for a power BJT in quasisaturation.

Highpower BJT transistors, as represented by figure 20.32(b), are therefore also characterized by a
fairly poor VCE(sat) because of this quasisaturation region.

This effect is represented by figure 20.32(a) and (b). If we analyze details of the semiconductor
junction workfunctions and injected carrier levels, we will find, after all the mathematical and
semiconductor dialogue is completed, that the power BJT structure will have a VCE(qsat) at the
boundary of the quasisaturation region given by

VCE ( qsat ) = V BE 2VT ln + Vi (20.34)
where Vi = Ri x IC is the resistive drop in the intrinsic region, VBE is the voltage across the forward
biased baseemitter junction, and the term 2VT ln(Ni/ni) is a collective term due to the work function
potential between base and intrinsic regions and the charge carriers injected into the intrinsic region
from the base. The term ni = intrinsic carrier density for a pure semiconductor, which = 1.5 x 1010
#/cm3 for the most likely semiconductor, silicon, at nominal ambient temperature 300 K. VT is the
thermal voltage, and is approximately .026V at 300K

EXAMPLE 20.32: Assume that a 400V power BJT has a p-i-n collector junction of the same
dimensions and doping as example 20.31. For a VBE of 0.69 V and current density J = 50A/cm find
the value of VCE at the boundary of quasisaturation.

SOLUTION: This is a good-sized transistor so dont expect a small VCE. At the boundary of quasi
2VT ln(Ni/ni) = 2 x .026 x ln[(2 x 1014)/(1.5 x 1010)] = .0494V
so that the complete VCE across the BJT at the onset of the quasisaturation condition will be

VCE(qsat) = VBE 0.494+Ri x (J x Ai) = 0.69 0.494 + (0.075 x 50) = 3.95V

At saturation conditions, for which base current is large, the p-i-n junction becomes forwardbiased
and carriers will flood the intrinsic region and make Ri approximately 0.0. In this case

VCE(sat) = 0.69 = 0.195V

In practice, VCE(sat) is seldom achieved or a highpower transistor, because the forward current gain
F of such a transistor is so low it becomes difficult to provide the necessary base current. Even in the
active region, F would probably be no better than about 20 for a transistor of this power capability.


The Power MOSFET

The power MOSFET is a vertical structure as represented by figure 20.33. A power nMOSFET is
represented. It is a doublediffused structure (sometimes called DMOS). In this case the DMOS is
formed by a pwell diffused into a lightlydoped substrate layer, followed an n+ source diffused into
the pwell. Although this structure doesnt look much like the classical MOSFET, the figure shows
that the region of the pdiffusion at the surface will be subject to an Efield across the oxide at that
point. Gate-inspired field inversion will be achieved in the p-material and conduction will occur. The
drain terminal is at the bottom. High voltages at the drain node are isolated from the gate and the
implants at the upper surface by the thick lightlydoped (n) substrate layer.

Figure 20.33 The power MOSFET:

(a) crosssections (b) ID vs VGS characteristics (c) ID vs VDS output characteristics.
In reverse bias the intrinsic layer provides the usual highfield protection by means of the p-i-n
junctions. In forward bias the intrinsic layer has a finite series resistance that will give undesirable loss
effects not unlike those for the power diode and the power BJT. The MOSFET gatechannel voltage
must be able to withstand channel bias levels on the order of 10 to 20 V, and therefore requires oxide
thickness on the order of 100 to 200 nm. The pwell must be at a healthy doping level to avoid a
problem called punchthrough. These effects combined imply that VTH will have a magnitude on the
order of 4 to 5V. Because the depletion region extends into the channel during forward operation, the
value of L is small. This shortchannel results in very strong field along the channel which drives the
transistor into a velocitysaturation mode of VDS when in the forward active mode. The result is a
linear transfer characteristic for ID vs VGS, as represented by figure 20.33(b), and is of the form

I D = WC OX vC (VGS VTH ) (20.35)

In velocity saturation vC is on the order of 107 cm/s for electrons in silicon. Cox is the oxide
capacitance/area and W is the channel width, which we make as large as possible by artful designs of
the surface geometry. One of the favorite surface designs is a hexagonal arrangement, and such
structures are often called HEXFETS.

Resistance rDS is the channel resistance for a MOSFET at low VDS , given by

rDS = C OX (VGS VTH ) (20.36)

and represents the lower boundary of the velocitysaturated drain levels, as shown by figure 20.3-3(c).
It also represents the drain resistance of the MOSFET channel when it is operating in its most
conductive state for which power dissipation in the device may be identified.


A class-A power amplifier can be of any topology for which the transistor is biased into a quiescent
point for amplification and control, but is most accurately represented by the voltage-follower circuit
as represented by figure 20.41(a). Since the transistor is biased in the active regime the drive
transistor will be in a mode with a 100% duty cycle.. In the voltage follower mode the drive transistor
stays in the active mode throughout the drive cycle. The output should therefore be almost undistorted,
depending only on the linearity of the drive transistor(s). The follower circuit has a fairly linear
response over a wide output range, as indicated by figure 20.41(b). Therefore the class-A circuit
manifests relatively little distortion of the output. The current source, which defines fixed current IS,
also requires a power transistor and heat sink.
Figure 20.41 Class A circuit using BJT drivers.

The follower circuit does not necessarily have to make use of bipolar power rails but is elected in this
case for comparisons to other classes of power amplifiers for which bipolar power rails are necessary.
The voltage and current requirements of the circuit are defined in terms of the maximum power
delivered to load RL. For a power amplifier with BJT drivers, and assuming that the output driver of
the current source is a single BJT, then the amplitude of the output waveform will be bounded by the
voltage rails V S offset by VCE(sat). In the usual caveat of electronics, VCE(sat) is taken as negligible
for all but lower voltage (Vo < 5V) levels. For highpower, highvoltage BJTs, VCE(qsat) limit may be
as much as 5V, but this higher limit may also be ignored for drive voltage levels on the order Vo >
100V, typical for highpower transistors.

We therefore identify the approximate current level needed to drive the load RL as

IS = (20.42)

This current is also the quiescent current corresponding to input signal of zero amplitude. Since IS is a
fixed level then the power supply will continuously deliver power at the level

2V S2
PS = 2V S I S = (20.43)

For sinusoidal signals of output amplitude VL averaged power delivered to load RL will be

1 1 V L2 sin 2 1 V L2
PL = PL =
T 0
V (t ) dt =
d =
2 RL

PL is a maximum (= PL(max)) when VL = VS. The maximum efficiency that the class A
circuit can provide is then

PL (max) V S2 2 R L
(max) = = = 0.25 (or 25%)
PS 2V S2 R L

Worst case power dissipation PD(worst) will be at quiescent, for which

2V S2
PD ( worst ) = = 4 PL (max) (20.4-6)

and is the design criterion that must be used in assessment of the cooling system (heat sinks, etc).

The action of the transistors for the classA amplifier is represented by figure 20.42.

Figure 20.42 (a) Class-A circuit consisting of BJT driver and simple current mirror. (b) Waveforms
for the class-A amplifier.

If the transistors employ individual cooling systems each would need to be designed to accommodate

In the design process, specifications typically include values for RL and PL(max). The design task is
primarily a matter of identifying power supply requirement VS and the ratings and heat sinks for the
drive and current source transistors.

Consider the following example:

EXAMPLE 20.41: It has been determined that mosquitos appreciate certain audio frequencies, for
which they will fall out of the sky, lie on their backs, and wave their little legs in appreciation.
The 16.4 kHz piezoelectric oscillator in the Donohoe mosquitosuppressor operates at
maximum effectiveness when PL = 4W. The equivalent load resistance of this transducer is RL =
10 and is to be driven by a class-A amplifier of the form of figure 20.42. Q3 is onefifth the size of
Q2. Determine

(a) power supply requirements VS , IS and PS of the voltage rails and

(b) load efficiency for this circuit.

SOLUTION: Maximum power to the load results when VL = VS. So for PL = PL (max) = 4W and
using equation (20.4-4)
V S = 2 PL (max)R L = 2 4 10 = 8.94V

and the current source must provide

V S 8.94
IS = = = 0.89A
RL 10

Therefore the biasing resistance R1 of the current source must be

8.94 0.7
R1 = = 46

The positive supply rail must provide PS1 = IS x VS = 2 x PL = 8W. The negative supply rail must
provide current of approximately (IS + IS/5) = 1.07 A so that PS2 = (-1.07) x (-8.94) = 9.6W.

The efficiency of this circuit is then

PL 4
= = = 0.227 (or 22.7%)
PS 1 + PS 2 8 + 9.6

A caveat of this circuit is that the input and output signals for this amplifier are offset from one
another by approximately 0.7 V. For optimum performance and minimum distortion the offset should
be accommodated by a 0.7V levelshift in the signal produced by the stage preceding the power



As cited by example 20-4-1 one of the more common problems that is encountered with largesignal,
amplification is distortion of the waveform. The analysis of distortion caused by caveats of the circuit
are considerably simplified by use of (SPICE) circuit simulation software.

Distortion is manifested by harmonics, for which the signal VL(t) to the load is

V L (t ) = V1 cos(1t + 1 ) + V 2 cos( 2 t + 2 ) + V 3 cos( 3 t + 3 ) + + V N cos( N t + N )

where 1 is the input signal frequency and 2 = 21, 3 = 31, .. etc, accompanied by phase shifts,
1, 2, 3, . The rms output is then

Vrms = (V1
+ V22 + V32 + + VN2 2

Distortion content is defined by the THD (total harmonic distortion) of VL(t) and is defined as

Vrms (total )
(V 1
+ V22 + V32 + + V N2 )
Vrms ( 1 ) V1
The circuit simulation software can readily decompose VL(t) by invoking a Fourierseries analysis, for
which a Fourier-series table and THD are generated under the output file, as represented by example
and figure 20.5.

EXAMPLE 20.51. Class B amplifier crossover distortion and compliance limit distortion using

Figure 20.5-1: Since Va > Vs, the output swing is clipped.

In assessing distortion the THD is the defining figure of merit even though we may single out some of
the harmonic overtones. Clipping due to the compliance limits always results in a strong third
harmonic content. Third harmonic distortion is also called cubic distortion.

Figure 20.5-2. THD = 4.45% . The third harmonic content to the distortion = 2.09%

In most respects the class-A amplifier is not a good choice as a power amplifier since its efficiency is
poor and since it consumes power when in the quiescent state. Indeed if you value your battery power
supply you will avoid the class-A amplifier for anything but amplitude gain. Most linear power
amplifiers are designed using the class B form, or its cousin, class AB for which the conduction path
between voltage rails is off or nearly so when there is no input signal.

In order to achieve such a caveat, class-B makes use of complementary drive transistors with each at a
50% duty cycle. A representative class-B power topology with an npn and pnp (complementary) BJT
pair is shown by figure 20.61. Class-B circuits are also identified as pushpull amplifiers because of
the directions of current flow through the load RL and the transistor drivers. In this respect a similarity
does exists between the class-B action and that of the class-A circuit topology, except that zero signal
input signal corresponds to no conduction path between the voltage rails.

Figure 20.61 Class B circuit using BJT output drivers.

There is a little problem with this configuration. The transistors will suffer a dead zone for
V I 0.6V for which the output will then have a zerocrossing distortion. This crossover distortion is
particularly serious at low signal amplitudes. This type of effect is represented by figure 20.62.

Figure 20.62 Crossover distortion for class-B

The crossover problem is aggravated even further when MOSFETs are used, particularly since power
MOSFETs have a relatively high VTH. For this reason, MOSFETs are usually used in the CS driver
configuration, as indicated by Figure 20.63(b).

Figure 20.63 Idealized schemes for correction of the crossover distortion problem by use of diode
connected transistors at the input.

In our usual flair for approximation crossover effects are treated as being negligible and the class-B
operation results in straightforward recipes. For ideal class-B the transistors are conducting on a 50%
duty cycle and the timeaveraged current that is drawn from either rail of the power supply will be

1 V L sin V
I AV =
d = L

assuming sinusoidal signals. Therefore the power drawn from the voltage rails is

PS = I AV 2VS = (20.62)

For VL(t) = VL sin t, the power to the load is the same as derived via equation (20.4-4)

1 V L2
PL =
2 RL

For which the efficiency = PL/PS will be

V L2 2 R L VL
= = (20.63)
2V LV S R L 4 V S
At VL = VS for which the maximum power is delivered to the load the ideal class B circuit form has
(theoretical maximum) efficiency /4, or 78.5%. The higher efficiency means that less power is
dissipated in the transistor junction and therefore the transistors will have a happier and longer
lifespan. The relationship

PD = PS PL = PS PS = (1 ) PS (20.64)

should be part of the picture for the power amplifier topologies.

The more definitive relationship for power PD dissipated in the transistors makes use of equations
(20.6-2) and (20.4-4), for which

2V LV S 1 V L2
PD = PS PL = (20.65)
R L 2 RL

Equation (20.6-5) is quadratic in VL with maximum (= worst-case) dissipation at PD V L = 0 .

Taking this derivative give the result that the maximum occurs when

2V S
VL = (20.66)

Substituting (20.66) into (20.65) the maximum power (= worst-case) dissipated in the circuit will be

2 V S2 4 1 V S2 4
PD ( worst ) = = = PL (max) (20.67)
2 RL 2 2 RL 2

or approximately 0.406 PL(max). PL(max) is the power delivered to load RL when VL =VL(max) = VS.
If equation (20.66) is applied to equation (20.6-3) the result is an efficiency of 50%, i.e. PD = PL .

In design of the cooling system the worst-case heat dissipation must be considered and so PD as given
by equation (20.6-7) is the benchmark.

Table 20.61 summarizes design considerations of the class A and class B amplifiers. Usually power
amplifier design is effected in terms of PL(max) for which the minimum power supply rail voltage is
then given by

VS (min) = 2 R L PL (max) (20.6-8)

Actual rail voltages will be higher than VS(min) and therefore the PD(worst) benchmark is significant
to the circuit definition and well as that of the heat sink.


The class AB amplifier relies on the fact that it is approximately the same as the class B with some
accommodation the dead space crossover problem. Essentially, class AB makes a mild increase of
duty cycle for each transistor so that there is no dead-space and the transistors will conduct at low-
level for the cross-over. To good approximation most of the analysis associated with class B will
apply to class AB. With cross-over eliminated distortion is minimized due to the symmetry. The
principles behind class AB operation are represented by figure 20.71.

Figure 20.71: Principles of operation of the class-AB amplifier.

The efficiency is reduced since a relatively small quiescent current IQ flows through the transistors
when VI is 0. Rather than use two current sources as indicated by figure 20.71, it is sufficient and
necessary to use a single current source and make use of the previous stage act a current sink as
represented by figure 20.7-2.

Figure 20.72: Class AB diode bias of transistor pair.

The current source Ibias must provide sufficient base drive to meet the requirement of the output
transistors, i.e.,
I (max)
I bias > I B (max) = L (20.7-1)
( F + 1)
In order for effective class-AB operation, offset bias VBB must keep both transistor junctions in
conduction at VI = 0. This condition is achieved by stacking as many diode bias junctions as there are
transistor junctions. It is also essential and necessary that the bias diodes be thermally linked to the
drive transistors QN and QP or the circuit will suffer a destructive situation called thermal runaway.
Thermal runaway occurs when a fixed bias is emplaced across a junction. At fixed junction bias the
current though the junction will approximately double for every 10 oC rise in temperature. The
increase in junction current then causes an increase in temperature, and this produces an increase in
current, which then causes an increase in temperature. The effect is exponential and catastrophic.

When the bias VBB is set by thermallylinked junctions as represented by figure 20.72, it will
automatically compensate, decreasing by V = -2 mV/oC as the biasing diodes heat up.

Offset bias VBB is on the order of 2 x 0.6 V. More explicitly, VBB = VBEN + VBEP for the transistor pair.
Taking inverses of the junction characteristics for which I = IS exp(VBE/VT ) for each transistors and
assuming I = IS exp(0.5VBE/VT ) at quiescent, then retention of a relatively fixed VBB implies that

V BB = VT ln(I EN I S ) + VT ln(I EP I S ) = 2 VT ln I Q I S )
For these relationships Is = reverse saturation current of the output transistors, assumed to be matched,
and. VT = kT /q = thermal voltage.

By inverting the logarithmic condition

I Q2 = I EN I EP (20.72)

The currents IEN and IEP for the ouput transistors will be inverses of one another.

This scheme will work fine in most respects, but suffers a problem that conflicts sizing and the
forward current gain of the transistors. The problem is illustrated by example 20.71.

EXAMPLE 20.71: A class AB amplifier configuration with biasing diodes 1/5 that of the drive
transistor is used to drive an 8W, 4 load. Matched complementary BJTs for which F = 50
are employed.

Determine Ibias and IQ under the requirement that current through the bias diodes ID is not allowed to
vary by more than a factor of 10. For simplicity (and to avoid iteration) assume that IB(min) is


VL(max) = VS(min) is given by load requirements as 2 R L PL (max) = 2 (4 8) = 8.0V

I L (max) 8.0 4
and from equation (20.7-1) I B (max) = = = 39.2mA
( F + 1) 50 + 1
Since I Bias = I D + I B , then I D (max) + I B (min) = I D (min) + I B (max) , for which the conditional
requirement is that ID(max) = 10 x ID(min) and IB(min) = 0
For which the results are that ID(min)= 4.36mA and ID(max) = Ibias = 43.6mA

ID(max) is also the current that flow through the diodes at quiescent conditions. Combining these two
conditions. Since the diodes are 1/5 the size of the drive transistors and have the same junction bias

I Q = 5 I D (max) = 218mA

This level of IQ corresponds to quiescent power consumption PQ = 2VS x IQ = 3.48W = an additional

power dissipation contribution to the cooling (heat sink) system.


The example reflects an extra expenditure of power PQ for correction of crossover distortion. If the
power budget can accommodate this extra overhead then the simple diode bias is an adequate design
option. The quiescent current IQ is much less if the bias diodes are more nearly the same size as the
output drivers but at the expense of a more bulky circuit.

The key factor, however, is as much the forward current gain F as the relative sizing of bias diodes
and output transistors. If we should use drive transistors with large F the current levels in the bias
network are considerably smaller. Since quiescent current IQ is a multiple of these current levels, then
it would consistently be smaller. For example, had we used transistors for which F = 200 in example
20.71 the quiescent current IQ would have been 55mA, and the power dissipated at quiescent
conditions would have been PQ = 0.884 W.

Unfortunately power BJTs, particularly the highvoltage types, do not have large F . More commonly
have forward current gain on the order of 25 to 50. Forward current gain is even less respectable for
the PNP power BJT, since carrier mobility is about a factor of 2.5 lower for holes than it is for

However, have no cause to fear. Because of these caveats, power transistors usually are devised as a
Darlington pair as reflected by figure 20.73. The Darlington pair has current gain

F = 1 2 + (1 + 2 )

which is on the order of F = 400 to 10,000, even for

transistors for which individual F is poor. These are usually
incorporated in a single package and are sometimes called
superbeta transistors. Their improved current gain is mildly
offset by the fact that they also have an equivalent VCE(sat) =
VBE1 + VCE2(sat) which will be on the order of 1.0V. And
highpower, highvoltage transistors may have VCE(sat) = 5V.
The Darlington pair will also require an input offset biasing of
VBE1 + VBE2 which we expect to be on the order of 1.2 V.
Figure 20.73: The Darlington pair

When we use the class AB Darlington configuration, and even when we dont, it is often convenient to
use another input offset biasing scheme, the VBE multiplier circuit. This circuit is a resistance defined
ladder made up of R1, R2 and transistor Q5 of form represented by figure 20.74. This circuit uses the
junction VBE5 of the bias transistor Q5 as the junction
voltage reference coupled to resistances R1 and R2 to get
necessary VBB bias. Inasmuch as Q5 is the reference
junction for the input bias it is necessary that it be in good
thermal contact with the output transistors in order to
assure temperature compensation. A class AB Darlington
with VBE multiplier is shown by figure 20.75a.

Figure 20.74: The VBE multiplier

A modification of the class AB Darlington configuration for which the relatively weak PNP output
driver is replaced is is shown by figure 20.75b This topology is known either as the compound pnp
or as the Sziklai configuration. Since the power transistor Q2 is of type npn, the compoundpnp driver
will usually have a better forward current gain than the PNP Darlington.

It does represent a slight compromise in symmetry, since the output resistance is higher for the
compoundpnp than for the pnp Darlington. This option may make induce a mild asymmetry in VL(t)
depending on load RL.

Figure 20.75: Class AB Darlington configurations.

Analysis of the VBE multiplier is not much different from the process used for example 20.71,
except that we now need to identify the appropriate value of VBB in order to find the correct values for
R1 and R2. If we have the vanilla form of class-AB output drivers, like that shown by figure 20.75a,
then V BB 4 x 0.6V.
EXAMPLE 20.72: The L59U cricket laser robot requires a linear amplifier for beam steering. At
maximum (sinusoidal) modulation signal, a load power of PL = 32W must be applied to the focus coil,
which has an equivalent load resistance of RL = 4. Design a class-AB Darlington using transistors
for which both npn and pnp super-beta transistors have F = 2000. Choose IR = 0.5mA and require IC5
to vary by no more than a factor of 5. Assume reference transistor junction Q5 to be1/50 the area of
power transistor Q1.

(a) VS(min) and IB(max)
(b) quiescent current IQ and quiescent power PQ
(c) Ibias, R1 and R2
(d) Total worst-case power dissipation budget PD if VS = VS(min)
(e) Total worst-case power dissipation budget PD if VS = 20V


(a) Power supply rails must be greater than VS = VL(max) = 2 R L PL (max) = (2 4 32) = 16.0V
V L (max) 16
for which the maximum load current is I L (max) = = = 4.0A
RL 4
Since the Darlington pair has equivalent F = 2000 then IB(max) is approximately

I L (max)
4 .0
I B (max) = = 2.0mA
F 2000
(b) Assume IB(min) is negligible 0 . Since I bias = I R + I B + I C 5 then

I C 5 (max) + I B (min) = I C 5 (min) + I B (max)

or 5I C 5 (min) = I C 5 (min) + 2.0mA , which gives IC5(min) = 0.5mA and therefore

IC5(max) = 2.5mA.

Since Q5 = (1/50) the size of Q1, then I Q I E1 = 50 x IC5(max) = 125mA.

(c) At quiescent V BE 5 0.6V default, so that R1 = VBE5/IR = 0.6V/0.5mA= 1.2k. Since the VBE
multiplier must bias an equivalent of four junctions, three more junction 0.6V default levels must fall
across R2 and therefore

R2 = (3 x 0.6V)/IR = 1.8V/0.5mA = 3.6k.

Ibias = IR + IB(min) + IC5(max) =0.5mA + 0 + 2.5mA = 3.0mA

1 V S2 (min)
(d) For voltage rails VS = VS(min) = 16.0V, PD ( worst , class B ) = 0.406
2 RL
= 0.406 x (32W) = 13.0W and PQ = IQ x (2VS) = 125mA x (2 x 16) = 4.0W

so the total worst-case power dissipation = 13.0W + 4.0W = 17.0W

1 V S2
(e) For voltage rails VS = 20.0V, PD ( worst , class B) = 0.406
2 RL
= 0.406 x (0.5 x 20 /4) = 20.3W and PQ = IQ x (2VS) = 125mA x (2 x 20) = 5.0W

so the total worst-case power dissipation = 20.3W + 5.0W = 25.3W

A larger cooling system penalty must be paid when VS > VS(min) even though no more power is
applied to the load than when VS = VS(min)


Instantaneous Power Dissipation

In the overview so far, it has been have taken for granted that the thermal time constants are much
longer than the time constants of the signal. The assessment of power PD in the circuit has been able
to be defined in terms of time averages. However, nothing prohibits the levels of current and voltage
to have an instantaneous level of power consumption that exceeds the PD(max) of the power
dissipation hyperbolas. The time averaging process may be a bad call if the signal time constant is
very low. For example, a linear power amplifier intended to drive a servo motor control may have
operation stop for long periods of time at point A, and PD is then defined in terms of the long instant.
In such an application, the transistor dissipation must be analyzed in terms of a worstcase
instantaneous power dissipation scenario. For a linear load line as represented by load resistance RL,
the maximum instantaneous dissipation occurs at the center of the load line, for which

VS V 1 V2
PD = S = S = 0.5 PL
2RL 2 2 2RL

where sinusoidal signals are still assumed, just at a longer time constant.

Figure 20.8-1: Load-line dissipation hyperbola overlay onto class-B output characteristics
Power gain

It is essential and is expected that the power amplifier stage have a high intrinsic power gain. In most
cases this is reflected by the caveat of high current gain since the output drivers are of the form of
voltagefollower circuits. But the corollary is that the power amplifier must have a high input
impedance. This requirement is no problem for the FET amplifiers, assuming that we dont go too
high in frequency. But it presents a little greater problem to BJT drivers, since the input impedance
depends on F. The superbeta transistors are therefore almost a caveat to this requirement, since
that the input impedance of the emitterfollower circuit is approximately

Rin = ( F + 1)R L

For very high power, highvoltage transistors, even the Darlington configuration has some limitations,
particularly for the PNP output transistors for which F may be as low as 5 to 10. In this respect the
compound pnp option may be a caveat of high-power design.

Inductive loads

Many of the high-power applications include inductive loads, particularly those for which an
electromechanical device is being controlled. Inductive loads are prone to the creation of large voltage
transients at the output node of the transistor when output current changes too rapidly through the
inductance. This induced emf is the caveat of the energy stored in an inductance, for which it reflects a
transfer of energy into a voltage mode in response current change, as reflected by

V =L (20.8-1)

This induced emf can be catastrophic to the output transistors of the power amplifier since it can
exceed the inverse breakdown voltage of the power transistor. For this reason power amplifiers with
inductive loads should be bridged by clamping diodes or snubbers as represented by figure 20.02.
During normal operation these diodes are reversebiased. During overvoltages they forward bias and
allow the induced emf to harmlessly discharge into the power rails.

Figure 20.82: Use of protective snubber diodes with an inductive load.

Shortcircuit protection and foldover current limiting

An accidental shortcircuit to ground or an overload at the output, both of which are not uncommon,
represents a potentially fatal situation. Assuming that the power supply has a comfortable margin of
current that it can provide, the power amplifier, in its ignorance, will let its drive transistors handle the
situation. The drive transistors will comply for only a short interval before the junction exceeds
temperature limits and suffers irreversible effects. To prevent these problems, shortcircuit protection
is usually necessary. The circuit is shown by figure 20.83.

Figure 20.83: Shortcircuit protection for class AB amplifier.

Transistors Q3 and Q4 are normally off at moderate current load levels. They begin to conduct when
there is sufficient current through R3 and R4 to produce and threshold of approximately 0.5V, sufficient
to steal base current from the power transistors Q1 and Q2 and thereby limiting current to the load. If
the output is shorted the load current limit is effectively

I L (max) = 0.5 R3 (20.82)

Since the voltage drop 0.5V is relatively small compared to the output levels, R3 and R4 will have
negligible effect.. Because Q3 is not across the power rails, the power it must dissipate is negligible
and is a basedrive shunt device, not some type of sacrificial transistor.

A somewhat similar problem is the possibility of the output load being positioned so that an accidental
short or low impedance path to one of the voltage rails can occur. This situation will have
consequences that are as catastrophic as a short to ground if not more so. We can see from the plot
given by figure 20.84(a) showing the dissipation hyperbolas (for the class AB) that one of the drive
transistors would be well into an overload should VO be shorted to +VS or VS. Setting lower current
shortcircuit limits is not a good solution since this would seriously restrict the maximum drive
capability of the amplifier.
Figure 20.84: Foldover protection circuit for class AB amplifier.

Figure 20.84(b) shows a modification of the circuit called a foldover circuit which gives an effective
shortcircuit protection through the extra resistance ladder formed by R1 and R2. When we use this

V B 3 = (V L + I L R3 )
R1 + R 2

and since the voltage at VE3 = VL, then the voltage across the baseemitter junction of Q3 is then

R2 (R2 R3 I L R1V L )
V BE 3 = V B 3 V E 3 = (V L + I L R3 ) VL =
R1 + R2 R1 + R2

If we assume a cutin value VBE3 = 0.5V then the limit relationship is

R1 R + R2
IL = V L + 0.5 1 (20.8-3)
R 2 R3 R 2 R3

Note that this is a currentvoltage line which varies with respect to VO, and can be used to limit the
current without crossing over the PD hyperbola, as represented by figure 20.84(c). Therefore we have
gained a wider range of overload protection with minimum compromise of the loadhandling
capability of the circuit.


At a higher level of abstraction and simplicity we may take advantage of technology and packaging.
As a consequence of integrated circuit evolutions many applications can be covered by an integrated
circuit form which we identify as the power opamp. The majority of power opamps are constructed
with moderate-voltage power transistors and therefore do not encounter the difficulties of integrating
highvoltage processing technology with lowervoltage technologies. Power opamps will invariably
incorporate such features as shortcircuit protection, current boosters, etc, integrated into the IC
package. They are optimized for class AB operation with minimum quiescent power budget and in
this respect closely mimics ideal class-B operation. Therefore for designs with power opamps the
worst-case maximum power dissipated in the opamp, PD(max), is identical to that determined in
section 20-6, i.e
4 1 V S2
PD (max, worst ) = 2 (20.9-1a)
2 RL

And if the power supply rails can be chosen such that VS = VL(max) this can be simplified to

PD (max, worst ) = 0.406 PL (max) (20.9-1b)

The basic usage issues are then the identification of load and cooling system relationships for which it
is necessary to define

(1) VS(min)
(2) thermally derated limit PD(max)

For loads requiring greater levels of power than a single opamp will deliver, power opamps may be
coupled in parallel. Figure 20.91 shows two common options. Even though not represented by the
figure, it is also necessary that a small equalization resistance, on the order of 0.1 be placed
between each follower output node and the load to handle unequal offsets in the paralleled opamps.
Figure 20.91: Circuits configurations using stacked power opamps.

Consider the following example:

EXAMPLE 20.91: PL = 120W (approx 1/5 Hp) of power is needed to drive the Halpin
electromagnetic grip used in the forearm of the markII cyborg. Equivalent load resistance of the
artificial muscle is RL = 4. A power stage with good linearity and frequency response is needed in
order to achieve the necessary dexterity. Power opamps having ratings of 100W and thermal limits
TJmax = 200oC are available. Heatsink grease such that contact resistance CS = 0.2oC/W is available.

Analyze for possible designs by

(a) determining minimum VS necessary and minimum heatsink resistance, assuming we desire to keep
junction temperature TJ < 180 oC to prolong device lifetime. Also find the case temperature TC.

(b) If the system can only accommodate a heat sink of SA = 5 oC/W, what is the minimum number of
paralled opamps needed and their case temperature?

SOLUTION: (a) If we drive the 120 W load at maximum efficiency, then

VS = VL(max) = 2 R L PL (max) = ( 2 4 120) = 31.0V

Assuming that the transistor is rated for 100W at case temperature 25oC then

JC = (200 25) 100 = 1.75 oC/W

The worst-case estimate of the power that the cooling system will need to dissipate is

PD (max, worst ) = 0.406 PL (max) = 48.6W

for which we need a heat sink of thermal resistance

SA = (TJ T A ) / PD ( JC + CS ) = (180 25) / 48.6 (1.75 + 0.2 ) = 1.24oC/W

A heatsink with such low thermal resistance would have to be very large.

Case temperature is given by TC = T J JC PD = 180 48.6 x 1.75 = 94.9oC

(b) Assuming heatsink resistance SA = 5 oC/W the maximum power that can be dissipated per opamp
for the constraint TJ = 180oC, is

PD = (T J T A ) ( JC + CS + SA ) = (180 25)/(1.75+0.2+5) = 22.3W

for which we will need N OA = 48.6 22.3 = 2.18 opamps

Since opamps doe not exist as fractional quantities, we will need three opamps NOA = 3.

The case temperature will then be

TC = T A + ( CS + SA ) JC PD = 25 +(0.2 + 5) x (48.3/3) = 109 oC

and the junction temperature will be: TJ = 137.6 oC


Power opamps provide us other configurations for delivering power to a load. One of these is the
power bridge configuration which makes use of a unitygain follower and a unitygain inverter to
deliver a linear output of amplitude VL = 2VS across a bridged load, for which the load power is then

1 (2V S )
2V 2
PL = = S (20-9.2)

Figure 20.92: The power bridge: (a) the opamp pair (b) output transistor operation.
Figure 20.92(b) shows how the output transistors for the two opamps alternately conduct in the
bridge configuration. The peak current IL(max) is defined by the power rails and is approximately

I L = 2V S R L (20.93)

The average current over one half-cycle is the same as that for class-B, i.e.

1 VL
I L (avg , half ) = (20.94a)

and conduction takes place for both half-cycles so that

1 VL
I L (avg ) = 2 (20.94b)

The power drawn from the supply is then

PS = 2V S I S (avg ) = (20.95)

The maximum power dissipated in the circuit is then defined by

4V S V L 1 V L2
PD = PS PL = (20.96)
R L 2 RL

Taking the condition PD V L = 0 gives that PD(max) occurs when

VL =
(2VS ) (20.97)

Substituting (20.9-7) into (20.9-6) the maximum power (= worst-case) dissipated in the circuit will be

2 (2V S ) 4 1 (2V S )
2 2
PD ( worst ) = 2 = 2 = PL (max) (20.98)
RL 2 RL 2

which is entirely consistent with ideal class-B analysis. The bridge circuit consists of two opamps so
each opamp will dissipate half of this value. The advantage to the bridge configuration has some
advantage in that it only needs half as much supply voltage VS as does the voltage follower circuit.
The caveat is that the load RL must be floating load. A ground connection will short out one of the
opamps and if it is not protected against this sort of catastrophe then a spectacular demise should be
Reconsider example 20.91(a), but using a power bridge.
EXAMPLE 20.92: For PL = 120 W, we find, using equation (20.92)

VS = R L PL (max) / 2 = 2 R L PL (max) = 15.5V

The maximum power that we expect to be dissipated in each opamp is then

PD (ea) = PL (max, worst ) = 24.3W

Each opamp has qJC = 1.75oC/W. Therefore a heatsink of thermal resistance

SA = (180 25) / 48.6 (1.75 + 0.2) = 4.42oC/W

is needed. The size of the heatsink is not quite as prohibitive as it was for example 20.9-1(a).

Case temperature is given by TC = TJ JC PD = 180 24.3 x 1.75 = 137.4oC

Note that the results are somewhat similar to example 20.9.1(b) which should not be unexpected since
we are making use of two opamps (via the power bridge).

We are also allowed to stack opamps in the power bridge configuration with the caveat that an even
number of opamps is necessary.


The class B amplifier could have an efficiency approaching 100% if it is used to handle a full-voltage
squarewave rather than a sinusoidal wave. This greater efficiency results because large currents occur
when the transistor is put into its most conductive state, for which the device voltage VD (VDS or VCE )
= small. Alternatively, when device voltages VD is large the transistor is in its least conductive state,
and therefore device current ID = small. Since PD = ID x VD then it is always small since either the
current is nearly zero or the voltage is nearly zero during is operational cycle.

The class-D amplifier is a modification of this principle for which the signal is chopped into rail-rail
squarewave pulses as a highfrequency switchmode operation that alternately connects load RL to
the positive and negative supplies. The class-D amplifier therefore has an efficiency approaching
100%. But in order for it to function as a signal amplifier its input must be of PWM (pulsewidth
modulated) form as shown. The output is derived by means of a time-averaged form with appropriate
filter time constants. This requires that the class-D amplifier include a pulsewidth modulion front end
and a filter circuit on the back-end. Switching frequency must be considerably higher than the signal
frequency in order to avoid aggravations such as distortion, aliasing, and others associated with pulse
modulation schemes. Usually, a CMOS type of output circuit is used, as represented by figure 20.10-
1(a) in order to achieve the switching speed necessary.
Figure 20.101: Class-D amplifier using complementary CMOS output drivers

The PWM system uses a highspeed comparator to generate the switchlevel input, comparing signal
input VI(t) to a sawtooth with amplitude VP < VI(max) at switching frequency fS . The output of the
comparator VA must be of amplitude at least twice that needed to switch tdrive transistors M1 and M2
on and off.

A representative modulator design is shown by figure 20.102. The modulator itself is switched by a
pulse train of frequency fS, for which switch Q1 has the effect of discharging capacitance C, which is
otherwise linearly charged by and current source Io. The amplitude VP of the sawtooth is

1 IO
VP = (20.101)
fS C

Figure 20.102a: PWM circuit for frontend of class-D amplifier.

Figure 20.102b: Use of sawtooth action to accomplish PWM

Assuming that a CMOS output drive is used similar to that of figure 20.101, the CMOS input node
will be driven by an input PWM pulse VI = 0.5V A V M which corresponds to VGS = V M for each
transistor, since zero signal (corresponding to VI = VA/2 input) corresponds to gate voltage for each
transistor being at the voltage rails. The MOSFETs act as switched resistances for which the on state
then has an approximate conductance

G DS = 2 K (V M VTH ) (20.102)

The output voltage amplitude to the load is then defined by the voltage divider for which

V L = V S (20.103a)
R L + 1 / G DS

and the power delivered to the load, time-averaged for a sinusoidal input signal, will then be

1 V L2 1 R L G DS V S2
PL = = (20.103b)
2 R L 2 1 + R L G DS RL

The current drawn by the transistor and the load is of the form

IL = = V S (20.104a)
R L 1 + G DS R L

so that the power drawn from the supply will be

(R L + 1 / G DS ) =
PS = I L2 (20.104b)
2 (1 + G DS R L )

Therefore the efficiency of the amplifier isI

= = (20.105)
PS (1 + G DS R L )

This equation, along with 20.102, also defines the lower limit of the input amplitude VM. Example
20.101 illustrates this analysis.

EXAMPLE 20.101: A class-D amplifier of the form shown by figure 20.101 uses a complementary
matched pair of MOSFETs for which K = 0.4A/V2 and |VTH| = 3.2 V. It is used to provide a maximum
of 60W of power to a RL = 5 load. Determine power supply requirements VS and IS, and minimum
input drive level VM for operation at 80% efficiency.

SOLUTION: The maximum output voltage level Vo = VS is given by

VS = 2 R L PL (max) = (2 5 60) = 24.5V

for which IS = VS /RL = 4.9A

For an efficiency of 80%, we have, from equation (20.105)

G DS R L = = =4
1 0 .2

for which GDS = 4/RL = 0.8

From equation (20.102) we get

VM = VTH + G DS 2 K = 3.2 + 0.8 /(2 0.4) = 4.2V



Converters are the most common form of power electronics. A converter takes one form of electrical
power and converts it into another. AC-AC converters are the simplest. AC-AC conversion is
accomplished by inductive coupling for which the time-varying nature of AC power is well suited.
AC-AC converters also are the means to tap power from the power grid which accomplishes its task at
50Hz or 60Hz frequencies over high-voltage transmission lines.

A cousin to this type of converter is the ACtoDC converter. Conversion from the bipolar nature of
AC to the unipolar form of DC is accomplished through the artifact of diode rectifier circuits under
such categories as halfwave, fullwave, three-phase, etc.
Considerably more conversion versatility and efficiency can be accomplished by means of transistors
as high-speed switches. These are categorized as switching power supplies and are most commonly
employed as DC-DC converters. They also find use as DC-AC converters, also identified as

Since the DC-DC switching technique is simple and straightforward and offers advantages in
adaptability, size, and efficiency, it is rapidly taking the lead over the older linear technologies.

The generic form of the switching converter is DC to DC, for which a unipolar, steady-state source
level ( I1 ,V1 ) is converted to a unipolar steady-state load requirement (I2 ,V2 ). Assuming that it is
lossless, then
I 1V1 = I 2V2 (20.11-1)

The assumption that a converter is lossless is a typical idealization caveat, but not unreasonable. The
basic converter topology is represented by figure 20.111 and consists of a series element and a shunt
element. For the direct converter these are switches and for proper operation must be complementary.

Figure 20.111(a) and (b): Basic topology. 12V 9V example

Figure 20.111(c): (I,V) waveforms for the 12V 9V converter

The switching power supply relies on time-averages levels as defined by the duty cycles of its two
switches. The duty cycle DS of the series switch SW1 defines the average voltage level V2 transferred
from the source side to the load side. Switch SW2 keeps the current I2 flowing through the load when
switch 1 is off. For the converter represented by figure 20.111, switch #1 has a duty cycle DS = 0.75
and switch #2 will therefore have complementary duty cycle (1 DS) = 0.25.

V1 is assumed to be a steady levels of voltage. I2 is assumed to be a continued flow of current, as

afforded by SW2. The action of the switches and time-averaging then yields

V2 = V2 (t ) = DS V1 (20.11-2a)

I 1 = I SW 1 (t ) = DS I 2 (20.11-2b)

where x(t ) indicates time averaging. The variation in levels from the switching action are smoothed
over by use of capacitances and inductances. Note that equations (20.11-2a) and (20.11-2b) also obey
the lossless condition (equation (20.11-1)).

The switching is usually executed at sufficiently high frequencies so capacitance and inductances of
modest sizes can be used to smooth out the waveforms. Both of these elements are energy storage
elements, for which capacitances are used to store voltage (in the form Q/C), and smooth out the
voltage waveform. Inductances are used to store current and smooth out the current waveform.

The effects of these components in the circuit are realized by the definitions

dV = dt (20.11-3a)

dI = dt (20.11-3b)

It should be no great revelation that the larger the values of C and L , the smaller the ripple.

Equation (20.11-3b) is also emphasizes that an emf (voltage) will be generated across the inductance
with a change in current. This effect is manifested by figure 20.112 for which an interruption of
current flow such as that caused by a switch induces an emf of magnitude that can easily break-over
the switch gap. In the early part of the century, when many unwary experimenters would hook up a
DC induction motor to a simple knife switch, a panicky yank on the switch to shut off the motor would
create an enormous, dangerous arc, usually sufficient to melt parts of the switch. In modern circuits,
this effect merely annihilates the switching transistor as the overvoltage surges well beyond junction
breakdown. For this reason, many circuits containing an inductance add a snubber to shunt
destructive overvoltage spikes and arcs. Snubbers are even included in digital integrated circuits, since
at high switching speeds, the small inductances due to long interconnects may be sufficient to cause
large overvoltages.
Figure 20.112: Induced voltages in an inductance due to current interruption.

This effect is of advantage in converter circuits because the opening of the controlled switch will
induce sufficient reactive voltage to turn on a reactive switch such as a diode. This action is illustrated
by figure 20.113.

Figure 20.113: Inductive complementary switching by means of a diode.

As indicated by the figure the diode is pulled into forward bias by the emf induced across the
inductance. The diode will therefore serve as the complementary switch to that of the controlled
switch (which usually is a transistor)

A complete converter circuit might then be represented by figure 20.114, which represents the
topology which we usually call a direct converter.

Figure 20.114: The direct converter topology (down converter).

The converter transfer action is defined by the switches. For the topology shown the input voltage is
stored on capacitance C and voltage V1 supplied to the switches = VC. The capacitance is discharged
by a current of magnitude I2 during the interval in which SW1 is on. It is supplied continuously by
current I1 flowing from the input source, as represented by figure 20.115.

Figure 20.115: Charge and discharge current

The drop in voltage on the capacitance over the interval from 0 to DST is then


VC = V1 =
(I 2 I 1 )dt
(I 2 I 1 )DS T = 1 1 I 1 (DS I 2 )T
C 0
C C I2

which is the same as

VC = V1 = (1 DS )T (20.11-4)

since DS x I2 = I1.

Equation (20.114) represents the decrement of VC during discharge or the magnitude of the ripple.
Figure 20.115 illustrates the effect of the capacitance on average voltage V1.

Figure 20.116. Ripple on V1 (= VC ) .

The amplitude of this ripple can also be evaluated by evaluating VC when SW1 is open for which the
capacitance is charged up by a flow of current I1 onto the capacitance. This current causes an
increment of voltage across C of value

VC = V1 =
I 1 dt = (1 DS )T (20.115)

and is the same as that of equation (20.114).

Which is expected and should be no surprise.

Similarly, a ripple in the current I2 will occur as the inductance discharges through the load while SW2
is closed, i.e.
V2 dt = 2 (1 DS )T
I 2 =

This ripple will induce a corresponding ripple in V2, i.e.

V2 = I 2 R2 (20.116b)

EXAMPLE 20.111: The circuit of figure 20.117 shows a direct converter which is supplied by a
source of value VB = 26 V and internal resistance RB = 0.1. RB also acts as the resistive component
of the R-C input filter. It is assumed that the load can be represented by R2 = 0.1. It is switched by a
clock at fs =50 kHz.

(a) What are the converter values I2, V1, and I1 and what duty cycle DS is required.
(b) What values of L and C are needed to keep the current ripple at the output and the voltage
ripple of the input to less than 2%?

Figure 20.117: 26Vto5V direct converter operating at fs = 50 kHz

SOLUTION: For V2 = 5V, we have: I2 = V2/R2 = 5/0.1 = 50 A.

Assuming V1 x I1 = V2 x I2 = 250 W, and I1 = ( 26 V1 )/R1, we get the quadratic:

10V1(26 - V1) = 250

which has solutions V1 = 25 and V1 = 1. Only the solution V1 = 25V makes sense since the other
solution is less than V2 (= 5V). For this value, we then get:

I1 = (26 V1 )/R1 = 10A

The duty cycle DS is then: DS = V2 / V1 = 0.2

The ripple current at the output is, from equation (20.115),

I 2 = .02 50 = 5.0 (1 0.2) 20 s

5.0 0.8 20u

from which the inductance needs to be (at least) L = = 80H
0.02 50
Similarly, from equation (20.114)
V1 = .02 25 = 10 (1 0.2) 20s

10 0.8 20u
from which the capacitance will need to be (at least) C = = 320F
0.02 25


The topology of figure 20.114 in general will end up with the quadratic equation

V1 (V B V1 ) = PL R B

which has solution

V1 =
VB 1 + 1 4 PL R B (20.118)
2 V B2

where only the positive root is valid, required in order that V1 > V2.

The topology represented by figure 20.114 is also called the down converter or buck converter, since
it bucks the voltage down to a lower output level. It has a sister topology that uses the same
principles, called the boost converter or up converter, represented by figure 20.118.

Figure 20.118: The direct converter boost topology.

This converter will take the energy stored in the inductance during the first part of the duty cycle and
dump it into the righthand side of the circuit at a higher voltage induced by the inductance. If DP
represents the duty cycle of the controlled switch, which is now the shunt switch, then current through
the diode results only when the controlled switch turns off. The fraction of the interval for which the
controlled switch is off corresponds to duty cycle (1 DP) for which the diode is toggled into a
conducting state. The conduction current through the diode is therefore

I D = I 2 = (1 D P ) I 1 (20.119)

Since we require that the circuit be lossless, for which I2V2 = I1V1, then, by equation (20.119) the
voltage at the output must be:

V2 = (20.1110)
(1 D P )
Since (1 D) is always less than 1, then V2 > V1, and the converter therefore boosts the voltage.

The voltage across capacitance C is VC = V2. Compare this condition to the buck converter, it was V1
that fell across capacitance C. Therefore, if we designate DS = the duty cycle of the series switch,
which for the boost converter is defined by (20.11-9) as 1 DP, then equations (20.1110) and (20.11
2a) are exactly the same.

This is no coincidence, of course. The topologies are the same, except that figure 20.118 is a right
toleft reflection of figure 20.114. The only difference is in the achoice of the controlled switch and
the diode.

Analysis is therefore entirely the same as for the down converter except that subscripts are
interchanged. Ripple equations for voltage across the capacitance and current through the inductance
are the same as (20.114) and (20.116), except that the subscripts may be interchanged if we adhere
to subscript 1 as being at the input and subscript 2 as being at the output. A comparison is represented
by example 20.112.

EXAMPLE 20.112: Warriorbrand combat underwear uses a muscle electrostimulation (ESM) unit
which requires 72V at 1A to operate in the superman mode. If it is supplied by a 9V battery belt
capable of supplying 50A of shortcircuit current, determine (a) converter values V1, and I1 and duty
cycle D of the controlled switch, (b) values of L and C needed to keep the voltage ripple at the output
and the current ripple of the input to less than 2%, assuming that the circuit is toggled at switching
frequency fs = 50 kHz.

SOLUTION: (a) the output requirement is P2 = PL = I2 V2 = 1A x 72V = 72W.

Assuming that the converter is approximately lossless, I1V1 = I2V2.

In this case we have V1 = VB I1R1, where VB = battery voltage = 9V and R1 = RB = 9V/50A = 0.18.

Therefore (V B I 1 R B ) I 1 = P2 = 72

Which, with values is of the form (9 0.18I 1 ) I 1 = 72

which has solutions I1 = 10A and 40A. Although both solutions will work, I1 = 10A is the more
reasonable one, and will correspond to

V1 = 7.2V and DP = 1 I2/I1 = 0.9

(b) For ripple of less than 2%,

V2 = VC = .02 x 72 = 1.44 V

According to equation (20.11-4) C= (1 DS )T
As far as the topology is concerned DP and (1 - DS) are the same, since both are the fraction of the
cycle for which the two sides are not conjoined. I1 is the current flowing off the capacitance, which
for the boost converter corresponds to that through the load = 1.0A, so that

1 .0
C= (0.9 20 s ) = 12.5F

where we have used T = 1/fs = 20

Similarly for a 2% ripple in input current, and evaluating for the condition that SW1 = ON (and for
which the two sides are disconnected)
I 1 = I L = .02 10 = (7.2 (0.9 20s ))
and which gives L = 648H


The topology of figure 20.118 requires the need of the quadratic equation

(V B I 1 R B ) I 1 = PL

for which the required solutions is

I1 = 1 1 4 PL R B (20.1111)
2RB V B2

Synopsis: For the direct converter (whether up or down), equations (20.11-8) and (20.11-11) are the
benchmarks for the voltage and current transfer from one type of energy storage element to the other
and can be restated as

VC =
VB 1 + 1 4 PL R B (20.1112a)
2 V B2

IL = 1 1 4 PL R B (20.1112b)
2RB V B2

for which VC is the averaged voltage that appears across the capacitance and IL is the averaged current
that flows through the inductance. Equations (20.11-12a) and (20.11-12b) identify the unknown input
level, from which the duty cycle D that is required to accomplish the conversion can then be

The ripple across these elements is defined by the R-C and R-L constants which can be restated in
terms of equations (20.11-4) and (20.11-6a)
VC = DS (off )T (20.11-13a)

I L = D S (off )T (20.1113b)

where the usage identifies that the ripple is stated in terms of current IC that is supplying the
capacitance and voltage VL that is supplying the inductance. The use of Dseries(off) nomenclature
identifies the fraction of the duty cycle for which the two sides of the converter are electrically isolated
from each other as results of the series switch being off.

It is a little more practical to express equations (20.11-13a) and (20.11-13b) in terms of the time
constants C = RC C and L = L/RL , where RC is the resistance in the capacitance path and RL is the
resistance in the inductance path. Using these relationships the ripple equations take the form

VC 1
= t (off ) (20.11-14a)

I L 1
= t (off ) (20.1114b)

In the case of the direct-down converter topology, the resistance in the capacitance path corresponded
to RB and the resistance in the inductance path corresponded to RL. And for the nomenclature used
with this topology, I1 corresponds to IC and I2 corresponds to IL. Take note that VC I C RC for the
down converter.

It is not good practice to assume that the resistance RB of the power source be equal to zero. When it is
assumed then the down-converter will have no need of a capacitance. And the up-converter will
(apparently) have no need of an inductance, which is not true since the inductance is needed to toggle
the reactive switch. The mathematics does become simpler since the duty cycle D is sufficient to
describe the relationships between input and output, since both are then either known or identified by
the load requirement and the source characteristics.

Another topology is the indirect converter represented by figure 20.119. This topology can be either
an up converter or a down converter.

Figure 20.11-9. The indirect (buck-boost) converter topology

If we acknowledge that the time average of voltage over the inductance must be zero, then
V1 DT V2 (1 D)T = 0
so that
V2 D
= (20.11-15)
V1 1 D

where D is the duty cycle of the controlled switch and T is the period of the cycle. Depending on the
value of D, V2 can be either greater or less than V1. We also note that the average capacitance current
must be zero, in which case,

I 2 DT = I 1 (1 D)T

which is the same as

I2 1 D
= (20.11-16)
I1 D

This result just confirms that the (ideal) net power going into the converter should be zero, assuming
that the converter is approximately lossless.

But as is true for the power amplifiers, the converter is not lossless, since some power is dissipated in
the switching components themselves. For the cases represented by figure 20.114 and its cousins,
these are the transistor(s) and the diode(s). Although considerably better than mechanical switches,
these components will have finite turnon and turnoff times during which significant power levels
are dissipated in the switches. The principle is represented by figure 20.1110.

Figure 20.1110: Power dissipation in the switches.

Assuming that a switching transition can be represented by an approximately linear behavior over
transition interval (0 < t < tON) as represented by Figure 20.118, then during this transition time

I (t ) = I ON
t ON

V (t ) = (VOFF VON )1
t ON

The power dissipated in the switch during transition is the timeaverage P (t ) over the switching
interval 0 < t < tON for which

t ON
1 t 1 1 VON
P (t ) =
T 0
I (t )V (t )dt = +
T 6 3 VOFF


where t is the transition time (= either tON or tOFF) and T = 1/fS, with fS = switching frequency.
Equation (20.11-17 is the same for either the ON-OFF or the OFF-ON transition.

The current ION that passes through either one of the switches is always the current through the
inductance. The voltage VOFF across a switch is always the voltage across the capacitance. It should
be no surprise that the energystorage elements define the levels of voltage and current that are
switched on/off by the two complementary switching elements to yield the desired I1,V1 -> I2, V2

Furthermore, the power dissipated when the switch is on is

PD (ON ) = I ON VON (20.11-18)

where D is the duty cycle for the switch, whether defined by external control or defined by the
reflexive nature of the circuit.

Turnon and turnoff times tON and tOFF are a function of the levels of current and voltage, since
these switches must usually be charged up for minoritycarrier injection or the depletion of a drift
region. tON and tOFF are on the order of s for large power transistors and diodes . These response
times are the fundamental limit to the switching speed fs. Also the switches themselves will have a
finite voltage drop, which, as we noted in section 20.3. These may on the order of 1 to 6V for a power
BJT in the ON state. A power diode will have an ON voltage drop on the order of 0.6V to 2.0V.
For lowvoltage converters, as represented by examples 20.111, and 20.112, common offthe
shelf, large BJTs and diodes may be used, for which the voltage drop across the devices is less severe.

EXAMPLE 20.113: Assume that the controlled switch (= BJT) of example 20.111 has VCE (on) =
1.0V, and that the diode has V(on) = 0.6 V. Assume that tON = 1.0s = tOFF for both devices.
Determine the power dissipated in the switches.
SOLUTION: The switching frequency fS = 50kHz, for which 1/fS = 20s. From the example ION = IL
= I2 = 50A and VOFF = VC = V1 = 25V. From equation (20.118) the power dissipated during switch
transitions is then

1.0 s + 1.0s 1 1 1.0

PD1 (transition) = (50 25) + = 22.5W
20s 6 3 25.0

1.0 s + 1.0 s 1 1 0.6

PD 2 (transition) = (50 25) + = 21.8W
20s 6 3 25.0

The power dissipated during the time when the switches are ON is

(0.2 20s ) 1.0s

PD1 (ON ) = (50 A 1.0V ) = 7.5W
(0.8 20 s ) 1.0 s
PD 2 (ON ) = (50 A 0.6V ) = 22.5W
20 s

Therefore the power dissipated budget due loss in the switches is

PD1 = PD1 (trans ) + PD1 (ON ) = 30W

PD 2 = PD 2 (trans) + PD 2 (ON ) = 44.3W

This loss represents a total PD of 74.3 W. Since the power load requirement was 250W, it is necessary
to factor this power loss into the analysis, for which it is apparent that duty cycle D will have to be
increased in order to compensate for the loss in the switches. The process is iterative. If iterations are
carried back and forth between examples 20.8.1 and 20.8.2, with the modification

I 1V1 = I 2V2 + PD

With PD = PD1 + PD2 and a repeat of the analysis, we find that the duty cycle must be increased to D =
0.203. And with this change we also find that V1 increases t 24.62 V

In example 20.113, the change in the duty cycle D due to the power loss in the switches is relatively
minor. The analysis does alert us that we need to have a BJT and a diode capable of dissipating
approximately 30W and 44.3W, respectively. Allowing for safety margins and de-rating via the heat
sinks, this converter can probably be constructed using a 75W power transistor and a 100W diode to
support the 250W load with circuit efficiency 77%.