DFT Q & A- part 1

1. What is sequential Depth In DFT? How does it improve coverage?

Ans: FastScan performs clock sequential test generation if you specify a non-zero sequential
depth.

Clock sequential identification selects scannable cells by cutting sequential loops and limiting
sequential depth based on the -Depth switch. Typically, this method is used to create structured
partial scan designs that can use the FastScan clock sequential ATPG algorithm.

Setting the -Sequential switch to either 0 (the default) or 1 results in patterns with a

maximum sequential depth of one, but FastScan creates clock sequential patterns only if the
setting is 1 or higher.

The maximum allowable sequential depth is 255 (a typical depth would range from

2 to 5).

Coverage Improvement :

Testable faults become ATPG_untestable faults because of constraints, or limitations,

placed on the ATPG tool (such as a pin constraint or an insufficient sequential depth).

These faults may be possible-detectable, or detectable, if you remove some constraint, or

change some limitation, on the test generator (such as removing a pin constraint or changing
the sequential depth).

Also,(while using named capture procedure) gradually add more capture procedures with higher
sequential depth until the test coverage goal is achieved or the pattern count limit is reached.

2. What is the difference between flops and scan flops?

Ans: Difference between scan flop and simple flops becomes more easy to understand when we
know why do we need scan flop!!

Need of scan flop:

The goal of scan design is to make a difficult-to-test sequential circuit behave (during the testing
process) like an easier-to-test combinational circuit. Achieving this goal involves replacing
sequential elements with scannable sequential elements (scan cells/scan flops) and then
stitching the scan cells together into scan registers, or scan chains. You can then use these
serially connected scan cells to shift data in and out when the design is in scan mode.

Before Scan design is difficult to initialize to a known state, making it difficult to both control
the internal circuitry and observe its behavior using the primary inputs and outputs of the
design. In a "Scan design" scan memory elements (scan flops) replace the original memory
elements (normal flops) imparting controllability and observability to the design (prime
requirement for the design being testable), when shifting is enabled.

3. What is robust / non_robust test for path delay faults?

Ans: Non -Robust tests:

A pair of at-speed vectors that test a path delay fault; fault detection is not guaranteed, because
it depends on other delays in the circuit.

Robust Tests:

A pair of at-speed vectors that test a path delay fault independent of other delays or delay faults
in the circuit.

4. What are the techniques used to reduce pattern count without losing coverage ?

Ans: The number of test patterns that you need to achieve full coverage depends on the design
size. Different ATPG tools offer different compression and pattern ordering techniques to help
reduce pattern count.

fault models beyond stuck-at typically require pattern counts that are much larger than those
for stuck-at only.

For Pattern reduction, first step is the chain balancing during Stitching or scan insertion. If your
chains are balanced, Tool needs to insert less dummy patterns for reaching till required flop.

Also we can include compression on the chains where we have constraints on the pins of
device.This means if we are having the compression factor of 2 then your 1 scan chain will get
divided into 2 inside the device reducing your chain length (flops per scan chain).

5. Are the faults on the resets of the flops are detected? if so how are they detected?

Ans: Yes the faults on reset of the flop are detectable. It is detected in the following way
 1) Define the reset pin as clock in the tdl

2) Let us assume that the reset of the flop is active low. Keep the reset as 'high' and scan in '1' in
to the flop (during this scan enable is 'high')

3)As we have scan-in '1' the Q of the flop will have '1'

4) Make the scan-enable 'low' and toggle the reset(i.e. make it low). This is allowed because we
have declared the reset as clock.

5) As reset is 'low' the flop need to get reset and whatever the value in the flop will become '0'

6) Then strobe for '0', while shifting-out the contents from the flop.

7) If the output while shifting out is '0', it means the reset pin of the flop is not stuck-at 1.
Otherwise it is stuck at '1'.

Note:

1. In test mode all the flops should have a asynchronous reset.

2. The reset pins of all flops should be controllable from Top (Chip) level.

If your design contains a lot of synchronous reset flops. Then since during AC (transdly) testing
these reset line faults are not targeted for AC, Constraining the reset to off state is the best way.
2. ues: What is glitch? What causes it (explain with waveform)? How to
overcome it?
Ans:
 3.
4. The following figure shows a synchronous alternative to the gated clock using a data
path. The flip-flop is clocked at every clock cycle and the data path is controlled by
an enable. When the enable is Low, the multiplexer feeds the output of the register
back on itself. When the enable is High, new data is fed to the flip-flop and the
register changes its state
 Ques : A very good interview question... What is difference between setup
and hold time. The interviewer was looking for one specific reason , and its
really a good answer too..The hint is hold time doesn't depend on clock, why
is it so...?
Ans: Setup violations are related to two edges of clock, i mean you can vary the
clock frequency to correct setup violation. But for hold time, you are only concerned
with one edge and does not basically depend on clock frequency
5. Ques :What is Stuck-at fault ?
Ans: A Stuck-at fault is a particular fault model used by fault simulators and
Automatic test pattern generation (ATPG) tools to mimic a manufacturing defect
 within an integrated circuit. Individual signals and pins are assumed to be stuck at
Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state during test
generation to assure that a manufacturing defect with that type of behavior can be
found with a specific test pattern. Likewise the output could be tied to a logical 0 to
model the behavior of a defective circuit that cannot switch its output pin.
6. Ques : What is Clock Gating ?
Ans: Clock gating is one of the power-saving techniques used on many synchronous
circuits including the Pentium 4 processor. To save power, clock gating refers to
adding additional logic to a circuit to prune the clock tree, thus disabling portions of
the circuitry where flip flops do not change state. Although asynchronous circuits by
definition do not have a "clock", the term "perfect clock gating" is used to illustrate
how various clock gating techniques are simply approximations of the data-
dependent behavior exhibited by asynchronous circuitry, and that as the granularity
on which you gate the clock of a synchronous circuit approaches zero, the power
consumption of that circuit approaches that of an asynchronous circuit.
7.
Ques : How to fix the hold/setup violation in scan path (Q to SI path)?
8. Ans : If the violations are small, as in most designs with well balanced clock trees,
the place and route tools can generally fix these by adding small buffers/inverters.
Some smart scan reordering tools will take a slightly farther scan flip-flop to avoid
hold problems.
If the violations are big, due to large clock skews, the best way to solve this is to add
a data lockup latch.
I have always wondered why scan chain reordering tools don't take clock skew
information into consideration. Not sure if the latest tools uses this vital information.
9. I think the tools look first to reduce congestion, by reducing the number of clock
buffers in the scan path, which will minimize hold time violations, but there are
always some left, so your process has to include a step where the post-route netlist
is re-analyzed for timing (both mission and scan mode), and any hold violations left
in the scan path are manually fixed.
10.
11. Ques : I have 3 types of flops in my design.
1. CLK domain posedge
2. CLK domain negedge
3. RCO_CLK domain posedge only.
Is it feasible/possible to put them in 1 scan-chain ?
12.
13. Ans: Yes, it is possible.
Assuming that CLK is a Return-to-Zero clock (0->1->0 pulse), you would stitch the
negedge CLK domain flip-flops before posedge CLK domain flip-flops, i.e., negedge
CLK FFs are closer to scan input, and posedge CLK FFs are closer to scan output.
RCO_CLK domain can be stitched at either end of the chain. However, if CLK has a
significantly larger clock tree than RCO_CLK clock tree, then it is better to put
RCO_CLK domain FFs at the end of the chain. Otherwise, you may need to skew your
 clock timing on the ATE.
This means your chain will look like this:
ScanIn -> negedge CLK -> posedge CLK -> RCO_CLK -> ScanOut
14. Ques:----- Can any body tell me

1) What causes HOLD VIOLATIONS in DESIGN.

2) How it effects DESIGN.

3) What changes need to be done to make DESIGN work.

15.
16. Ans:----
17. Hi Friend,

1) What causes HOLD VIOLATIONS in DESIGN.

Simply, data should be hold for some time (hold time) after the edge of the clock. So, if the
data changes with the hold time might cause violation. In general, hold time will be fixed
during backend work (during PNR) while building clock tree. If u r a frontend designer,
concentrate on fixing setup time violations rather than hold violations.

2) How it effects DESIGN.

If a chip is done with some setup violations it can work by reducing the frequency.
If achip is done with hold violations, JUST DUMP the chip. This is how it effects at the end of
the day. Hold vilations needs to be fixed.

3) What changes need to be done to make DESIGN work.

PNR tools will route and place the cells in such a way that no timing violations will occur. If
still u face hold violations, u can manully work on it to fix. Manually place the cells to
avoid hold violations, or in the worst case, u can keep some buffers in the datapath to
avoid hold violations (but be sure setup timing is not effected.)
18.
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20.
21. you said "If achip is done with hold violations, JUST DUMP the chip. "
>why can't reducing the frequency to settle the hold violation as setup violation ?
>could you explain it clearer ?

Equation for Setup Time

Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter

Equation for Hold Time

Tclktoq + Tlogic - Tskew > Thold
 Note that Hold Time equation is independent of clk frequency(i.e Time period Tclk)

key things to note from above equations

a) once the silicon comes back , if u have setup time problem , u can
increase the clock period (Tclk) to fix it , whereas if u have hold
time problem , its a more serious problem and u will need a new
metal fix tapeout . ( But u can still test the current chip using Low supply voltage,
or High temperature or SS corner part that decrease hold time violation
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