DIGITAL ELECTRONICS

CP-15 IIIRD SEM, JNTC (GOPALPUR)

1st chapter(Introduction)
1. Only two voltages are present in a ____________ electronic circuit.
a. analog
b.digital
c.both a & b
d.none of these.
~end~

2. An analog device is one in which data is represented by _________.

a.Physical variable
b.constant
c.both a & b
d.none of these.
~end~

3. In a digital system all the electronic components operate in a ____________mode.

a.analog mode
b. variable mode.
c.switching mode
d. neutral mode.
~end~

4. Digital computers function in the ______________ number system.

a. logarithmic
b. exponential
c. decimal
d. binary
~end~

5. A sequential logic circuit consists of

(a) Only FFs
(b) Only gates
(c) FFs and combinational logic circuits
(d) Only combinational logic circuit
~end~

2nd chapter
(Number system & codes)
6.Conversion from decimal- to- octal is usually done by ____________division.
a. receprocal
b. successive
c. both a & b
d. none of these.

~end~
7. The binary number 101010 equals ________________ in decimal.
a. 42
b.23
c.24
d.53
~end~

8.The binary number system is sometimes called the _________system.

a.base-1
b.base-2
c.base-8
d.base-10
~end~

9.ASCII stands for ____________.

a. American standard for information interchange.
b. American standard for interchange information.
c. American stand for information interchange.
d. Automatic standard for information interchange.
~end~

10.Grey code is ____________ bit change code.

a.1
b.3
c.2
d.4
~end~

11. Add the following BCD numbers--- 1001 and 0100=___________.

a.1101
b.0101
c.1100
d.1001
~end~

12.Equivalent Gray code representation of AC2.is _____________.

A. BCD
B.F46
C.2FD
D.59E
~end~

13.10s complement of 245 is_________.

A.245
B.754
C.755
D.756
~end

3rd chapter
(Logic gates)
14) The maximum number of gates (load ) that can exist without impairing the normal
operation
of the gate is known as..
a) Fan-in
 b) Fan-out

c) speed

d) none of these

~end~

15) A quantitative measure of noise immunity is called .

a) noise analyser

b) noise identifier

c) noise margin

d) none of these

~end~

16) The circuits ability to tolerate noise without causing spurious changes in the output
voltage is known as .

a) noise immunity

b) noise identifier

c) noise margin

d) none of these

~end~

17.The output of AND gate, if one of its input terminals is connected to logic 0, is
_______________.
A.0
B.1
C.both a & b
D.none of these
~end~

18.A NOR gate is equivalent to a ____________ AND gate.

A.positive
B.negative
C.both a & b
D.none of these

~end~

19.The ___________ gate can perform an AND function and an OR function.

A.NAND
B.NOR
 C.both NAND/NOR
D.none of these
~end~

20.The ___________ level is the active output level for the AND gate.
A.high
B.low
C.both a & b
D.none of these
~end~

21.____________ is a measure of noise immunity.

a.microdecible
b.picodecible
c.decible
d.none of these
~end~

22.NOT gate is also called as ____________.

a.universal gate
b.equality gate
c.unequality gate
d.inverter
~end~

23. The maximum number of logic i/ps that an o/p of a logic gate can drive is specified in
______.

(a) fan in
(b) fan out
(c) tPHL
(d) tPLH
~end~

24. The fan-in of a gate is equal to the number of _____ which can be connected to
it.
a.gate i/ps
b.gate o/ps
c.both a & b
d.none of these
~end~

25. If a logic gate has a fan out of 4, than the gate

(a) has 4 i/ps
(b) can drive a maximum of 4 i/ps
(c) has 4 o/ps
(d) gives o/p 4 times the i/p.
~end~

26. The figure of merit of a logic family is given by

(a) gain * band width
(b) propagation delay time * power dissipation
(c) fan-out * propagation delay time
 (d) noise margin * power dissipation
~end~

27. The number of standard i/p loads that can be driven by an IC is called its ______.
a.power dissipation
b.fan in
c.noise margin
d.fan out
~end~

28. Which of the following parameters is not specified for digital ICs?
(a) gate dissipation
(b) propagation delay
(c) noise margin
(d) band width
~end~

4th chapter
(Boolean algebra & karnaugh map)
29.A+AB = ___________.
(a)B
(b)C
(c)A
(d)1
~end~

30.A 3 variable K-map has _____________cells.

(a)2
(b)9
(c)6
(d)none of these
~end~

31.Complement of a variable is always its_______.

a.inverse
b.equal
c.may/maynt equal
d.none of these
~end~

32.Distributive law states that_____________.

a.A+B=B+A
b.AB=BA
c.A(B+C)=AB+AC
d.none of the above
~end~

33.Simplify the expression AB + A( B + C ) + B ( B + C )= ____________.

a.A+BC
b.B+AC
c.C+AC
d.A+B+C
~end~
34.5 variable karnaugh map has_______ cells.
a.8
b.10
c.16
d.32
~end~

35.Give an example of SOP form?

a.(A+B)(B+C)
b.AB+BC+CA
c.both a & b
d.none of the above
~end~

36.According to assosiative law ________.

a.A+B=B+A
b.AB=BA
c.A(BC)=AB(C)
d.A(B+C)=AB+AC
~end~

37.On karnaugh map grouping of 0s produces_______.

a.SOP expression
b.POS expression
c.both
d.none of these
~end~

38.A logic circuit with an output X=ABC+AC consist of ______ gates, _______gates and
_______inverters.
a.two,one,two
b.three,two,one
c.one,two,three
d.two,one,three
~end~

39.(A+B)(A+C)=_________.
a.B
b.A+B
c.C
d.ABC
~end~

40.An n variable K-map will have __________ number of cells.

a.2n
b.n
c.2n
d.2n+2
~end~
 5th chapter
(Combinational logic circuit)
41.According to assosiative law ________.
a. AB=BA
b. A+B=B+A
c. A(BC)=AB(C)
d. None of these
~end~

42.A logic circuit with an output X=ABC+AC consist of ______ gates, _______gates and
_______inverters.
a.one, one and one
b.one, two and one
c.two , one and two
d.none of these
~end~

43.The OR operations can be produced with two_______gates or three_______gates.

a.NAND,NOR
b.NOR,NAND
c.AND,OR
d.NAND, NOT
~end~

44.The AND operation can be produced with two_________gates.

a. AND
b. OR
c. NOT
d. NAND
~end~

45.___________&____________ are universal gates.

a.OR & AND
b.EX-OR & EX-NOR
c.NAND & NOR
d.none of the above
~end~

46.A NAND gate becomes ___ gate when used with negative logic ?
a.NOR
b.AND
c.OR
d.NOT
~end~

47.OR operation can be produced by _______gates.

a.NOR
b.NAND
c.both NAND & NOR
 d.None of the above
~end~

48.________is known as a universal gate as can be used to implement all Boolean

expressions.
a.NOR
b.NAND
c.both NAND & NOR
d.None of the above
~end~

49.The OR operations can be produced with two_______gates or three_______gates.

a.AND,NOT
b.NOT,AND
c.NOR,NAND
d.none of these
~end~

50.The AND operation can be produced with two_________gates.

a.OR
b.NOT
c.NAND
d.NOR
~end~

51.A half adder is characterized by _____inputs and______ outputs.

a.2,3
b.3,2
c.2,2
d.4,4
~end~

52.A multiplexer has ___________data inputs,________data outputs and selection inputs.

a.one,several
b.several,one
c.2,3
d.4,2
~end~

53.A full adder is characterized by _______inputs and_____outputs.

a.1,2
b.2,3
c.3,2
d.2,4
~end~

54.A 4 bit parallel adder can add ___________4 bit binary numbers.
a.5
b.2
c.4
d.3
~end~
55.Data selectors are basically same as _________
a.multiplexers
b.encoder
c.demultiplexer
d.decoder
~end~

56.A full adder is a circuit which adds _________bits at a time.

a.5
b.3
c.2
d.4
~end~

57.A 3-bit counter is also called as MOD ____ counter.

a.8
b.3
c.2
d.4
~end~

58.Frequency division is an application of ______.

(a) decoder
(b) encoder
(c) multiplexer
(d) flip-flop
~end~

59.An 16-input MUX should have ___________ number of selection lines.

a.1
b.3
c.2
d.4
~end~

6th chapter
(latches & flip flop)
60.__________is the output when the input of a D-flip flop is tied to the output through
the XOR gate .
a.0
b.1
c.both
d.none of these
~end~

61._________ number of flip flops are required to produce a divide by 32 device ?

a.4
b.5
c.6
d.7
~end~
62.Preset and clear are called as ___________ inputs.
a.DC set and DC clear
b. previous and clear.
c. both a and b
d.none of these
~end~

63.Flipflop is an example of ____________.

a. combinational switching
b. sequential switching
c. both a and b
d.none of these

~end~

64.The input frequency of MOD10 counter is 10 KHz, and then output frequency is _____.
a.1 Hz
b. 1k Hz
c. 10 kHz
d. none of these
~end~

65.IIL stands for _______________ family.

a. Integrated injection logic
b. Integrated industrial logic
c. inverted industrial logic
d. none of these
~end~

66.the maximum count that a MOD 35 counter can count in binary is___________.
a.32
b.64
c.34
d.61
~end~

67.To SET a JK FF, what should be the values at its i/ps J and K?
a.J=1,K=1
b.J=1,K=0
c.J=0,K=0
d.none of the above
~end~
~
68.To RESET a JK FF, the values at J and K is ______.
(a) 0and 1
(b) 1 and 0
(c) 1 and 1
(d) 0 and 0
~end~

69. In a JK FF (j=k=1, Q=0 and Q=1), after the occurrence of 3rd clock pulse,
what will be the values of Q and Q?
 a.Q=1,Q=1
b.Q=0,Q=0
c.Q=1,Q=0
d.Q=0,Q=1
~end~

70. To count the numbers form 00 to 11 serially, the number of clock pulses required is
______.
a.1
b.3
c.2
d.4
~end~

71. Preset and Clear i/ps of JK ff are called as ______ set and reset i/ps.
a.synchronous
b.Asynchronous
c.both (a),(b)
d.none of the above
~end~

72. The table which shows the necessary levels at J and K i/ps to produce every possible FF
state transition is called _______ .
(a) truth table (J-K)
(b) state transition table
(c) excitation table (J-K)
(d) FF transition table.
~end~

73. How many FFs are required for a counter to count (0)10 to (255)10?
a.2
b.4
c.8
d.16
~end~

74.A group of FFs used for data storage is called _______.

a.counter
b.converter
c.register
d.none of these
~end~

75.A FF is used to store _________ .

(a) one bit
(b) two bit
(c) one byte
(d) one nibble
~end~

76.A word is _____ bit data.

a.2
 b.4
c.8
d.16
~end~

77.A memory of 8K means

(a) 108
(b) 8000
(c) 8*1024
(d) 5*103
~end~
7th chapter
(Timer & timing circuit)

78.Monostable Multivibrator is also called as ________.

a. Free Running Generator
b. Monoshot
c. Both a & b
d. none of These
~end~

79.Clock signal is a ___________in wave nature

a. Sine Wave
b. Saw tooth Wave
c. Square Wave
d. None of these
~end~

8th chapter
(Sequential logic circuit)
80. A mod N counter divides the clock pulse frequency f into a value ____.
a.N/f
b.f/N
c.1/N
d.1/f
~end~

81. A mod-5 counter divides the clock pulse frequency 20Khz into _____ Hz.
a.1K
b.3K
c.2K
d.4K
~end~

82 If the asynchronous i/ps PRESET=0 and Clear=1 of a JK FF, than Q o/p will be
_____
a.1
b.3
c.2
d.4
~end~

83. If the asynchronous i/ps PRESET=1 and Clear=0 of a JK FF, than Q o/p will be
 _____.
a.1
b.3
c.2
d.4
~end~

84.493 IC is _____ bit binary counter IC.

a.1
b.3
c.2
d.4

~end~

85.A 7493 IC can be used as a maximum Mod counter of_____.

(a) mod-4
(b) mod-8
(c) mod-16
(d) mod-12
~end~
86. A mod-10 counter is also called as _____ counter.
a. decade
b. mode
c. both a and b
d. none of these
~end~

87. A decade counter divides the clock pulse frequency f into _____.
(a) f/2
(b) f/5
(c) f/10
(d) f/8
~end~

88. A counter which counts the binary numbers from 0000 to 1001 is also
called as ______ counter.
a. BCD decade
b. Synchronous
c. Asynchronous
d. None of these
~end~

89. Cascading of a mod-3 and mod-5 counters, result a counter of overall mod
number ______.
a.5
b.10
c.15
d.20
~end~

90. Two or more counters can be cascaded to produce overall mod number equal to
the _______ of the individual mod numbers.
 (a) sum
(b) difference
(c) product
(d) division
~end~

91. The number of 7493 IC require to design a mod-50 counter is ____.

a.1
b.3
c.2
d.4
~end~

92. 7490 is a ripple _____ counter IC.

a.MUX
b.DEMUX
c.decade
d.None of these
~end~

93. If an asynchronous counter is designed with 4 JK FFs of propagation delay time 50ns
each,
than the total propagation delay time is _____.
a.100ns
b.200ns
c.150ns
d.20ns
~end~

94. Synchronous counter is also called as _______ counter.

a. serial
b. parallel
c. both a and b
d. none of these
~end~

95. If a 3-bit parallel counter designed with JK FF of propagation delay time 20ns, than
overall delay will be ______.
a.3ns
b.6ns
c.20ns
d.200ns
~end~

96. In the JK FF excitation table, to change Q o/p from Q(N)=1 to Q(N+1)=0, what will
be the J and K value require?
(a) 0 and X
(b) 1 and X
(c) X and 1
(d) X and 0
~end~
97. To change Q o/p of JK FF from Q(N)=0 to Q(N+1)=1, what will be values for J and K
i/ps require?
a.1 & 1
b.0 & 0
c. 1 & X
d. 0 & X
~end~

98. The number of decade counters are required to convert a clock frequency of 10Mhz to
100hz is _____.
a. 2
b. 4
c. 7
d. 6
~end~

99. Cascading four counters of mod numbers 10,6 and 8 produces the overall mod
number is equal to _____.
a. 480
b. 24
c. 10
d. 6
~end~

100.Which of the following is a sequential logic circuit?

(a) decoder
(b) multiplexer
(c) flip-flop
(d) counter
~end~

101.A 2-bit counter is also called as MOD ____ counter.

a.3
b.2
c.1
d.4
~end~

102.An asynchronous counter is also called as ______.

a. binary counter
b. ripple counter
c. both a and b
d. none of these
~end~

103.To design a N-bit counter, the number of FFs required is ______.

a. 2N
b. 2N
c. N
d. none of these
~end~

104.A counter counts the number of _____.

 a. clock pulses
b. flip flop
c. input state
d. none of these
~end~

105. The maximum MOD number of a counter having N FFs is _____.

a. 2N
b. N2
c. 2N
d. 2N -1
~end~

106. A 4-bit counter starts counting at 0000, then what will be the counting number after
5th pulse.
a. 5
b. 0101
c. 1010
d. 0110
~end~

107. Is it true or false, in an asynchronous counter all FFs changes state at the same
time?
a.true
b.false
~end~

108. In a ripple down counter, the clock i/p of a FF is connected to _____ o/p of a
previous FF.
(a) Q
(b) Q
(c) Both Q and Q
(d) Q.Q
~end~

109. What is the MOD number of a counter which counts the numbers from (0) 10 to
(127)10?
a. 127
b. 7
c. 10
d. 128
~end~

110. Which one of the following is a unused state in the decade counter?
(a) 0111
(b) 1000
(c) 0101
(d) 1011
~end~

111.To convert a 4-bit mod-16 counter to a mod-12 counter, the ffs must be reset when the
counter reaches the number _____.
a. 1101
b. 1100
c. 1111
d. 0000
~end~

112. The maximum number of states that a counter with six filp-flops can count is ____
(a) 6
(b) 8
(c) 64
(d) 256.
~end~

113.The input frequency of MOD10 counter is 10 KHz, and then output frequency is _____.
a. 0.001MHz
b. 0.000001GHz
c. Both a & b
d. None of These
~end~

114. The minimum number of FFs required to construct a mod-10 ripple counter is ____.
(a) 2
(b) 4
(c) 6
(d) 10
~end~

115. A BCD counter has

(a) 12 distinct states
(b) 10 distinct states
(c) 9 distinct states
(d) 4 distinct states
~end~

116. 74163 is a _______ IC.

a. synchronous 4-bit binary counter
b. asynchronous 4-bit binary counter
c. both a and b
d. none of these
~end~

117. The terminal count of mod-13 counter is _______.

a. 1100
b. 1101
c. 1011
d. 0000
~end~

118. 74193 IC is a synchronous 4 bit binary _____ counter IC.

(a) up
(b) down
(c) up/down
 (d) up/down presettable
~end~

119. The maximum mod number counter can be obtained from a 74193 IC is ____.
a.12
b.8
c.16
d.32
~end~

120. If U/D i/p of 74190 IC is kept at high, than the counter IC is being used as ____
counter.
a.up
b.down
c.up/down
d.none of these
~end~

121. A _____ shift register is one in which data can be moved internally in either direction.
a.Biderectional
b.unidirectional
c.Both a and b
d. none of these
~end~

122. The type of a register, in which data is entered into it only one bit ata time but has all
data bits available as o/p is
(a) SIPO register
(b) PISO register
(c) SISO register
(d) PIPO register
~end~

123. A ______ shift register is one that has both serial and parallel i/ps and o/ps.

a. Universal
b.Parallel
c.Both a&b
d.None of these
~end~

124. A register with four FFs, can store up to ____ bits of data.
a. 16
b. 4
c. 8
d. 1
~end~

125. To enter 1010 into a 4 bit serial-in, serial out shift register, the number of clock
pulses to be applied is _______.
a. 10
b. 9
c. 11
 d. 4
~end~

126. To shift a 4-bit data completely from a 4bit SISO register, the number of clock pulses
to be applied is _____.
a. 15
b. 8
c. 16
d. None of These
~end~

127.______ type of register can have data entered into it only one bit ata time , but has all
data bits available at o/ps.
a.SISO
b.SIPO
c.PIPO
d.PISO
~end~

128. IC 74164 is a 8-bit ______ register IC.

a.SISO
b.SIPO
c.PIPO
d.PISO
~end~

129.74164 IC is a _____ bit SIPO register.

a.12
b.6
c.10
d.8
~end~

130. _____ bit of data can be shifted out at a time by using 74165 IC.
a. 1
b. 4
c. 8
d. 16
~end~

131. A ring counter is constructed by ______ register.

(a) SISO
(b) SIPO
(c) PIPO
(d) PISO
~end~

132. A n-bit ring counter can count _____ numbers.

(a) n2
(b) 2n
(c) n
(d) 2n
~end~
133. A johnson counter is constructed by ______ register.
(a) SISO
(b) SIPO
(c) PIPO
(d) PISO
~end~

134. A twisted ring counter is also called as ______ counter.

a. Ripple
b. Johnson
c. Decade
d. Ring
~end~

135. A n FF ring counter is a mod _____ counter.

a. n
b. 2n
c. 2n
d. n-1
~end~

136. A johnson counter designed with n FFs can have ____ number of different states.
a. 2n
b. n
c. 2n
d. n-1
~end~

137.A johnson counter with n FFs is a mod ______ counter.

a. 2n
b. n
c. 2n
d. n-1
. ~end~

138.After 4 clock pulses, a Johnson counter o/p from 0000 will change to ______.
(a) 1000
(b) 1100
(c) 1110
(d) 1111
~end~

139. Which of the following components is used for storing binary information
(a) A register
(b) A latch
(c) A flip-flop
(d) all of the above
~end~

140. If in a shift register with N ffs , Q(inverted o/p) is fed back to i/p the resulting counter
is
(a) twisted ring with mod N
(b) ring counter with mod N
 (c) twisted ring with mod 2N
(d) ring counter with mod 2N
~end~

141. A ring counter is same as

(a) Up/down counter
(b) Parallel counter
(c) Shift register
(d) Ripple counter
~end~

142. speed in synchronous counter is more than asynchronous counter.

a) False
b) true
c) neither false nor true
d) either false or true

~end~

143. In mod 80, counts starts from to

a) 0 - 80
b) 0 - 81
c) 0 - 79
d) none of these

~end~

144. Asynchronous counter also known as

a. counter
b. register
c. ripple counter
d. parallel counter

~end~

145. Synchronous counter also known as

a. counter
b. register
c. ripple counter
d. parallel counter

~end~

146. Which one the following is 4 bit asynchronous decade counter

a. 7493
b. 7490
c. 74163
d. 7495

~end~
147. Which one the following is 4 bit asynchronous binary counter.

a. 7493
b. 7490
c. 74163
d. 7495

~end~

148. Which one the following is 4 bit synchronous presettable binary counter.

a. 7493
b. 7490
c. 74163
d. 7495

~end~

149. Which one the following is 4 bit presettable up/down binary counter.
a. 7493
b. 7490
c. 74163
d. 74193

~end~

150. Which one the following is 4 bit presettable up/down BCD counter.

a. 7493
b. 7490
c. 74163
d. 74192

~end~

151. Speed of a counter is depends on ..

a. glitches
b. accuracy
c. propagation delay
d. none of these

~end~

152. MOD 10 counter also referred as .

a. decade counter
b. binary counter
c. ripple counter
d. none of these
 ~end~

153. Which one of the following counter is used to divide the frequency ,

a. synchronous counter
b. asynchronous counter
c. parallel counter
d. all the above

~end~

154. Pre-settable counter can be preset to any desired starting count either asynchronously
or synchronously

a) false
b) true neither false nor true
c) true
d) either false or true

~end~

155. pre-setting operation also known as

a. loading counter
b. clearing counter
c. resetting counter
d. none of these

~end~

156. Asynchronous preset is independent of the clock signal

a. false
b. true neither false nor true
c. true
d. either false or true

~end~

157.IC 74165 is a 8 bit ______ register.

a. PIPO
b. PISO
c. SIPO
d. SISO
~end~

158. synchronous preset is independent of the clock signal

a. false
b. true neither false nor true
c. true
d. either false or true
 ~end~

159. Which one of the Pre-settable counter, can be preset to any desired starting count on
active transition of the clock signal,

a. synchronous preset
b. asynchronous preset
c. synchronous reset
d. none of these

~end~

9th chapter
(Data converters)
160.. 74193 IC can be presettable _______.
A.asynchronously,
B. synchronously
c. either false or true
D.None

~end~

161.. A D/A converter consists of a(n)______ network and a(n) _____ amplifier.

a. Resistor , Summing
b. Resistor , instrumentation
c. Capacitor , Summing
d. Inductor,Inverting
~end~

162. The voltage levels for a six bit binary ladder are 0=0V, 1= +10v, its o/p for the i/p
101001 will be
(a) 4.23V
(b) 5.52v
(c) 6.41v
(d) 9.23v
~end~

163. An eight bit digital data 10101100 is fed to an DAC, the reference voltage is +10
volts. The analog o/p voltage will be
(a) 1.05v
(b) 6.71 v
(c) 10.10v
(d) 11.11v
~end~

164. What is the resolution of a nine bit D/A converter which uses a ladder network in
percentage
(a) 1
(b) 2
(c) 4
 (d) 10
~end~
165. Percentage of resolution of 2 bit DAC is ..

a. 33.33%
b. 14.28%
c. 6.66%
d. none of these

~end~

166. Percentage of resolution of 4 bit DAC is ..

a. 33.33%
b. 14.28%
c. 6.66%
d. none of these

~end~

167. Percentage of resolution of 8 bit DAC is ..

a. 33.33%
b. 14.28%
c. 6.66%
d. 0.39%

~end~

168. The percentage of resolution of a DAC depends only on the no. of bits.

a. True
b. false
c. neither false nor true
d. none of these

~end~

169. The maximum deviation of the DAC output from its expected value is called ......

a. half scale error

b. final scale error
c. full scale error
d. none of these

~end~

170. full scale output is 10v, accuracy 0.01%, the full scale error is ..
a) 2 mv
b) 1mv
c) 5mv
d) 0v
 ~end~

171. The minimum deviation in step size from ideal step size is called .

a. nonlinearity error
b. linearity error
c. full scale error
d. none of these

~end~

10th chapter
(Integrated logic families)
(3.0)
172.. For successive approximation , with N o/p bits number of clock required is
(a) N+2 or N
(b) 2N+1
(c) 2N
(d) 2N+1
~end~

173.. TTL stands for _____.

a. Transistor to transistor logic
b. Transistor to triac logic
c both a and b
d. none of these
~end~

174.. In TTL, the voltage range for logic 1 is

(a) 2v-5v
(b) 3v-5v
(c) 2.5v-5v
(d) 0v-0.8v
~end~
175.. CMOS stands for ____.
a. composite metal oxide semiconductor
b. complementary metal oxide semiconductor
c. both a and b
d. none of these

~end~

176.. ECL stands for _____.

a. Emitter Coupled log
b. Emitter Complement logic
c. both a and b
d. none of these
~end~

177. CMOS has _____ power dissipation.

 a. Very high
b. Very low
c. Moderate
d. None of these
~end~

178.. The i/p signal to a TTL NAND gate travels through three stages of internal
circuitry: i/p, control and _____.
a. totem pole o/p
b. totem pole i/p
c. both a and b
d. none of these
~end~

179.0. RTL consists of

(a) resistors, transistors and inductors
(b) resistors and transistors
(c) resistors, diodes and transistors
(d) resistors, capacitors and diode.
~end~

180. Which of the following logic families has the least propagation delay ?
(a) RTL
(b) CMOS
(c) DTL
(d) I2L
~end~

181. Which of the following logic families dissipates minimum power ?

(a) ECL
(b) CMOS
(c) DTL
(d) TTL
~end~

182. The main advantages of TTL with totem pole o/p as compared to other TTL types are
(a) higher fan-in and fan-out
(b) fast switching and low power dissipation
(c) higher noise margin and low cost
(d) none of these.
~end~

183. Which of the following logic families has complementary o/p ?

(a) DTL
(b) TTL
(c) I2L
(d) ECL
~end~

184. Which of the following logic families has maximum fan-out ?

(a) CMOS
(b) PMOS
(c) ECL
 (d) I2L
~end~

185. The logic family best suited for high noise level industrial environment is
(a) TTL
(b) HTL
(c) MOS
(d) ECL
~end~

186. An i/p of +3.1v to a TTL IC would be considered _____.

(a) High
(b) Low
(c) Undefined
(d)none of these
~end~

187. The bipolar technology giving the fastest logical family is

(a) DTL
(b) TTL
(c) ECL
(d) None of these.
~end~

188. The recommended fan out for a TTL gate is

(a) 10
(b) 15
(c) 20
(d) 25
~end~

189.EEPROM stands for _______.

a. electrically erasable programmable read only memory.
b. electromechanically erasable programmable read only memory.
c. easy erasable programmable read only memory.
d. None of these
~end~

190.A 32*8 memory can hold _____ words.

a. 32
b. 16
c. 8
d. 256
~end~

191.A_____ memory can be erased easily.

a. RAM
b. ROM
c. Both a &b
d. None of these
~end~

192. Semiconductor memories are

 (a) Volatile
(b) Nonvolatile
(c) Volatile, small size
(d) Nonvolatile, small size

~end~

193.RAMs are used in computers for the _____ storage of programs and data.

a. Permanent
b. Auxiliary
c. Temporary
d. None of these
~end~

194. Clock signal is a ___________in wave nature.

a. Rectangular
b. Square
c. Both a & b
d. None of these
~end~

195.) What does ROM stand for?

a) Read One Memory

b) Random Optic Memory
c) Requires One Mind
d) Read Only Memory
~end~

196. What does RAM stand for?

a) Read Access Memory

b) Random Access Memory
c) Random Optic Memory
d) Requires One Mind
~end~

197. What does SRAM stand for?

a) Static Read Access Memory

b) Static Random Access Memory
c) Static Random Optic Memory
d) Static Requires One Mind
~end~

198. What does DRAM stand for?

a) Dynamic Read Access Memory

b) Dynamic Random Access Memory
c) Dynamic Random Optic Memory
d) Dynamic Requires One Mind
~end~
199. What does the term PLD stand for?

a) Programmable Logic Device

b) Program List Device
c) Programmable Array Logic
d) Piezo Array Lamp
~end~

200. What does EPROM stand for?

a) Erasable Programmable Read-Only Memory

b) Elective Programmable Read-Only Memory
c) Erasable Programmable Random-Only Memory
d) none of these
~end~

201. An 0/p of 0.5v from a TTL IC would be considered _____.

(a) High
(b) Low
(c) Undefined
(d).None
~end~

202.A full adder accepts __________ inputs and produce _________ outputs.
a.2,3
b.3,2
c.3,3
d.3,1
~end~
 ANSWER

1. b
2. a
3. c
4. d
5. c
6. b
7. a
8. b
9. a
10. a
11. a
12. b
13. c
14. b
15. c
16. a
17. a
18. b
19. c
20. a
21. c
22. d
23. c
24. b
25. b
26. b
27. b
28. d
29. a
30. d
31. a
32. c
33. b
34. d
35. b
36. c
37. b
38. a
39. b
40. c
41. c
42. c
43. b
44. d
45. c
46. b
47. c
48. c
49. c
50. c
51. c
52. b
53. c
54. b
55. a
56. b
57. a
58. d
59. d
60. b
61. b
62. a
63. b
64. a
65. a
66. c
67. b
68. a
69. c
70. b
71. b
72. c
73. c
74. c
75. a
76. c
77. c
78. b
79. c
80. b
81. d
82. a
83. a
84. d
85. c
86. a
87. c
88. a
89. c
90. c
91. c
92. c
93. b
94. b
95. c
96. c
97. c
98. d
99. a
100. d
101. d
102. b
103. c
104. a
105. c
106. b
107. a
108. b
109. d
110. d
111. b
112. c
113. c
114. b
115. b
116. a
117. a
118. d
119. c
120. b
121. a
122. a
123. a
124. b
125. a
126. c
127. b
128. b
129. d
130. a
131. a
132. c
133. a
134. b
135. a
136. c
137. c
138. d
139. d
140. c
141. c
142. b
143. c
144. c
145. d
146. b
147. a
148. c
149. d
150. d
151. c
152. a
153. d
154. c
155. a
156. c
157. b
158. a
159. a
160. a
161. a
162. c
163. b
164. b
165. a
166. c
167. d
168. a
169. c
170. b
171. b
172. a
173. a
174. a
175. b
176. a
177. b
178. a
179. c
180. d
181. b
182. b
183. d
184. a
185. a
186. a
187. c
188. a
189. a
190. b
191. b
192. c
193. c
194. b
195. d
196. b
197. b
198. b
199. a
200. a
201. b
202. b