CAD Tools for Course

Specification and Simulation of Digital Systems

In the course you shall use the Xilinx ISE Environment to simulate, synthesize and
implement your designs.

Xilinx Environment
GUI/Environment: Xilinx ISE 14.7
VHDL Simulator: ISim or ModelSim Student Edition 10.4a
Synthesis: Xilinx XST 14.7Implementation: Xilinx ISE 14.7

Note: Xilinx ISE Webpack 14.7 requires special start-up procedure when used with
Windows 8 or Windows 10.

1. Option 1: When you install Xilinx ISE, it gives you the option to run either 32 or 64-bit
version of the tool. Along with that, it gives you the Command prompt utility to invoke
any of the two versions of ISE. Open utility for the 32-bit version and type ise to start
this version. This procedure will ensure the error free operation of the tool during
simulation, synthesis and implementation.

Option 2: Follow the complete guidelines (file 03 Get Xilinx ISE Webpack 14.6 to work
on Windows8.pdf). The original text refers to ISE Webpack 14.6 and Windows 8, but it
also works for ISE Webpack 14.7 and Windows10.

To work on your PC/laptop, download and install Xilinx Webpack 14.7 following the steps
described in the file 01 ISE Design Suite 14.7 Installation Tutorial.pdf.

In case you prefer to use ModelSim PE Student Edition (@home)

How to install and set up ModelSim PE Student Edition (@home):

a. Go to this link: https://www.mentor.com/company/higher_ed/modelsim-student-edition

b. Click on the tab Download Student Edition.
c. Once you downloaded it, install it.
d. At the end of the installation, the tool will now redirect you to the license page of the
ModelSim PE
e. Fill out the form and click on the Request License button. Please use your Polito e-
mail ID.
f. An e-mail will be sent to your e-mail ID.
g. Save the attached file with the name 'student_license.dat' to the top level installation
directory for ModelSim PE Student Edition (e.g., c:/modeltech_pe_edu). This is the
directory that contains that sub-directory 'win32pe_edu.'
h. Do not edit the file 'student_license.dat' in any way, or the license will not work.
i. You should now be able to run ModelSim PE Student Edition.

Adding ModelSim PE Student Edition in Xilinx ISE (@home):

All ModelSim simulator editions are configured in Xilinx ISE using the Integrated Tools
page of the Edit => Preferences dialog box. To configure ModelSim or confirm your
configuration settings:

Open Xilinx ISE.

Select Edit => Preferences.
In the left-pane window of the Preferences dialog box, expand the ISE General
hierarchy.
Click Integrated Tools.
On the Integrated Tools page, set the Model Tech Simulator field by browsing to the
location of modelsim.exe

(e.g.:C:\Modeltech_pe_edu_10.3c\win32pe_edu\modelsim.exe).

Replacing ISim with ModelSim PE during simulation (@home):

When you create a new project in ISE:

a. A New Project Wizard Dialog box opens.

b. In this box, under the Simulator option select ModelSim-PE VHDL.
c. Now you should be good to use ModelSim Simulator.

How to set up Xilinx Environment

Start Xilinx ISE Webpack 14.7

To start a new Project go to the menu File->New Project

Specify Project Name and location for project files

Click Next and specify

Family : Spartan6
Device : XC6SLX4
Package : TQG144
Speed Grade : -3
Simulator : ISim
Click Finish

Your project should contain at least 1 VHDL source file for your design and 1 VHDL
testbench file. You can:
Use your favorite editor to create the VHDL sources (design + testbench) and then add
them to your project
Create the VHDL sources (design + testbench) from within ISE and then add them to
your project.

The following sections briefly describe the two alternatives.

How to add existing VHDL source files

To add VHDL sources to the design, right click at the name of the FPGA device (e.g.,
xc6slx4-3tqg144) under Hierarchy and select Add Source. Choose files for the project.

In this tutorial you shall use files fulladder.vhd and its testbench fulladder_tb.vhd.

The next window shows you the files being added to the project and their status.
Then click OK. Your project has been defined. Your project consists in a design
(fulladder.vhd) and in its testbench (fulladder_tb.vhd).

How to create a VHDL source

1. Click the menu Project/New Source.

2. Select VHDL Module as the source type.
3. Type in the file name that you want to create. For example, myfulladder.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for your design by filling in the port information as in the following
figure.
7. Click Next (re-verify the summary of the port declarations), and then Finish to
complete the new source file template.

The source file containing the entity myfulladder and its architecture is displayed in the ISE
environment, and in the Hierarchy tab appears as Top Module for the current design.
Remember, in projects containing multiple source files, if one accidentally changes the top
module entity, you can reset it as a top module by right click on a source in Hierarchy, and
select Set as Top Module.

Attention: the parent of the myfulladder entity in the hierarchy is formed by the properties
of the FPGA target device. With this Xilinx environment setup, you must see xc6slx4-
3tqg144. If it does not coincide, this means that you have probably skipped step 6.

Make sure that the proper VHDL libraries are included in the source file header. You now
have 2 alternatives:
1. Edit the VHDL Source Code
2. Use VHDL Language Templates
Then follow the Save, Check, Synthesize & Display steps.

Editing the VHDL Source Code:

1. Add component and/or signal declarations between the architecture and the begin
statements.
2. Add the rest of the code (component instantiation, behavioral description, etc.) after the
begin statement and before the end statement.
3. For this example add the following statements after begin for a dataflow description of
the fulladder:
sum <= (a XOR b) XOR cin;
cout <= (b AND cin) OR (a AND cin) OR (a AND b);
Using VHDL Language Templates:
Language Templates includes VHDL synthesizable examples that you can use in your
designs:
1. Place the cursor under the begin statement of your architecture.
2. Open Language Templates by selecting the menu Edit Language Templates
3. Navigate in the hierarchy +, to the coding examples: VHDL Synthesis
Constructs
4. Select the desired component in the hierarchy, then right click Use in File. This step
will copy the model code to your source file at the place of your cursor. For this
example select Process Combinatorial
5. Close the Language Templates.
6. Change the signal names so that they will match the signals in your entity.

Save, Check, Synthesize & Display:

1. Save the file by selecting File Save or Ctrl + S.
2. Select the top-level entity in the Hierarchy tab: myfulladder.
3. Verify that your VHDL syntax is correct: in the Processes zone: Synthesize XST
double click Check Syntax
4. Correct the errors if they appear in the bottom part of the ISE environment. Start from
the top with the first error.
5. Synthesize your design: double click Synthesize XST
6. View the resulting circuit: double click Synthesize XST View RTL Schematic. In
the next dialog be sure to select the second variant (Start with a schematic of the top-
level block), press OK. The top-level entity will appear.

Double click to view its internal organization. You should recognize at least a part of
the declared entity. This is a first method to verify that your code is correct and
implements the desired circuit. Simulation is the topic of a further Section.
Read this schematic as follows:
The 2-input a_b_AND_1_o1 gate implements ab
The 2-input Mxor_a_b_XOR_1_o1 gate implements a XOR b
The 2-input cin_ a_AND_2_o1 gate implements cin(a XOR b)
The 2-input cout1 gate implements ab + cin(a XOR b) that is equivalent to bcin + acin +
ab, i.e. the carry-out
The 2-input Mxor_sum1 gate implements (a XOR b) XOR cin, i.e. the sum.

You have now created the VHDL source for the myfulladder project with no errors.

How to create and add a testbench

As an alternative you can create your own testbench file and add it to your project. This
section shows how to create a new test bench file and modify it by editing it with
statements from fulladder_tb.vhd. Follow these steps:

1. Highlight your project as seen in the figure below and then click on the New Source
button
2. In the new dialog box that appears, select VHDL Test Bench from the list of file types
and enter myfulladder_tb as the file name

The default location is the current project directory and can be left as is. Ensure the Add to
Project box is selected and click the Next button. You will then see a screen with your file
name associated to the simulation.
Verify the information in the next few dialog boxes and click Next then Finish.

A new file will be associated with your project in the Hierarchy pane (myfulladder_tb.vhd)
and a skeleton VHDL file with new information will be shown in the Workspace panel on
the right hand side of the screen.
7. Edit the VHDL testbench file. Notice that the entity is already there and that the
architecture is partially filled (the component declaration and instantiation and the interface
signals, though not compliant with the standard used in the course (signalname_s) are
already there). As the design is purely combinational, there is no need for the clock
process. Just paste the stimuli found in fulladder_tb.vhd in the stim_proc process. As an
alternative, open Language Templates by selecting the menu Edit Language
Templates. Navigate in the hierarchy +, to the coding examples: VHDL Simulation
Constructs. Select the desired component in the hierarchy, then right click Use in File.
This step will copy the model code to your source file at the place of your cursor.
If you attempt to close the testbench file in the Workspace panel on the right hand side of
the screen a new window will pop as seen below. Press Yes to ensure you save the file.

How to simulate a design

Now that you have a testbench in your project, you can perform behavioral simulation on
the design using ISim. The ISE software has full integration with ISim. The ISE software
enables ISim to create the work directory, compile the source files, load the design, and
perform simulation based on simulation properties.
In the view you have either Implementation or Simulation highlighted. Use the
Implementation mode when you want to design a circuit in VHDL. Switch to Simulation
mode when you want to simulate your design.

Clicking on the designs name in Implementation mode opens the VHDL file of the
design.

Doing the same in Simulation mode opens the corresponding testbench.

There are several options in Simulation mode:
1. Behavioral Simulation (which is performed before you synthesize your circuit)
2. Post Translate Simulation (which is performed after synthesis but before you
implement the design)
3. Post Map Simulation (which is performed after implementing the design, i.e., mapping)
4. Post Route Simulation (which is performed after mapping, placement and routing).

In this tutorial we will only look at and use Behavioral Simulation (i.e., prior to synthesis).

Behavioural Simulation

ISim is a simulation tool integrated into Xilinx ISE. You can use ISim to debug and verify
your designs.

Click on the radio button for Simulation. Then highlight the top level Testbench. Then
double click Simulate Behavioral Model in Processes Menu.

ISim should now be running, and you should see a window similar to the following:
Move the cursor close to time 0 and zoom in (F8, see later for view commands) until you
obtain a suitable view like the next one:

There are four main sections in the ISim display:

A. Instances and Processes: Contains a hierarchical list of all component
instantiations in the design you are simulating.
B. Objects: Displays all signals, constants, variables in a selected component in your
design.
C. Waveform: Displays waveforms for selected signals.
D. Console: Displays compilation messages and any text output from your testbench
 and the following icons are used:
design hierarchy icons:

design objects icons:

signals

buses

Running Simulations
You can run a simulation using the simulation toolbar:

From left to right, these buttons perform the following functions:

1. Restart: Restarts a simulation from the beginning without recompiling design files. Use
this if you have added more signals and wish to see their waveforms, but you have not
changed any of your design files
2. Run All: Runs for an unspecified amount of time.
3. Run For Specified Time: Runs for the amount of time specified in the adjacent box.
4. Step: A useful tool in debugging code, allows the user to step through their design as
it executes.
5. Break: Stops the simulation that is currently running.
6. Re-launch: Recompiles the design. This is useful to use when you have made
changes to the code and wish to re-run your simulation.

Adding Signals to the Waveform

By default the waveform window begins with the signals from your top-level file, which is
the testbench. To add signals from your design to the waveform views, select the
component containing the signals from the Instances and Processes window and then
select the signals of interest. Right click on the signals and then choose Add to Wave
Window. To add all signals from a particular component, right click on the component in
the Instances and Process window and choose Add to Wave Window. To view the
waveforms for these signals, you must restart the simulation. Click the Restart button in
the simulation toolbar and re-run your simulation.

Waveform Format
If the timescale of the waveform is such that you cannot read the values of some of the
signals. To zoom in, use the Zoom toolbar:

The functions in this toolbar are (left to right):

1. Zoom In
2. Zoom Out
3. Zoom Fit: Fits entire waveform into window
4. Zoom to Cursor: Zooms in, centered at the location of the cursor.

Some other useful options are:

The functions in this toolbar are (left to right):

1. Go to previous transition moves the main cursor to the previous transition.
2. Go to next transition moves the main cursor to the next transition.
3. Adds a marker at the position of the main cursor to the waveform area.
4. Moves the main cursor to the nearest marker to the left of the main cursors current
position.
5. Moves the main cursor to the nearest marker to the right of the main cursors current
position.

With more complicated designs, your waveforms will often contain a large number of
signals. To keep your waveform organized and readable, you may wish to group related
signals together. To do so, select the signals you wish to group, right-click and select
New Group
The result is a group of signals that can be hidden when not being used and visible when
needed. Give a name to the new group, e.g. outputs in this case. You can also create
dividers to classify signals. Dont forget to name the new divider:
You will often want to measure the duration of an event, or the time between two events.
One way to do this is by using markers. Markers serve as reference points and can be
used to measure time intervals. The commands in the marker toolbar are:

1. Create Marker
2. Move Cursor to Previous Marker
3. Move Cursor to Next Marker

Clicking on a placed marker will display the time relative to that marker. In the example
below, you can see that signal sum_s stays high for 20 ns. We measured this by placing a
marker when the signal rose to 1 and another one when it fell to 0.

A shortcut is to click on the waveform at the desired time and then drag the mouse curson
to the end point of the interval.

Saving Waveform Format

When you close ISim, the simulation data you were using is lost. You will need to rerun the
simulation the next time you start ISim in order to recreate the data. It is therefore a good
idea to always save the waveform format of your simulations so that you do not have to
add all of your signals and create and groups, dividers, or buses every time you wish to
run the simulation. To save the waveform format, go to File Save As and save your
waveform as a .wcfg, the native format for ISim waveform configurations.
Taking a print out and saving the waveform in a PDF file
Under File menu, click on "Print" option. You can either choose the entire length of
simulation or specify the range of simulation. It is very important to specify whether you
want the output on single or multiple pages.

Take a print out by choosing any third party tool to create a PDF file of the waveform.
Here is a sample of the waveform output saved in the PDF file.